JPH0754616B2 - Digital signal processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital VTR, and more particularly to a digital signal processing apparatus suitable for application to a digital audio signal processing circuit of a reproducing circuit thereof.

[Outline of Invention]

The present invention relates to a digital signal processing apparatus suitable for being applied to a digital VTR, and particularly to a digital audio signal processing circuit of a reproducing circuit thereof, in which a block-coded digital signal is edited at an arbitrary edit point in a block and obtained. The stored digital signal is stored in the memory, it is determined whether the number of samples of each block of the digital signal is out of the specified number of samples, and when the block whose count value is out of the specified number of samples is detected, By repeatedly reading a block of a prescribed number of samples from the memory instead of the abnormal block, it is possible to correct the block coding collapse due to editing.

[Conventional technology]

Referring to FIGS. 2 and 3 below, the conventional digital VT
Electronic editing in R, especially editing of digital audio signals will be described. In the case of the NTSC system in the digital VTR, for example, one frame of digital video signal is divided into five, and each segment video signal is formed on two magnetic tracks by a rotary magnetic head. 2) or 4) of the digital audio signal
The channel portion is recorded at the end portion or the middle portion of each inclined track. Two pairs of magnetic heads each having an angle of 180 degrees are used as the rotary magnetic heads for recording and reproduction.

By the way, as a format of the digital audio signal, there is a format according to the AES / EBU standard. Here, AES is an abbreviation for AUDIO ENGINEERING SOCIETY (Audio Technology Association) and EBU is an abbreviation for EUROPEAN BROADCASTING UNION (European Broadcasting Union). The format of this digital audio signal will be described with reference to FIG.

Figure 2 shows one subframe (one sample), which
It consists of 32 bit signal, 4 bit sync signal (or preamble), 4 bit auxiliary data, 20 bit digital audio sample data and 1 bit audio sample validity (V), user bit data (U ), Audio channel status (C), and subframe parity (P). Then, 192 subframes (samples) are collected to form one block.

In this case, in particular, 192 1-bit audio channel statuses of each subframe are gathered to form channel status data. This channel status data is a block signal of 192 bits, that is, 24 bytes, and the data contents are additional information of audio data, time code data, and CRC check code. Therefore, this channel status data will not be completed unless the audio channel statuses of 1 bit for each of consecutive 192 subframes are prepared.

Therefore, when electronically editing a digital audio signal, a part of the channel status data is missing. This point will be described with reference to FIG. FIGS. 3A and 3B show signals having different data contents of the above digital audio signal, which are represented by blocks O1, O2, O3,
... and blocks N1, N2, N3, ..., and the phases between the blocks are different from each other. Therefore, when electronic editing is performed so that the digital audio signal of FIG. 3A is switched to the digital audio signal of FIG. 3B at the point α, a new digital audio signal as shown in FIG. 3C is obtained. . Looking at this signal, the block consisting of each part in blocks O2 and N2 is longer than 192 samples. Further, it may be shorter than 192 samples depending on the phase of the blocks of both digital audio signals and the edit point.

[Problems to be solved by the invention]

In this case, there is no problem with the audio data, but the channel status data of the block at this edit point is incomplete. Such a problem occurs not only in digital audio signals but also in block-coded digital data in general.

In view of such a point, the present invention proposes a digital signal processing apparatus capable of correcting block coding collapse in a digital signal obtained by editing block-coded digital data at an arbitrary editing point in a block. Is what you are trying to do.

[Means for solving problems]

The digital signal processing apparatus according to the present invention transmits asynchronously to each other, and similarly obtains a third block signal obtained by editing first and second block-coded first and second digital signals at arbitrary edit points in respective blocks. (3) in which the digital signal of (3) is stored, counting means (9) for counting the number of samples of each block of the third digital signal, and whether the count value of the counting means (9) deviates from the specified number of samples. And a count value determining means (10) for determining whether or not a block having a count value deviating from a specified number of samples is detected, the memory (9) is controlled to replace the abnormal block with a specified sample. The feature is that a number of blocks are read out repeatedly.

[Action]

According to the present invention, when a block whose count value is out of the specified number of samples is detected, the memory (9) is controlled to repeatedly read the specified number of blocks instead of the abnormal block. There is no risk of the block coding of the signal being broken.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.
In this embodiment, the present invention is applied to a component digital VTR. The digital signal reproduced from the rotary magnetic head is separated into a digital video signal and a digital audio signal. This digital audio signal is the AE described above.
The S / EBU standard signals are recorded on the magnetic tape as 16-bit digital audio sample data and 4-bit signals V, U, C, P or 18-bit digital audio of each subframe. Sample data and 2
These are bit signals U and C. This digital signal is the electronically edited signal shown in FIG. 3C described above, and is subjected to signal processing such as block sync signal detection, horizontal error correction, deshuffling, etc., and then from the input terminal (1). It is supplied to a vertical error correction circuit (2) and a counter (9) for counting audio channel status. Circuit (2)
Output memory (3) is supplied. This memory (3) is a memory for matching the phase of a digital audio signal with a digital video signal. On the other hand, the count value of the counter (9) is supplied to the count value determination circuit (10), and it is determined whether or not the count value matches the specified value 192.

When the judgment circuit (10) judges that the count value does not match the specified value, the judgment output is supplied to the memory controller (11) to control the memory (3), and the third As shown in FIG. D, instead of the abnormal block consisting of a part of the blocks O2 and N2, the block O1 having the next specified sample number is read twice.

The digital audio signal read from the memory (3) is supplied to the format forming circuits (5) and (6) of the AES / EBU via the modifying circuit (4) and the signals of the format shown in FIG. To be done. That is, this circuit (5),
In (6), the digital signal portion not recorded on the magnetic tape is added. And the output terminals (7), (8)
The digital audio signals of the first and second channels and the digital audio signals of the third and fourth channels are output to the respective channels.

Incidentally, when the editing points of both digital audio signals in FIGS. 3A and 3B are selected at the boundary of one block as shown by β and γ in the figure, an uncertain block of the digital audio signal obtained by editing is selected. Can be reduced.

Further, since the data contents of each block of the digital audio signal are the same except for the time code signal, the time code error caused by the repetition of the same block can be solved by rewriting this, and there is no problem.

Instead of the abnormal block, a CRC error flag may be set for a block having a specified number of samples read from the memory (9).

In the above embodiments, blocking coding of channel status data has been described, but the same can be applied to user data.

〔The invention's effect〕

According to the present invention described above, it is possible to obtain a digital signal processing device capable of correcting a block coding collapse in a digital signal obtained by editing block-coded digital data at an arbitrary editing point in a block. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a format diagram of a subframe, and FIG. 3 is an explanatory diagram of electronic editing. (3) is a memory, (5) and (6) are format forming circuits, (9) is a counter, (10) is a count value determination circuit,
(11) is a memory controller.

Claims (1)

[Claims] 1. Storage of a third digital signal obtained by editing first and second digital signals which are transmitted asynchronously to each other and are likewise block coded, at arbitrary editing points in the respective blocks. Memory, counting means for counting the number of samples in each block of the third digital signal, and count value determining means for determining whether or not the count value of the counting means deviates from a specified sample number. However, when a block whose count value deviates from the specified number of samples is detected, the memory is controlled to repeatedly read the specified number of blocks instead of the abnormal block. Signal processing device.