JPH0752857B2 - Eco-Cancer circuit - Google Patents

Description

The present invention relates to an echo canceller circuit in a pair cable digital transmission system, and particularly to a relatively short distance (for example, 1
The echo canceller circuit is realized with a relatively simple configuration for the purpose of transmission of up to 2 km.

[Conventional technology]

FIG. 2 shows an example of a conventional echo canceller circuit. In this example, the number of transversal filter taps is four. In the figure, 201 is a coder circuit, 202 is a line driver, 203 is a hybrid circuit, 204 is a shift register,
205 to 212 are digital multipliers, 213 to 216 are register circuits,
217 to 221 are digital adders, 222 is a digital-analog converter (DAC), 233 is an analog adder circuit, 224 is an analog-digital converter (ADC), and 225 is a pair cable.

In the figure, the binary transmission data (takes a value of "0" or "1") is inverted in polarity by the coder circuit 201 according to "1,0" of the transmission data and is converted into a waveform suitable for transmission. The line driver 202 performs level conversion and impedance conversion so that the line can be driven, and the hybrid circuit
It is sent to the pair cable 225 via 203.

At this time, due to the unbalanced portion of the hybrid circuit 203, a part of the transmission signal goes around to the reception side. This wraparound signal is superimposed on the reception signal sent from the transmission unit of the opposite device at the reception unit and deteriorates the reception S / N. In order to remove the loop-in signal, a signal (echo replica) simulating the loop-in signal is generated, and the analog adder circuit 223 subtracts it from the received signal on which the loop-in signal is superimposed to extract only the received signal. However, conventionally, the signal after cancellation is digitized in the ADC 224, and each output signal of the shift register 204 and each of the multipliers 205 to 212 are integrated in each integration circuit including the multiplication register circuits 213 to 216 and the addition circuits 217 to 220. , The echo replica corresponding to each time position is corrected and held in each register, the past transmission data held in the shift register 204 is multiplied by the contents of each register in the multipliers 209 to 212, and then the adder 221 To create a digital echo replica, and then add the digital-analog converter 222.
, An echo replica is generated by converting into an analog signal.

[Problems to be solved by the invention]

Conventionally, by performing arithmetic in a digital circuit, various problems that occur when realized in an analog circuit, for example,
Noise, gain error, DC offset, leakage, etc. can be avoided, and it has the advantage of enabling highly accurate echo replica generation.
There is a problem in that a digital-analog converter is required.
In particular, it is difficult to realize high-speed and high-accuracy ADCs and DACs. Also,
When the sneak signal is not so large compared to the level of the received signal from the opposite device, that is, the amount of suppression of the sneak signal in the hybrid circuit is sufficient, the line length of the pair cable is short, and the received signal level is low. When the value is high, there is a problem that the digital method may not be advantageous in terms of cost performance because it does not require a highly accurate echo replica as in the case of digitally realizing an echo canceller. is there.

[Object of the Invention]

An object of the present invention is to solve the above problems of the conventional circuit and to realize an echo canceller circuit suitable for relatively short distance transmission with a simple structure.

[Means for solving problems]

The echo canceller circuit of the present invention comprises a shift register for shifting binary transmission data, conversion means for converting the transmission data to a predetermined level and impedance, and a hybrid circuit for outputting the output of the conversion means to a pair cable. And an analog adder having one input of the received data and the echo component of the transmitted data input from the pair cable via the hybrid circuit, and a first buffer for inverting and amplifying the output of the analog adder. An amplifier, a second buffer amplifier for non-inverting amplification of the output of the analog adder, a capacitor, and a tap of the shift register, each of which is connected only when the transmission data at the tap has one value. A first analog switch that is closed to provide the output of the first buffer amplifier to the capacitor. H, a second analog switch that closes only when the transmission data at the tap has the other value and supplies the output of the second buffer amplifier to the capacitor, and a third buffer that non-inverts and amplifies the output held by the capacitor. An amplifier, a fourth buffer amplifier that inverts and amplifies the output held by the capacitor, and a third buffer amplifier that closes only when the transmission data at the tap has one value and supplies the output of the third buffer amplifier to the analog adder.
And a plurality of tap circuits having a fourth analog switch that closes only when the transmission data at the tap has the other value and applies the output of the fourth buffer amplifier to the input of the analog adder. It is characterized by having.

〔Example〕

FIG. 1 shows an embodiment of an echo canceller circuit according to the present invention. In the figure, 101 is a coder circuit, 102 is a line driver, 103 is a hybrid circuit, 10
Reference numeral 4 is a shift register, 105 is a tap circuit, and the tap circuit 105 is composed of components shown by reference numerals 106 to 115. 106 is an inverter circuit, 107 to 110 are analog switches, 111 is a non-inverting buffer amplifier, 112 is an inverting buffer amplifier, 1
Reference numeral 15 is a resistor, 114 is a capacitor, and 113 is a resistor. 11
6 is an inverting buffer amplifier, 117 is a non-inverting buffer amplifier, 118 is an analog adder, and 119 is a pair cable.
It should be noted that the tap circuit 105 uses the same N circuits depending on the number N of used taps. In FIG. 1, 101 coders, 1
The line driver 02, the hybrid circuit 103, the shift register 104, and the analog adder circuit 118 are indicated by 201 in FIG.
The same function as the coder, the line driver 202, the hybrid circuit 203, and the analog adder circuit 223.

In FIG. 1, the transmission data is sent to the pair cable 119 through the coder 101, the line driver 102, and the hybrid circuit 103, and at the same time, a part of the data wraps around to the receiving side. The transmission data is also input to the shift register 104.
If the transmission data in the shift register 104 is “1”,
The analog switch 109 is in a closed state (state in which an analog signal passes), and the cancel signal held in the capacitor 114 is maintained by the non-inverting buffer amplifier 111 while maintaining the same polarity as the voltage held in the capacitor 114, so that an appropriate value can be obtained. After level conversion and impedance conversion, the analog conversion circuit 118 is supplied to the analog addition circuit 118 via the resistor 115. On the contrary, when the transmission data in the shift register 104 is “0”, the analog switch 110 is closed, and the cancel signal held in the capacitor 114 has a reverse polarity in the inverting buffer amplifier 112 and the resistor 115 is passed. And is supplied to the analog adder 118. By the above operation, an echo replica having a polarity that always cancels the sneaking signal according to the polarity of the transmission waveform is generated. In the same process for other taps, the echo replica corresponding to the position of each tap (however, the polarity is opposite to the actual echo) is applied to the resistor 11
Occurs on output of 5.

The residual echo output from the adder 118 is passed through the inverting and non-inverting buffer amplifiers 116 and 117 to the analog switch 10
It becomes the input signal of 7,108. This analog switch 107,108
Opens and closes according to "1" and "0" of the transmission data held in the shift register 104. That is, when the transmission data in the shift register is “1”, the analog switch 107 is closed, and the signal of the opposite polarity of the residual echo is supplied via the resistor 113 to hold the capacitor 114. The voltage is modified. When the transmission data of the shift register is “0”, the analog switch 108 is closed, and the residual echo is not inverted and the resistor is turned on.
It is supplied to the capacitor 114 via 113 and the holding voltage is corrected. Due to the above operation, the voltage of the capacitor 114 is the buffer amplifier 111, 112, the analog switch 109, 11
When 0 is supplied to the analog adder circuit 118 via the resistor 115, the echo cancellation is always controlled in a more accurate direction.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, it is possible to realize a sneak signal from the transmitting section to the receiving section with a very simple circuit without using an analog-digital converter or a digital-analog converter. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional example. 101 …… coder circuit, 102 …… line driver, 103 ……
Hybrid circuit, 104 ... Shift register, 105 ... Tap circuit, 106 ... Inverter circuit, 107-110 ... Analog switch, 111 ... Non-inverting buffer amplifier, 112 ...
… Inverting buffer amplifier, 113 …… resistor, 114 …… capacitor, 115 …… resistor, 116 …… inverting buffer amplifier, 117 …… non-inverting buffer amplifier, 118 …… analog adder, 119 …… pair cable.

Claims (1)

[Claims] 1. A shift register for shifting binary transmission data, conversion means for performing predetermined level conversion and impedance conversion on the transmission data, a hybrid circuit for outputting the output of the conversion means to a pair cable, and An analog adder having one input of the reception data and the echo component of the transmission data input from the pair cable via the hybrid circuit; and a first buffer amplifier for inverting and amplifying the output of the analog adder, A second buffer amplifier that non-inverts and amplifies the output of the analog adder, a capacitor, and each tap of the shift register, each of which is closed only when the transmission data at the tap has one value. A first analog switch, which provides the output of the first buffer amplifier to the capacitor, is connected to the tap. A second analog switch that closes only when the transmission data has the other value to give the output of the second buffer amplifier to the capacitor, a third buffer amplifier that non-inverts and amplifies the output held by the capacitor, and the capacitor. Buffer amplifier for inverting and amplifying the held output of the second buffer amplifier, a third analog switch which closes only when the transmission data at the tap has one value, and supplies the output of the third buffer amplifier to the analog adder, and A plurality of tap circuits each having a fourth analog switch that closes only when the transmission data at the tap has the other value and applies the output of the fourth buffer amplifier to the input of the analog adder. Echo canceller circuit.