JPH0752584B2 - MOS type charge / discharge circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type charge / discharge circuit for charging / discharging a large-capacity load, and more particularly to a MOS type charge / discharge circuit capable of controlling rise and peak of charge / discharge current. Charge / discharge circuit

(Prior Art) Conventionally, in a synchronous MOS memory, an operation of charging and discharging a large-capacity load in a chip, for example, an operation of sensing and restoring a dynamic random access memory is often performed. In such a case, a rapid rise of the power supply current and a high peak of the power supply current due to the charging / discharging operation cause power supply noise inside the chip, which causes a defect of the memory and deterioration of the operation margin. In order to prevent such a situation from occurring, measures have been conventionally taken to suppress the rise of the power supply current and the high peak of the power supply current. For example, K.Sh
imohigashi et al., “A 65ns CMOS DRAM with a Twisted
Drivelin Sense Amplifier ", ISSCC87 Digest p.18 ~ p1
There is a method as seen in 9. This is an MO that charges in the sense amplifier drive circuit as shown in FIG.
Divide the S transistor into MOS transistors Q1, Q2, Q3,
The transistors Q1, Q2, Q3 are driven by P-channel sense enable signals SEP1, SEP2, SEP3 having a phase difference. The drive timing is performed as shown in FIG. 4, and the peak of the power supply current is divided into three small peaks, which are superimposed.

(Problems of Prior Art) However, the above method has the following problems. First, many elements such as delay circuits DC1, DC2, and DC3 are required, which increases the chip area. Secondly, since the number of elements increases, the element parameters increase, which makes it difficult to perform optimum design. For example, the delay time of the delay circuits DC1, DC2, DC3 and the sizes of the three MOS transistors Q1, Q2, Q3 must be designed carefully. Thirdly, when the device parameter changes so that the conductance of the MOS transistor becomes large, the peaks corresponding to the MOS transistors Q1, Q2, and Q3 become large, respectively, and the P channel Since the phase difference between the sense enable signals SEP1, SEP2, SEP3 also becomes small, the waveform of the power supply current as a whole shows a higher peak.

(Object of the Invention) The present invention has been made to solve the above-described problems, and has a small number of elements, excellent designability and controllability, and a MOS type charge / discharge circuit capable of driving a large capacity load. It is intended to provide.

(Means for Solving Problems) (Structure of the Invention) In the present invention, the source terminals of the first and second P-channel MOS transistors are connected to the power supply terminal, and the drain terminals of the second P-channel MOS transistors are connected. A capacitive element is connected to a load circuit including a sense amplifier, and the drain terminal and gate terminal of the first P-channel MOS transistor and the gate terminal of the second P-channel MOS transistor are commonly connected to a ground terminal via a resistor. Is connected to the gate terminal of the second P-channel MOS transistor,
The threshold voltage of the second P-channel MOS transistor is set to be approximately equal, and the channel width of the second P-channel MOS transistor is set to f times the channel width of the first P-channel MOS transistor.

(Operation of the Invention) As described above, according to the present invention, the threshold voltages of the first and second P-channel MOS transistors are set to be substantially equal, and the channel width of the second P-channel MOS transistor is set to the first P-channel MOS transistor. Therefore, the charging current flowing through the second P-channel MOS transistor is f times the current flowing through the first P-channel MOS transistor and the resistor.

(Embodiment) An embodiment according to the present invention will be described with reference to the drawings. FIG. 1 (a) shows an embodiment of a MOS type charge / discharge circuit according to the present invention. P-channel MOS transistor Q1, Q
The source terminals of Q2 and Q3 are connected to the power supply terminal, and the gate terminal of the transistor Q1 is connected to the sense enable terminal SEN. The drain terminal of the transistor Q3 is connected to a load circuit LC composed of a plurality of sense amplifiers S / A, and the drain terminals of the transistors Q1 and Q2 and the gate terminals of the transistors Q2 and Q3 are connected to a capacitor C which is a capacitive element. There is. The drain terminals of the transistors Q1 and Q2 and the gate terminals of the transistors Q2 and Q3 are connected to one end of a resistor R, and the other end of the resistor R is an N-channel transistor.
Grounded through Q4. The gate terminal of the transistor Q4 and the gate terminal of the transistor Q1 are both connected to the sense enable terminal SEN. The sense enable terminal SEN is also connected to the gate terminal of the N-channel MOS transistor Q5. Load circuit LC is P channel
It is connected to the drain terminal of the transistor Q3 via the common source terminal SAP, and is also connected to the drain terminal of the transistor Q5 via the N-channel common source terminal SAN. The sense amplifier S / A forming the load circuit LC is as shown in FIG. 1 (b).

The operation of the MOS type charge / discharge circuit according to the present invention having the above configuration will be described. This will be described with reference to the timing chart shown in FIG. First, in the initial stage, the sense enable terminal SEN is at a low level, the N-channel MOS transistor Q4 is off, and the P-channel MOS transistor Q1.
Is on. At this time, the capacitor C is charged, and the potential at the connection point SEP between the gate terminals of the transistors Q2 and Q3 and the capacitor C is at a high level, and the transistors Q3 and Q4 are off. When the sense enable terminal SEN becomes high level, the transistor Q4 is turned on and the charge charged in the capacitor C is discharged through the resistor R. The electric charge at the capacitor C is discharged, so that the potential at the connection point SEP drops. The transistors Q2 and Q3 are turned on by the decrease of the potential of the connection point SEP, and when the current flowing through the transistors Q2 and Q3 and the current flowing through the resistor R are balanced, the connection point SE
The potential of P becomes constant. The time during which the potential at the connection point SEP becomes constant is determined by the product of the capacitance of the capacitor C and the resistance value of the resistor R.

At this time, assuming that the impedances of the transistors Q2 and Q4 are sufficiently smaller than the impedance of the resistor R, the potential at the connection point SEP is VCC− | VTP, where the power supply voltage VCC and the threshold voltage of the transistor Q2 are VTP. |

Therefore, the bias current IB flowing through the transistor Q2, the resistor R, and the transistor Q4 is IB = (VCC- | VT |) / R (1).

On the other hand, the charging current IC flowing through the transistor Q3 is IC = IB × (WQ3 / WQ2) (2).

Where WQ3 is the channel width of transistor Q3, WQ2
Is the channel width of the transistor Q2.

The expression (2) is established because the source potential (VCC) and the gate potential (SEP) of the transistors Q2 and Q3 are common.

As is clear from the equations (1) and (2), the charging current IC is
It is determined only by the dimensional ratio of the channel widths of the transistors Q2 and Q3, the resistance value of the resistor R, the power supply voltage VCC, and the threshold voltage VTP of the transistor Q2. In addition, the rising waveform of the power supply current is the resistance R
And the time constant of the capacitor C alone. In the description of the embodiment, the case where the transistors Q2 and Q3 are P-channel MOS transistors has been described, but the present invention is not limited to the above, and the transistors Q2 and Q3 are N-channel MOS transistors.
Of course, it can be applied to a transistor.

(Effects of the Invention) The MOS type charge / discharge circuit according to the present invention has a smaller number of circuit elements than the conventional one, and can reduce the pattern area in the chip, and (1), ( As is clear from the equation 2), the resistance value of the resistor R and the transistors Q2 and Q3
The current peak value can be set accurately by determining the dimension ratio of the channel width. Further, the rising characteristics of the current can also be controlled accurately by setting the capacitance of the capacitor C to an appropriate value.

Furthermore, in the MOS type charge / discharge circuit according to the present invention,
Equation (2) is determined by the dimension ratio of the channel widths of the transistors Q2 and Q3, that is, the geometric pattern dimension,
The equation (1) only depends on the resistance value of the resistor R and the threshold voltage of the transistors Q2 and Q3, and there is little variation due to device parameters. Therefore, it is not affected by the fluctuation of the device parameters.

[Brief description of drawings]

FIG. 1 (a) is a circuit configuration diagram of a MOS type charge / discharge circuit according to the present invention, FIG. 1 (b) is a specific circuit configuration diagram of the sense amplifier in FIG. 1 (a), and FIG. FIG. 1 is a timing chart of the MOS type charge / discharge circuit according to the present invention shown in FIG. 1 (a), FIG. 3 is a circuit configuration diagram of a conventional MOS type charge / discharge circuit, and FIG. 4 is shown in FIG. 6 is a timing chart of the conventional MOS charge / discharge circuit shown. Q1, Q2, Q3 …… P-channel MOS transistor, Q4, Q4 ……
N-channel MOS transistor, R ... Resistor, LC ... Load circuit, S / A ... Sense amplifier, C ... Capacitor, SEN
...... Sense enable terminal.

Claims (1)

[Claims] 1. One of the first and second MOS transistors is connected to a first power supply terminal, the other terminal of the second MOS transistor is connected to a load circuit, and the first MO transistor is connected.
The other terminal and gate of the S transistor and the second MOS
The gate of the transistor is commonly connected to the second power supply terminal different from the one power supply terminal via the impedance element and the first switching element, and the capacitive element is connected to the gate of the second MOS transistor, Second MOS above
A second switching element is connected between the gate of the transistor and the first power supply terminal, and the first and second MO are connected.
The threshold voltage of the S-transistor is set to be approximately equal, and the channel width of the second MOS transistor is set to the first MOS.
The resistance value of the impedance element is set larger than the channel width of the transistor, and the resistance value of the impedance element is set larger than the impedance of the first MOS transistor.
MOS type charge / discharge circuit.