JPH0750742B2 - LSI design method - Google Patents

Description

The present invention relates to an LSI design method using CAD, and more specifically to an LSI design method that considers the layout of functional blocks to improve the wiring rate.

[Conventional technology]

In LSI design, the method of arranging functional blocks is
Several have been proposed. However, all of them are aimed at minimizing the total wiring length as described in, for example, P36 to 43 (published by IPSJ, Information Processing Society of Japan) of "CAD of logic device".

This has the advantage that the wiring delay time can be minimized in the shortest route, but has the following drawbacks. That is, in the placement result obtained by the above method, the placement target blocks are placed close to each other by minimizing the wiring length.

[Problems to be solved by the invention]

Usually, a certain block makes several wiring requests to the other block. Therefore, in the above arrangement result, a very large number of wiring requirements are brought to the center portion and they are crossed with each other, but the peripheral portion results in an empty cell portion in which no block is arranged. Therefore, in a master slice type LSI, etc., in which the wiring capacity between cell columns (the number of wires that can pass) is determined in advance, the wiring capacity in the central part is insufficient even though the wiring capacity in the peripheral part is sufficiently large. In some cases, 100% wiring may not be achieved in the end.

In this case, methods for replacing / moving the placed blocks, peeling the wiring results, and moving are conventionally used to correct unwiring, and since all of these are manual work, the number of design man-hours is significant. It has the drawback of leading to an increase.

[Means for solving problems]

The method of the present invention comprises a first step of inputting initial block placement result information and board information, a second step of taking out a block to be improved operation or a set of consecutively placed blocks, and A third step of taking out a set of improved operation mating blocks that are farther from the substrate center point than the set of blocks taken out in the step 2 and include empty cells and have the same size and shape; The n sets (n ≧ 2) of sets obtained in the second and third steps are exchanged with each other, and it is determined whether or not there is an improvement by an arrangement evaluation function indicating an increase in the number of empty tracks in the central portion of the substrate. A fourth step, and a fifth step of exchanging the set of n sets (n ≧ 2) of blocks when there is an improvement in the fourth step,
All of the blocks that can be a set of the improved operation partner blocks have a sixth step of returning to the third step if it has not been judged whether or not the third to fifth steps have been completed, and a block of the improved operation target block. It is judged whether all the items that can be a set have gone through the second to fifth steps, and if not, the second
The seventh step of returning to the step of No. 7 and the eighth step of editing and outputting the result obtained up to the seventh step as arrangement result information.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 4 is a diagram showing an example of a cell array forming a base structure of a master slice type LSI.

On the lower ground, there are set several cell columns 43 in which blocks to be placed can be placed, and blocks 45 are placed on the cell columns as shown in the figure. block
The 45 are not necessarily unified in a certain size and may be different from each other. In that case, assuming that the block 45a is the basic unit, the other blocks are represented by the same size or an integral multiple size. Between adjacent cell rows 44
Is called a wiring area.

Wiring is usually 1 on a wiring grid with a minimum pitch that satisfies the design rule between adjacent wires as 1 pitch.
It is carried out using two layers, one layer and two layers. Lateral wiring (1
Layer) is performed using the wiring region 44. The vertical wiring (two layers) is provided across the cell row 43. In addition, the vertical wiring is connected to the block terminal 41 and the prohibited area 42 in the block.
The top cannot pass.

FIG. 1 is a flow chart showing an embodiment of the present invention, which comprises a plurality of processing boxes and a judgment box. This process can be implemented by creating a program according to this flowchart and operating it on a computer, or by implementing the process as hardware and operating it. The case of creating a program will be described below.

FIG. 2 illustrates the processing steps of FIG. FIG. 2 (a) shows a general case of layout improvement.

The processing procedure will be described with reference to FIGS. 1 and 2. First, input the initial placement result information and board information (step 1
1). Next, the block 23 to be improved is taken out (step 12), and then the set of the block 21 and the empty cell 22 arranged farther from the substrate center point than the block 23 is taken out (step 13). In this case, the size of block 23
The shape and the size / shape of the block 21 and the empty cell 22 are exactly the same. Next, an attempt is made to exchange between the two sets of blocks, and the improvement by the placement evaluation function is judged (step
14) If there are improvements (YES branch of step 15), replace them (step 18). Of course, the block 21 may be a set of a plurality of blocks as long as they have the same size and shape.

FIG. 2B shows a case where the set of one block is only empty cells. First, the block 24 is taken out. Since this block has a size of 1, only the empty cells 25 farther from the substrate center point than the block 24 are taken out. After that, the possibility of replacement is checked by the same method as described above, and if yes, both are replaced.

The improvement operation by the two methods described above is repeated between the improvement operation target block set and all the block sets that can be the improvement operation partner side (step 16), and
This iterative process is repeated for all the refinement operation target block sets (step 17), thereby ending the process. An increase in the number of empty tracks in the central portion of the printed wiring board, which will be described later, can be used as the layout evaluation function for determining whether or not replacement is possible. FIG. 3 (a) shows wiring obtained by the layout result obtained by the conventional method.
The wiring result regarding the blocks a to h is performed using the wiring area between the cell columns. However, block a
~ Blocks h are arranged so as to be adjacent to each other without a gap, and a large number of in-block terminals 32 are used. Therefore, a vertical wiring request (2 Empty trucks 33)
On the wiring grid scale, there are only four positions of the first, fifth, seventh and twelfth columns. Therefore, if there are four or more vertical wiring requests, it is necessary to search for an empty track on the left side of the blocks a and e or the right side of the blocks d and h to perform wiring. Further, in order to perform this detour wiring, a lateral wiring request (one layer), which was not necessary in the past, is newly generated, resulting in an unwired portion that does not fit within the capacitance of the lateral wiring area.

FIG. 5 shows the above example. The vertical line segment 52 is originally an LSI
Although it should have passed through the central part of the above, there is no empty track for the vertical request in the central part 53 where the blocks are concentrated as a result of the arrangement. Therefore, a search is performed in the left-right direction from that position, and an empty track 56 is found at a position slightly apart. However, this causes new horizontal line segments 51 and 54, which causes the capacity of the wiring region to be exceeded, resulting in an unwired portion.

FIG. 3 (b) is an improvement of FIG. 3 (a) according to the present invention. In FIG. 3 (b), a block including an empty cell is an exchange target, and therefore, each block 31 has a space between the blocks 31. Empty cells 34 are moved / inserted, and as a result, there are a total of 6 empty tracks 33 on the boolock a to block h that satisfy the vertical wiring requirements (two layers) that penetrate the three cell rows.
(1,4,7,8,9,12 columns on the wiring grid scale) Clearly we can expect to obtain better wiring results than the conventional method.

Further, as a secondary effect, an effect that the number of wiring channels required for the lateral wiring request (one layer) is reduced can be expected.

Although the present embodiment has been described with respect to a good example in the master slice type LSI, it is possible to improve the layout of the LSI other than the master slice type LSI, the printed board, etc. by the same method.

〔The invention's effect〕

As described above, according to the present invention, among the set of n sets (n ≧ 2) of blocks for which layout improvement is to be performed, a block including an empty cell farther from the substrate center point and a block in the central portion. By performing the replacement with the above and performing the layout improvement according to the layout evaluation function, it is possible to secure an empty track to be used for wiring and prevent unwired wiring.

[Brief description of drawings]

FIG. 1 is a flow chart showing an embodiment of the present invention, and FIG.
FIG. 3 is an explanatory diagram showing the processing steps of the figure, FIG. 3 is a layout diagram showing a comparison of specific examples of layout improvement, FIG. 4 is a layout diagram showing an example of a base of an LSI, and FIG. 5 is an example of detour wiring according to a conventional example. It is a wiring diagram shown. 11 ~ 19 ... Flowchart steps, 21,23,24,31,45 ...
Block, 22, 25, 34 ... Empty cell, 31, 41 ... Block terminal, 3
3 ... Empty track, 42 ... Block prohibited area, 43 ... Cell row, 44 ... Wiring area.

Claims (1)

[Claims] 1. A first step of inputting initial block placement result information and board information, and a block to be improved,
Alternatively, the second step of taking out a set of blocks arranged continuously and the distance from the substrate center point is farther than the set of blocks taken out in the second step, and includes an empty cell, and is the same. A third step of taking out a set of improved operation partner blocks having a size and shape, and the second and third steps
A fourth step of exchanging a set of n sets (n ≧ 2) of blocks obtained in the above step with each other to determine whether or not there is an improvement by an arrangement evaluation function indicating an increase in the number of empty tracks in the central portion of the substrate; If there is an improvement in the fourth step, the n sets (n ≧
The fifth step of exchanging the set of blocks of 2) and the third step is all that can be the set of the improved operation partner side blocks.
To the fifth step, and if not, the sixth step to return to the third step, and all the blocks that can be the set of blocks to be improved are the second to fifth steps.
If it has not been determined whether or not the process has been performed, a seventh process that returns to the second process, and an eighth process that edits and outputs the results obtained up to the seventh process as placement result information. A method for designing an LSI, including: