JPH0750704B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH0750704B2 JPH0750704B2 JP62066030A JP6603087A JPH0750704B2 JP H0750704 B2 JPH0750704 B2 JP H0750704B2 JP 62066030 A JP62066030 A JP 62066030A JP 6603087 A JP6603087 A JP 6603087A JP H0750704 B2 JPH0750704 B2 JP H0750704B2
- Authority
- JP
- Japan
- Prior art keywords
- resist film
- film
- electron beam
- beam exposure
- opening
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体装置の電極・配線の形成方法の改良である。DETAILED DESCRIPTION [Outline] It is an improvement of a method of forming electrodes and wirings of a semiconductor device.
基板上にレジスト膜を形成し、レジスト膜上に液体酸化
膜よりなる電子線露光レジスト（本発明の出願人が開発
しすでに特許出願している（特願昭59−109503号）液体
酸化膜よりなる電子線露光レジストPMSS等）の膜を形成
し、電子線露光レジスト膜を電子線露光し、露光された
電子線露光レジスト膜を現像して開口を形成し、開口を
介して酸素プラズマ照射をなしてレジスト膜に開口を形
成し、導電体膜を形成し、レジスト膜を溶解して導電体
膜を残留して電極・配線を形成する工程を有する半導体
装置の製造方法である。A resist film is formed on a substrate, and an electron beam exposure resist composed of a liquid oxide film on the resist film (developed by the applicant of the present invention and already applied for a patent (Japanese Patent Application No. 59-109503)) Electron beam exposure resist PMSS etc.) is formed, the electron beam exposure resist film is subjected to electron beam exposure, the exposed electron beam exposure resist film is developed to form an opening, and oxygen plasma irradiation is performed through the opening. This is a method of manufacturing a semiconductor device including the steps of forming an opening in a resist film, forming a conductor film, dissolving the resist film, and leaving the conductor film to form an electrode / wiring.
〔産業上の利用分野〕 本発明は、半導体装置の製造方法の改良に関する。特
に、その電極・配線の形成方法の改良に関する。[Field of Industrial Application] The present invention relates to an improvement in a method for manufacturing a semiconductor device. In particular, it relates to improvement of the method of forming the electrodes and wiring.
半導体装置の製造方法において、素子の形成された基板
上に、電極・配線を形成する工程は重要な工程である。In the method of manufacturing a semiconductor device, the step of forming electrodes / wirings on a substrate on which elements are formed is an important step.
正確で微細な寸法をもって、短絡等をともなうことな
く、かゝる電極・配線を形成する手法の一つとして、逆
テーパ型レジスト膜を使用してなすリフトオフ法が知ら
れている。A lift-off method using an inverse taper type resist film is known as one of the methods for forming such electrodes / wirings with accurate and fine dimensions without causing a short circuit or the like.
これは、第６図、第７図に示すように、基板１上にレジ
スト膜７を形成し、これに等方性エッチングをアプライ
して、図示するようなテーパ型開口71を形成し、アルミ
ニウム等金属膜８を形成した後、レジスト膜７を溶解す
るものであるが、第７図に示すように、突起81が残留し
て短絡の原因になる等の欠点が避け難い。As shown in FIGS. 6 and 7, a resist film 7 is formed on the substrate 1 and isotropic etching is applied to the resist film 7 to form a tapered opening 71 as shown in FIG. Although the resist film 7 is dissolved after the equal metal film 8 is formed, as shown in FIG. 7, it is unavoidable that the projection 81 remains and causes a short circuit.
この欠点を解消する手法として、第８図、第９図に示す
ように、基板１上に下層レジスト膜９と二酸化シリコン
膜10と上層レジスト膜11とを重ねて形成し、上層レジス
ト膜11をマスクとして二酸化シリコン膜10をパターニン
グし、二酸化シリコン膜10をマスクとして下層レジスト
膜９をパターニングして、下層レジスト膜９の開口の幅
を二酸化シリコン膜10の開口の幅より大きくして、上記
の逆テーパ型レジスト膜を使用してなすリフトオフ法と
同様の効果を発揮する手法が提案されているが、二酸化
シリコン膜10の形成に長時間を要し、また、これを厚い
液体酸化膜とするときは、クラックが入りやすい等の欠
点があり、なお、実用上問題があり、よりすぐれた電極
・配線の形成方法の開発が望まれていた。As a method for eliminating this drawback, as shown in FIGS. 8 and 9, a lower resist film 9, a silicon dioxide film 10 and an upper resist film 11 are formed on a substrate 1 so that the upper resist film 11 is formed. The silicon dioxide film 10 is patterned as a mask, the lower resist film 9 is patterned using the silicon dioxide film 10 as a mask, and the width of the opening of the lower resist film 9 is made larger than the width of the opening of the silicon dioxide film 10. Although a method has been proposed that exhibits the same effect as the lift-off method using an inverse taper type resist film, it takes a long time to form the silicon dioxide film 10, and this is used as a thick liquid oxide film. In this case, there are drawbacks such as easy cracking, and there are still problems in practical use, and the development of a better electrode / wiring forming method has been desired.
本発明の目的は、この要請に応えることにあり、正確・
微細であり、しかも、短絡等のおそれのない電極・配線
の形成工程を有する半導体装置の製造方法を提供するこ
とにある。The object of the present invention is to meet this demand,
It is an object of the present invention to provide a method for manufacturing a semiconductor device which has a step of forming electrodes / wirings that are fine and do not cause a short circuit or the like.
上記の目的を達成するために本発明が採った手段は、 基板（１）上にレジスト膜（２）を形成し、 レジスト膜（２）上に液体酸化膜よりなる電子線露光レ
ジスト膜（３）を形成し、 この液体酸化膜よりなる電子線露光レジスト膜（３）を
電子線露光し、露光された電子線露光レジスト膜（３）
を現像して開口（４）を形成し、 開口（４）を介して酸素プラズマ照射をなして液体酸化
膜よりなる電子線露光レジスト膜（３）がひさし状に突
出して入口がせばめられている開口（５）をレジスト膜
（２）に形成し、 導電体膜（６）を形成し、 レジスト膜（２）を溶解して導電体膜（６）を残留して
電極・配線を形成することにある。The means adopted by the present invention to achieve the above object is to form a resist film (2) on a substrate (1) and to form an electron beam exposure resist film (3) made of a liquid oxide film on the resist film (2). ) Is formed, and the electron beam exposure resist film (3) made of this liquid oxide film is subjected to electron beam exposure to expose the electron beam exposure resist film (3).
Is developed to form an opening (4), and oxygen plasma irradiation is performed through the opening (4) so that an electron beam exposure resist film (3) made of a liquid oxide film protrudes like a canopy and the inlet is fitted. Forming an opening (5) in the resist film (2), forming a conductor film (6), dissolving the resist film (2) and leaving the conductor film (6) to form electrodes and wiring It is in.
本発明に係る電極・配線の形成工程は、本発明の出願人
が開発しすでに特許出願している（特願昭59−109503
号）液体酸化膜よりなる電子線露光レジストPMSS等の膜
が、厚さを薄くできるので正確にパターニングしうると
いう性質と、これが酸素プラズマ照射に耐えるという性
質と、酸素プラズマ照射を上記の液体酸化膜よりなる電
子線露光レジスト膜を介してノボラック系レジスト等に
アプライすると、適度に、等方性と異方性とが混合した
エッチング性能が実現するという性質とを組み合わせ
て、正確・微細であり、しかも、短絡等のおそれのない
電極・配線の形成方法を実現したものである。The electrode / wiring formation process according to the present invention was developed by the applicant of the present invention and has already applied for a patent (Japanese Patent Application No. 59-109503).
No.) The property of the electron beam exposure resist PMSS, which is a liquid oxide film, that can be patterned accurately because it can be made thin, and the property that it can withstand oxygen plasma irradiation. When applied to a novolac-based resist, etc. through an electron beam exposure resist film made of a film, a combination of the property of achieving an etching performance that is a mixture of isotropicity and anisotropy is achieved, and it is precise and minute. In addition, the present invention realizes a method of forming electrodes and wirings that does not cause a short circuit or the like.
以下、図面を参照しつゝ、本発明の一実施例に係る半導
体装置の製造方法についてさらに説明する。Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be further described with reference to the drawings.
第２図参照 半絶縁性ガリウムヒ素基板等１上に、ノボラック系レジ
スト等をスピンコートして、1.5μｍ厚のレジスト膜２
を形成する。See FIG. 2. A semi-insulating gallium arsenide substrate 1 is spin-coated with a novolac-based resist or the like to form a 1.5 μm thick resist film 2
To form.
つゞいて、PMSS（出願人が開発しすでに特許出願してい
る（特願昭59−109503号）１種の電子線露光型レジス
ト）等を薄く2,000Å厚にスピンコートして液体酸化膜
よりなる電子線露光レジスト膜３を形成する。Therefore, PMSS (a type of electron beam exposure type resist developed by the applicant and already applied for a patent (Japanese Patent Application No. 59-109503)) is spin-coated thinly to a thickness of 2,000Å to form a liquid oxide film. The electron beam exposure resist film 3 is formed.
第３図参照 電子線描画をなして幅１μｍの開口４を形成する。See FIG. 3. Electron beam drawing is performed to form an opening 4 having a width of 1 μm.
第４図参照 開口４を介して酸素プラズマを照射する。この工程によ
り、レジスト膜２が乾式現像された幅が1.2μｍ程度の
開口５が形成される。See FIG. 4. Oxygen plasma is irradiated through the opening 4. By this process, the resist film 2 is dry-developed to form the opening 5 having a width of about 1.2 μm.
第５図参照 アルミニウム等を真空蒸着またはスパッタして8,000Å
厚のアルミニウム膜６を形成する。See Fig. 5 Vacuum deposition or sputtering of aluminum, etc., 8,000Å
A thick aluminum film 6 is formed.
第１図参照 レジスト膜２を溶解して、残留したアルミニウム膜６を
もって電極・配線とする。See FIG. 1. The resist film 2 is dissolved, and the remaining aluminum film 6 is used as an electrode / wiring.
このようにして製造された電極・配線６は、短絡等の発
生のおそれがなく、しかも、微細・正確な形状を実現す
ることができる。The electrodes / wirings 6 manufactured in this manner are free from the risk of a short circuit or the like, and can realize a fine and accurate shape.
以上説明せるとおり、本発明に係る半導体装置の製造方
法によれば、液体酸化膜よりなる電子線露光レジストPM
SS等は極めて薄くコートすることができるので、正確・
微細であり、液体酸化膜よりなる電子線露光レジストPM
SS等は酸素プラズマ照射に耐える性質があり、一方、酸
素プラズマ照射はノボラック系レジスト等を容易にエッ
チするので、液体酸化膜よりなる電子線露光レジストPM
SS等の下部を大きくアンダーエッチすることになり、短
絡発生のおそれのない電極・配線を形成することができ
る。しかも、レジスト膜は、これに酸素プラズマを照射
するという乾式の単一工程をもって、露光・現像が同時
にしかも乾式になされるので、工程が短縮される利益も
ある。As described above, according to the method for manufacturing a semiconductor device of the present invention, the electron beam exposure resist PM made of a liquid oxide film is used.
Since SS etc. can be coated extremely thin,
PM that is a fine electron beam exposure resist consisting of a liquid oxide film
Since SS and the like have the property of resisting oxygen plasma irradiation, on the other hand, oxygen plasma irradiation easily etches novolac-based resists, etc.
Since the lower part of SS etc. is largely under-etched, it is possible to form electrodes / wirings that do not cause a short circuit. In addition, the resist film is exposed to oxygen plasma in a single dry process, and the exposure and development are simultaneously performed in a dry process. Therefore, there is an advantage that the process is shortened.
第１図は、本発明の一実施例に係る半導体装置の製造方
法を実施して製造した電極・配線の断面図である。 第２〜５図は、本発明の一実施例に係る半導体装置の製
造方法の工程図である。 第６〜９図は、従来技術に係る電極・配線の製造工程図
である。 １……基板、 ２、７、９、11……レジスト膜、 ３……電子線露光レジスト膜、 ４、５……開口、 ６、８……導電性膜、 10……二酸化シリコン膜、 81……突起。FIG. 1 is a cross-sectional view of electrodes / wirings manufactured by carrying out a method of manufacturing a semiconductor device according to an embodiment of the present invention. 2 to 5 are process diagrams of a method for manufacturing a semiconductor device according to an embodiment of the present invention. 6 to 9 are manufacturing process diagrams of electrodes and wirings according to the prior art. 1 ... Substrate, 2, 7, 9, 11 ... Resist film, 3 ... Electron beam exposure resist film, 4, 5 ... Opening, 6, 8 ... Conductive film, 10 ... Silicon dioxide film, 81 ...... Protrusion.
Claims (1)
し、 該レジスト膜（２）上に液体酸化膜よりなる電子線露光
レジスト膜（３）を形成し、 該液体酸化膜よりなる電子線露光レジスト膜（３）を電
子線露光し、該露光された電子線露光レジスト膜（３）
を現像して開口（４）を形成し、 該開口（４）を介して酸素プラズマ照射をなして、前記
液体酸化膜よりなる電子線露光レジスト膜（３）がひさ
し状に突出して入口がせばめられている開口（５）を前
記レジスト膜（２）に形成し、 導電体膜（６）を形成し、 前記レジスト膜（２）を溶解して前記導電体膜（６）を
残留する工程を有することを特徴とする半導体装置の製
造方法。1. A resist film (2) is formed on a substrate (1), and an electron beam exposure resist film (3) made of a liquid oxide film is formed on the resist film (2). Electron beam exposure resist film (3) is exposed to an electron beam, and the exposed electron beam exposure resist film (3)
Is developed to form an opening (4), and oxygen plasma irradiation is performed through the opening (4) so that the electron beam exposure resist film (3) made of the liquid oxide film protrudes like a canopy and the inlet is fitted. A step of forming an opening (5) formed in the resist film (2), forming a conductor film (6), dissolving the resist film (2), and leaving the conductor film (6). A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066030A JPH0750704B2 (en) | 1987-03-20 | 1987-03-20 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62066030A JPH0750704B2 (en) | 1987-03-20 | 1987-03-20 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63232448A JPS63232448A (en) | 1988-09-28 |
| JPH0750704B2 true JPH0750704B2 (en) | 1995-05-31 |
Family
ID=13304098
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62066030A Expired - Lifetime JPH0750704B2 (en) | 1987-03-20 | 1987-03-20 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0750704B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5626450A (en) * | 1979-08-13 | 1981-03-14 | Hitachi Ltd | Manufacture of semiconductor device |
-
1987
- 1987-03-20 JP JP62066030A patent/JPH0750704B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63232448A (en) | 1988-09-28 |
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