JPH07506461A - Integrated circuit with quantum well p-channel field effect transistor and complementary transistor - Google Patents

Integrated circuit with quantum well p-channel field effect transistor and complementary transistor

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Publication number
JPH07506461A
JPH07506461A JP5512972A JP51297293A JPH07506461A JP H07506461 A JPH07506461 A JP H07506461A JP 5512972 A JP5512972 A JP 5512972A JP 51297293 A JP51297293 A JP 51297293A JP H07506461 A JPH07506461 A JP H07506461A
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layer
band
forbidden band
narrow
holes
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ニュイェン, リン, テー.
カスターニェ,ジョン
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ピコジガ エス.アー.
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Priority claimed from FR9200668A external-priority patent/FR2686455A1/en
Priority claimed from FR9208985A external-priority patent/FR2694132B1/en
Application filed by ピコジガ エス.アー. filed Critical ピコジガ エス.アー.
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/802Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with heterojunction gate, e.g. transistors with semiconductor layer acting as gate insulating layer, MIS-like transistors

Abstract

(57)【要約】本公報は電子出願前の出願データであるため要約のデータは記録されません。 (57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 量子井戸nチャンネル電界効果トランジスタと、相補形トランジスタを有する集 積回路 本発明は単独で、あるいは相補形トランジスタの集積回路内のnチャンネル電界 効果トランジスタに組み合わせて使用される量子井戸nチャンネル電界効果トラ ンジスタ型の部品に関するものである。[Detailed description of the invention] A collection with quantum well n-channel field effect transistors and complementary transistors. product circuit The present invention can be applied to n-channel electric fields alone or in integrated circuits of complementary transistors. Quantum well n-channel field effect transistor used in combination with effect transistor This relates to resistor-type parts.

この点、CMOSシリコンは、メモ1月ビット当たり0. 3μWという低い値 まで下げることが可能で、したがって、複雑なデジタル回路の大規模集積を可能 にする、低い電力消費のおかげで非常に有望な技術になっている。In this respect, CMOS silicon has a memory capacity of 0.1 bit per month. Low value of 3μW and thus enable large-scale integration of complex digital circuits. Its low power consumption makes it a very promising technology.

しかしながらこの技術では、CMOSシリコンの伝播時間が長いために、超高速 回路を得ることはできない:したがって、この技術で得られるメモリアクセス時 間はIons程度である。However, with this technology, due to the long propagation time of CMOS silicon, ultra-high speed The circuit cannot be obtained: therefore, when memory access obtained with this technique The distance is about Ions.

もっと高速を望むならば、例えばIns程度のアクセス時間を可能にするシリコ ン上のECLバイポーラ−トランジスタに基づくような、別の技術で回路を実現 する必要がある。If you want higher speed, for example, silicon that enables access times on the order of Ins. Implementing the circuit with another technology, such as based on ECL bipolar transistors on There is a need to.

しかしこの回路はビット当たり数百マイクロワット程度のはるかに大きな電力を 消費する。But this circuit requires much more power, on the order of a few hundred microwatts per bit. Consume.

もう一つ可能な方法は、シリコンの代わりにIII−V合金を使用することであ り、特に速度と消費電力のパラメータが0.8nsで500μW程度であるGa As上に製造するM E S F E T s (MEtal−3emicon ductor Field−EffectTransistors :電界効果 金属半導体トランジスタ)に基づき回路を製作することである。しかしこの中間 的値は、速度と消費電力の妥協にしが過ぎないので、この技術には工業的に重要 な用途分野が見い出されない。Another possibility is to use III-V alloys instead of silicon. In particular, Ga M E S F E Ts manufactured on As (MEtal-3emicon ductor Field-Effect Transistors: Electric field effect (metal-semiconductor transistors). But this middle This technology has no industrial importance, as the target value is only a compromise between speed and power consumption. No suitable field of use has been found.

今日まで実現された一番高速の回路はAlGaAs/GaAsヘテロ接合を備え たHEMT s (High Electron Mobility Tran sistors :高電子移動度トランジスタ)を基礎に実現されたが、この部 品は伝播時間が論理ゲート当たり25がら30ps程度のTEGFETs (丁 to−DiIIlensional Electron Gas Field− EffectTransistors : 2次元電子ガス電界効果トランジス タ)という略称でも知られている。しかし電力消費が、論理ゲート当たり4mW 程度と大きいので、大規模集積は非常に困難である。The fastest circuits realized to date include AlGaAs/GaAs heterojunctions. HEMTs (High Electron Mobility Tran It was realized based on high electron mobility transistors (sisters: high electron mobility transistors), but this part The product is TEGFETs (TEGFETs) with a propagation time of about 25 to 30 ps per logic gate. to-DiII lenional Electron Gas Field- Effect Transistors: Two-dimensional electron gas field effect transistors It is also known by the abbreviation ``ta''. However, the power consumption is 4mW per logic gate. Due to its large size, large-scale integration is very difficult.

さらにもっと最近ではAlGaAs/Ga1nAsヘテロ接合集積回路の製作が 提案されたが、CMO3の場合と同様、n及びpチャンネルの相補形トランジス タが使用されるので、特に興味深い技術である。例えば、D、E、Grider らのDevelopH1ent of 5tatic Random Acce ss Memories Using Complemen狽≠窒■ Heterostructure In5ulated Gate Field  Effect Transistor Technolo■凵A GaAs Ic 5ynposiu+++ Digest 1990. p、 143を参 照することができる。この技術では200ps程度の比較的短い伝播時間で、ゲ ート当たり64μW程度の非常に低い消費電力の集積回路を実現することができ る。このようにしてアクセス時間が3.51sときわめて高性能で、消費電力が 183mWと非常に低い4にビットの静的メモリSRAMが実現された(参照、 D、E、GriderらのDelta−DopedComplelllenta ry Heterostructure FET5 with High Y− Value Pseudomo窒垂■奄■ In+Ga+−rAs Channels for tlltra Low I ’ower Digital ICApplication刀AIED)I Digest 1991. p、235 参照)。More recently, AlGaAs/Ga1nAs heterojunction integrated circuits have been fabricated. proposed, but similar to the case of CMO3, n- and p-channel complementary transistors This is a particularly interesting technique because it uses data. For example, D, E, Grider DeveloppH1ent of 5tatic Random Acce ss Memories Using Complemen 狽≠Nitrogen■ Heterostructure In5ulated Gate Field Effect Transistor Technolo A GaAs Ic 5ynposiu+++ Digest 1990. See p. 143. can be seen. With this technology, the propagation time is relatively short, about 200 ps, and the It is possible to realize integrated circuits with extremely low power consumption of approximately 64 μW per chip. Ru. In this way, access time is 3.51s, which is extremely high performance, and power consumption is reduced. A 4-bit static memory SRAM with a very low 183 mW was realized (see, Delta-Doped Complellenta of D., E. Grider et al. ry Heterostructure FET5 with High Y- Value Pseudomo Nittar ■奄■ In+Ga+-rAs Channels for tlltra Low I 'ower Digital ICA Application Katana AIED) I Digest 1991. (See p. 235).

本発明はこれまで提案されたAlGaAs/Ga1nAsヘテロ接合の周知の部 品のいくつかの不完全さと制約(後でもっと詳しく述べる)を解消することを目 的とする。The present invention is based on the well-known parts of AlGaAs/Ga1nAs heterojunctions proposed so far. The aim is to overcome some of the imperfections and limitations of the product (to be discussed in more detail later). target

より正確に言えば、本発明の目的の1つは、例えばnチャンネルトランジスタの 相互コンダクタンスの値がnチャンネルトランジスタと同じ程度で、nチャンネ ルトランジスタが+1チヤンネルトランジスタと同等の性能を有する相補回路を 実現することができる、相互コンダクタンスが非常に高いnチャンネルトランジ スタを実現するのに適した厚みとエピタキシアル層の選択を提案することである 。More precisely, one of the objects of the invention is to The transconductance value is about the same as that of an n-channel transistor. A complementary circuit that has the same performance as a +1 channel transistor. n-channel transistor with very high transconductance that can be realized The aim is to suggest the appropriate thickness and epitaxial layer selection to realize the star. .

これが今まで実現できなかったのは、nチャンネルトランジスタは、最善の場合 でも、その141互コンダクタンスがnチャンネルトランジスタの4分の1以下 であったからである。このような差のもとになる物理現象については後にもつと 詳しく述べる。This has not been possible until now because n-channel transistors However, its 141 mutual conductance is less than a quarter of that of an n-channel transistor. This is because it was. The physical phenomena that cause these differences will be discussed later. I will explain in detail.

本発明の第1の特徴によれば、ヘテロ接合の従来の構造を採用した部品が提案さ れる。According to a first feature of the invention, a component adopting the conventional structure of a heterojunction is proposed. It will be done.

もっと正確に言えば、この周知の構造は禁制帯が広いIII−V半導体材料(G aAs基盤上のAlxGa+−xAs、またはInP基盤上のAIr In+− rAsであることが望ましい)を含む層と禁制帯が狭いIII−V半導体材料( Ga、In+−yAsであることが望ましい)を含む層の間に形成されたヘテロ 接合から成り、このヘテロ接合が、禁制帯の狭い材料を含む層のレベルで、ヘテ ロ構造の価電子帯構造にHH型の側帯を作る量子井戸を形成する。More precisely, this well-known structure is based on wide forbidden III-V semiconductor materials (G AlxGa+-xAs on aAs substrate or AIr In+- on InP substrate rAs) and a narrow bandgap III-V semiconductor material (preferably rAs). A heterogeneous layer formed between layers containing (preferably Ga, In+-yAs) The heterojunction consists of a heterojunction at the level of the layer containing the narrow forbidden material. A quantum well is formed to form an HH type side band in the valence band structure of the B structure.

本発明の0;I述の第1の特徴として、ゲートに負の電圧が印加されたとき、量 子井戸内に側帯HH1とHH2,また場合によって高い次数の側帯HHs、、、 、が出現するように本質的に選択され、これら各種の側帯は一番高い有効質量m ”h//に対応する側帯が側帯HH,を占める正孔の密度よりもはるかに低い密 度の正孔によって占められるようなエネルギーによって分離され、量子井戸内に 有効質量m−//が低い正孔の蓄積状態が作り出され、それに従って部品の相互 コンダクタンスが増加するように禁制帯の狭い材料を含む層の厚みが実質上選択 されている。The first feature of the present invention described in 0;I is that when a negative voltage is applied to the gate, the amount of In the child well there are side bands HH1 and HH2, and in some cases higher order side bands HHs... , are essentially selected such that these various side bands have the highest effective mass m ``The side band corresponding to h// has a much lower density than the density of holes occupying the side band HH. within the quantum well, separated by the energy as occupied by the hole of the degree A state of accumulation of holes with a low effective mass m-// is created, and the parts are moved relative to each other accordingly. The thickness of the layer containing the material with a narrow forbidden band is substantially selected so that the conductance increases has been done.

本発明の第2の特徴によれば、従来のへテロ接合に対して修正された構造を示す 部品が提案される。According to a second feature of the invention, it presents a modified structure with respect to conventional heterojunctions. Parts are suggested.

本発明のこの第2の特徴として、部品は順番に、基盤上にエピタキシアル成長し た、禁制帯が広いIII−V半導体材料(GaAs基盤上のA I zG a  +−zA Sであることが望ましい)を含む第1の層と:禁制帯が狭いl11− V半導体材料(Ga、In+−yAsSGaASwSb+−w、またはG a  y I n +−yA swS b +−wであることが望ましい)を含む層と 、禁制帯が広いIII−V半導体材料(A I xG a +−xA Sである ことが望ましい)を含む第2の層を有し、これらの層の間の結晶格子の不一致の ために禁制帯の狭い材料を含む層は層の面内で単軸方向の圧縮ひずみを受け、こ の層のレベルの、構造の価電子帯回内でHH型の側帯を有する量子井戸を形成す る。さらに禁制帯が狭い材料を含む層の厚みと禁制帯が広い材料の組成は、負の 電圧がゲートに印加されたとき、量子井戸内に側帯HH1とHH2、また場合に よ1て高い次数の側帯HH,102,が出現するように本質的に選択され、これ ら各種の側帯は一番高い有効質量m″kl/に対応する側帯が側帯HH+を占め る正孔の密度よりもはるかに低い密度の正孔によって占められるようなエネルギ ーによって分離され、量子井戸内に有効質Jl1m”w/が低い正孔の蓄積状態 が作り出され、それに従って部品の相互コンダクタンスが増加するように選択さ れている。In this second feature of the invention, the components are sequentially grown epitaxially on the substrate. In addition, III-V semiconductor materials with a wide forbidden band (AIzGa on GaAs substrate) +−zA S) and: l11− with a narrow forbidden band. V semiconductor material (Ga, In+-yAsSGaASwSb+-w, or Ga y I n +−yA swS b+−w) , III-V semiconductor material with a wide forbidden band (A I x G a + - x A S (preferably), and the crystal lattice mismatch between these layers Therefore, a layer containing a material with a narrow forbidden band is subjected to uniaxial compressive strain in the plane of the layer, and this Forming a quantum well with HH-type sidebands in the valence band loop of the structure at the layer level of Ru. Furthermore, the thickness of the layer containing the material with a narrow forbidden band and the composition of the material with a wide forbidden band have negative effects. When a voltage is applied to the gate, there are sidebands HH1 and HH2 in the quantum well, and in some cases This is essentially chosen such that a higher order sideband HH,102, appears; Among the various side bands, the side band corresponding to the highest effective mass m″kl/occupies the side band HH+. energy that is occupied by holes with a much lower density than that of holes. - Separated by is created and the transconductance of the component increases accordingly. It is.

本発明のいずれの特徴においても、禁制帯の狭い材料がGa、In+−vAsで あるとき、この材料を含む層の厚みは、側帯HHを内の正孔密度が側帯HH,内 の密度よりはるかに低(なるように、インジウムのモル分率(1y)+++が0 .15と0.35の間であるとき、約4nmと約6nmの間に選択され、また側 帯HHs内のiE孔密度が側帯HH+とHH2内の密度よりはるかに低くなるよ うに、インジウムのモル分率(1y)Inが0.15と0.30の間であるとき 、約6nmと約9nmの間に選択される。In any of the features of the present invention, the material with a narrow forbidden band is Ga or In+-vAs. When the thickness of the layer containing this material is such that the hole density within the sideband HH is much lower than the density of (so that the mole fraction of indium (1y)+++ is 0 .. 15 and 0.35, selected between about 4 nm and about 6 nm, and the side The iE hole density in the band HHs is much lower than that in the side bands HH+ and HH2. uni, when the mole fraction of indium (1y) In is between 0.15 and 0.30 , between about 6 nm and about 9 nm.

本発明はさらに、nチャンネルトランジスタについて正孔の平均有効質量m″h //を下げ、それに従って相互コンダクタンスとその電流密度を増すように、I ;記の教示内容に従って製作された少なくとも1つのpチャンネル電界効果トラ ンジスタを含むことを特徴とする、pチャンネル及びnチャンネル電界効果トラ ンジスタ型の相補形部品の集積回路も対象とする。The invention further provides that for an n-channel transistor the average effective mass of holes m″h // to lower I and increase the transconductance and its current density accordingly. at least one p-channel field effect transistor fabricated in accordance with the teachings of; p-channel and n-channel field effect transistors, characterized in that they include transistors. It also covers integrated circuits with complementary components of the transistor type.

◇ 次に、付属の図面を参照して本発明の詳細な説明する。全ての図において、同一 の番号は同一の要素を指すものとする。◇ The invention will now be described in detail with reference to the accompanying drawings. Same in all figures The numbers refer to the same elements.

図1は、本発明がpチャンネル部品の構造に適用される、それぞれnチャンネル とpチャンネルの、2つのトランジスタの一般的構造を示している。FIG. 1 shows that the present invention is applied to the structure of p-channel components, respectively n-channel The general structure of two transistors, p-channel and p-channel, is shown.

図2a、2b、2cは図1の構造についての伝導帯と価電子帯の状態を示し、そ れぞれ静止状態、正のゲート電圧印加(nチャンネルトランジスタの場合)と負 のゲート電圧印加(nチャンネルトランジスタの場合)に対応する。2a, 2b, 2c show the conduction band and valence band states for the structure of FIG. quiescent state, positive gate voltage applied (for n-channel transistor) and negative gate voltage, respectively. (in the case of an n-channel transistor).

図3は、波動ベクトルの関数であるエネルギーで、圧力がかかつていない材料の 場合の、GaAsとGa InAsの価電子帯図を示している。Figure 3 shows the energy as a function of the wave vector for a material with no pressure. The valence band diagrams of GaAs and GaInAs are shown in the case of FIG.

図4は圧力がかかったヘテロ接合の構造とかけられた圧力の性質を概略的に示し ている。Figure 4 schematically shows the structure of a stressed heterojunction and the nature of the applied pressure. ing.

図5は図4の圧力がかかった材料の、図3と同様な図である。FIG. 5 is a view similar to FIG. 3 of the stressed material of FIG. 4;

116a、6bはアルミをわずかに含有する圧力がかかった構造の、それぞれ静 止状態及びゲートに負の電圧を印加した、価電子帯の状態を示している。116a and 6b are static structures with a pressured structure containing a small amount of aluminum, respectively. It shows the valence band state in the stopped state and with a negative voltage applied to the gate.

図7aと7bは、構造のアルミ含有率が高い点を除き、図6a、6bと同様な図 である。Figures 7a and 7b are similar diagrams to Figures 6a and 6b, except that the structure has a higher aluminum content. It is.

図8a、8bは、GalnAs層のレベルで、この層を異なる2つの厚みで作っ た場合について、形成される量子井戸の形状を示している。Figures 8a and 8b show the level of the GalnAs layer, which is made with two different thicknesses. The figure shows the shape of the quantum well formed in this case.

図9aと9bは、ゲートに異なる2つの負の電圧をかけた場合について、バイア スが掛けられたときの量子井戸の三角形変形を特に計算に入れた、図8bに示さ れた量子井戸内に存在する異なる側帯の位置をより明確に示している。Figures 9a and 9b show the vias for two different negative voltages on the gate. This is shown in Figure 8b, which specifically takes into account the triangular deformation of the quantum well when multiplied by This shows more clearly the location of the different sidebands that exist within the quantum well.

図10a、10b、10cは、先行技術の構造の場合について、それぞれ静止状 態とゲートに2つの異なる負の電圧がかけられた場合について、価電子帯の状態 、並びに量子井戸とこの井戸内に現れる側帯の状態を示している。Figures 10a, 10b and 10c respectively show the static state for the case of the prior art structure. The state of the valence band when two different negative voltages are applied to the state and the gate. , as well as the quantum well and the sideband states appearing within this well.

図11a、llb、llcは本発明の第1の特徴による構造について、図10a 110b、LoCと同様の図である。11a, llb, llc are for the structure according to the first feature of the invention, FIG. 10a 110b, a diagram similar to LoC.

図12は本発明の第2の特徴による構造について、図1と同様の図である。FIG. 12 is a diagram similar to FIG. 1 regarding the structure according to the second feature of the invention.

図13a、13b、14.15.16は様々な形状において、Ga InAsの 層に形成された1itf−井戸の状態を示している(より正確に言えば、図13 a、13b。Figures 13a, 13b, 14, 15, 16 show that GaInAs in various shapes It shows the state of the 1itf-well formed in the layer (more precisely, Fig. 13 a, 13b.

15は本発明の第1の特徴によるものであり、図14と16は、比較上、本発明 の第2の特徴によるものである)。15 is according to the first feature of the present invention, and FIGS. 14 and 16 are according to the first feature of the present invention for comparison. ).

◇ 図1に概略が示されている本発明の最初の構造は、連続的に、−GaAs基盤1 と、 −同じ<GaAs、またはGaAs/AlGaAsの積み重ねで構成されている が、500nmの厚みを有する(この厚みの値は、後述の全ての値開様、特記事 項なき限り、参考のためだけに挙げられた典型的な値である)化学的特性(純度 )と結晶特性が完全に制御されている、緩衝層2と、−シリコンに対する立体ま たは平面ドーピング(「δドーピング」)3と、−厚さ約3nm0)GaAsの 層4と、−厚さ15nm、ガリウム含有率yc−が約0.75から0,85程度 (これ以降、全ての含有率はモル分率で示される)のG a r I n +− yA sの層5と、−厚さが25nmの、アルミニウム含有率XAIが約075 程度のA l xG a +−xAsの層6と、 −厚さ3nmの保護層7: とを有する。◇ The first structure of the invention, schematically shown in FIG. and, - Consists of the same < GaAs or a stack of GaAs/AlGaAs has a thickness of 500 nm. Unless otherwise noted, chemical properties (purity) are typical values listed for reference only. ) and a buffer layer 2 whose crystalline properties are completely controlled; or planar doping (“δ-doping”) 3 and - about 3 nm thick) of GaAs. Layer 4 - 15 nm thick, gallium content yc - about 0.75 to 0.85 (Hereafter, all contents are expressed as mole fractions) G a r I n +- A layer 5 of yA s with a thickness of 25 nm and an aluminum content XAI of approximately 075 a layer 6 of A l x G a + - x As of degree; - protective layer 7 with a thickness of 3 nm: and has.

ついでに言えば、GalnAs層5上のAlr InI−rAs層6などの、上 記の例以外のIII−V属合金も使用可能で、異なる構成成分の含有率は特に、 InP基盤上で、その異なる合金の格子定数と適合させるように選ばれる。Incidentally, the upper layer of the AlrInI-rAs layer 6 on the GalnAs layer 5, etc. Group III-V alloys other than the examples given above can also be used, and the content of different constituents may be particularly On the InP substrate, it is chosen to match the lattice constants of the different alloys.

他方、この最初の構造を形成する全ての層は、平面ドーピングを除いて、非ドー ピング層である。On the other hand, all the layers forming this initial structure are undoped, except for planar doping. This is the ping layer.

この構造の上に、層3まで侵入するように、それ自体全〈従来どおりに、表面に ソース、ドレン、ゲート電極S、D、Gを形成する8と9で示したそれぞれn゛ とp゛のドーピング区域を打ち込むことによってnチャンネル、及びpチャンネ ル電界効果トランジスタを形成することができる。On top of this structure, it penetrates up to layer 3, so that it is completely The source, drain, and gate electrodes S, D, and G are formed by n 8 and 9, respectively. n-channel and p-channel by implanting doping areas of and p A field effect transistor can be formed.

このようにしてn及びpチャンネル相補形トランジスタ論理回路を実現できるが 、先に述べたごとく、本発明は別個に製造されると考えられた、即ちディスクリ ート部品の形で、pチャンネル電界効果トランジスタの製作にも適用できる。In this way n- and p-channel complementary transistor logic circuits can be realized. , as mentioned above, the present invention was conceived to be manufactured separately, i.e., discreetly. It can also be applied in the fabrication of p-channel field effect transistors in the form of flat components.

nチャンネルトランジスタの場合、閾電圧Vτ、を越える高い正の電圧をゲート に印加すると、Gayln+−yAsAs層に電子が蓄積され、そのときn型の チャンネルが形成される。逆に、nチャンネルトランジスタの場合、閾電圧VT Iより低い大きな負の電圧をゲートに印加すると、Ga、In+−yAsAs層 に正孔が蓄積され、そのときp型のチャンネルが形成される。In the case of an n-channel transistor, a high positive voltage exceeding the threshold voltage Vτ is applied to the gate. When the voltage is applied to A channel is formed. Conversely, in the case of an n-channel transistor, the threshold voltage VT When a large negative voltage lower than I is applied to the gate, the Ga, In+-yAsAs layer Holes are accumulated in the channel, and a p-type channel is formed at this time.

図2a、2b、2cは伝導帯Ecと価電子帯Evの形状を示し、それぞれ静止状 態、正のケート電圧印加(nチャンネルトランジスタの場合)と負のゲート電圧 印加(nチャンネルトランジスタの場合)に対応する。VGは印加されたゲート 電圧(場合によってO1正または負)、E、はフェルミレベルを表す。10はn チャンネルトランジスタの場合の電子が蓄積される場所を表し、11はnチャン ネルトランジスタの場合に正孔が蓄積される場所を表す。Figures 2a, 2b, and 2c show the shapes of the conduction band Ec and the valence band Ev, respectively in the stationary state. state, positive gate voltage applied (for n-channel transistors) and negative gate voltage (for n-channel transistors). VG is the applied gate The voltage (O1 positive or negative as the case may be), E, represents the Fermi level. 10 is n 11 represents the place where electrons are accumulated in the case of a channel transistor, and 11 is an n-channel transistor. represents the location where holes are accumulated in the case of a channel transistor.

これから述べる、これらの正孔と電子の伝導のそれぞれの状態は非常に異なり、 現在までに実現された構造において、同一の回路内に集積されたnチャンネルト ランジスタとnチャンネルトランジスタの特性の間にきわめて大きなずれが生じ ている。The states of conduction of holes and electrons, which we will discuss below, are very different. In the structures realized to date, n-channel transistors are integrated in the same circuit. An extremely large discrepancy occurs between the characteristics of the transistor and the n-channel transistor. ing.

実際、GaAsまたはGa InAs内で電子は低い有効質量m0.を有し、正 孔は大きな有効質ff1m″hを有することが判っている(先に述べたように、 有効質量は統計的平均に対応する)5言い換えれば、電子の移動度は高く、正孔 は非常に低い。In fact, electrons in GaAs or GaInAs have a low effective mass m0. and positive The hole is found to have a large effective volume ff1m''h (as mentioned earlier, The effective mass corresponds to the statistical average) 5 In other words, the mobility of electrons is high and the mobility of holes is is very low.

高速相補形論理回路製作の妨げになるこの難点を解消するためにG、 C。In order to solve this difficulty that hinders the production of high-speed complementary logic circuits, G and C.

0sbournらはElectron and Ho1e Effective  l1asses forTwo−Dimensional Transpor t in 5trained−Layer 5uperlattices、5u per撃≠狽狽奄モ■■ and Microstructures、 Vt+1.1. No、3. p 、223(1985)において、下に概略を説明する、複雑な物理現象を利用し て正孔の有効質量を減じる効果のある圧力がかかったGa InAs層を作り出 すためにGa1nAsをGaAsまたはAlGaAsと組み合わせることを提案 した。0sbourn and others Electron and Hole Effective  l1asses forTwo-Dimensional Transport t in 5 trained-Layer 5 upper lattices, 5u Persecution ≠ Crackling ■■ and Microstructures, Vt+1.1. No, 3. p. , 223 (1985), which utilizes complex physical phenomena outlined below. to create a GaInAs layer under pressure that has the effect of reducing the effective mass of holes. proposed combining Ga1nAs with GaAs or AlGaAs to did.

月−、)功(かかっていない材料では、GaAsまたはGa1nAsの価電子帯 が曲線がはっきり分離された2つの帯に分割される。図3はこの場合の面(ε、 に)(波動関数で表されるエネルギー)内の価電子帯の図を示している。HHで 示されたこれらの帯の1つは「重い正孔の帯」と呼ばれ、LHと付けられた他方 の帯は「軽い正孔の帯」と呼ばれる。正孔の有効質量は、次の関係式によって、 帯の曲線と反比例することが判っている m”h=h”/ (a’e/θ/C2) (1)この式で、hはブランク定数、 εはエネルギー、には波動ベクトルであることが判っている。Moon-, ) Gong (For unrestrained materials, the valence band of GaAs or Ga1nAs The curve is divided into two clearly separated bands. Figure 3 shows the plane (ε, ) shows a diagram of the valence band in (energy represented by a wave function). At HH One of these bands shown is called the "heavy hole band" and the other labeled LH. The band is called the "light hole band." The effective mass of a hole is determined by the following relational expression: It is known that it is inversely proportional to the band curve. m”h=h”/(a’e/θ/C2) (1) In this formula, h is a blank constant, It is known that ε is energy and is a wave vector.

次に、図4に示されたGaAsまたはAlGaAsの2つの層に挟まれたGa1 nAsの薄い層のような、圧力がかかった材料を考えると、界面に平行な面でG a1nAsの層は、矢印12で示された圧縮を受け、他方垂直面では、矢印13 て表された引張を受ける。Next, Ga1 sandwiched between two layers of GaAs or AlGaAs shown in FIG. Considering a material under pressure, such as a thin layer of nAs, G in a plane parallel to the interface The layer of a1nAs undergoes compression as indicated by arrow 12, while in the vertical plane it undergoes compression as indicated by arrow 13 is subjected to a tension expressed as

図5に示した、対応する価電子帯の図において、この変形の結果として価電子帯 が分離し、界面に平行な面内で帯が著しく変形する。In the corresponding valence band diagram shown in Figure 5, this deformation results in a valence band are separated, and the band is significantly deformed in a plane parallel to the interface.

図5において、図の右半分は界面に平行な波動ベクトルに7/に対応し、左半分 は界面に垂直な波動ベクトルに−に対応する。界面に平行に(即ち、図5の右半 分で)、帯は強く変形されて、「重い」正孔HHは軽くなり、逆に「軽い」正孔 LHは重くなり、一方界面に垂直方向では(即ち図5の左半分で)、「重い」正 孔HHは重いままで、「軽い」正孔LHは軽いままである。言い換えれば、正孔 の爪しヅ軽いという性質の逆転は価電子帯の一方で起きるが、他方では起きない 。In Figure 5, the right half of the diagram corresponds to the wave vector parallel to the interface, and the left half corresponds to 7/. corresponds to the wave vector perpendicular to the interface. parallel to the interface (i.e., the right half of Figure 5) ), the band is strongly deformed, the "heavy" holes HH become lighter, and conversely the "light" holes LH becomes heavier, while in the direction perpendicular to the interface (i.e. in the left half of Figure 5), the “heavy” positive Holes HH remain heavy and "light" holes LH remain light. In other words, holes The reversal of the lightness property occurs on one side of the valence band, but not on the other. .

この価電子帯の変形は正孔の充満の統計的分布も変える:例えば、平均的に、G aAs/Ga I nAs/GaAsまたはAlGaAs/Ga InAs/A lGaAsのシステムの中で、正孔の有効質量は圧力がかからないGaAs/A lGaAsシステムの中の質量よりも小さくなる。したがって、このような圧力 がかかったシステムの中でnチャンネルトランジスタは移動度が増加し、その結 果、相互コンダクタンスg1が向上する。例えば、Griderの上記の論文に は、ゲート長さが1μmのトランジスタで相互コンダクタンスg、。が70mS /mm(ミリメートル化たりミリシーメンス)に達したと記載されている。しか しこの値は300m5/mm程度であるnチャンネルトランジスタの同様な相互 コンダクタンスg−の値よりはるかに低く、4.3:1であり、nチャンネルト ランジスタをnチャンネルトランジスタと同じように働かせようとする場合には 克服しなければならない値である。This valence band deformation also changes the statistical distribution of hole filling: for example, on average, G aAs/Ga InAs/GaAs or AlGaAs/Ga InAs/A In the lGaAs system, the effective mass of the hole is the unpressured GaAs/A It is smaller than the mass in the lGaAs system. Therefore, such pressure The mobility of n-channel transistors increases in a system where As a result, mutual conductance g1 is improved. For example, in the above paper by Grider, is the mutual conductance g of a transistor with a gate length of 1 μm. is 70mS /mm (millimeters or millisiemens). deer The thickness value is about 300m5/mm for a similar mutual relationship of n-channel transistors. It is much lower than the value of conductance g-, which is 4.3:1, and the n-channel If you want to make a transistor work like an n-channel transistor, This is a value that must be overcome.

非常に最近になって、B、Laikhtmanらが5trained Quan tuIlfellValence−Band 5tructure and 0 ptiIIal Parameters for AlGaAs−1nGaA刀 |AIGaAs p−Channel Field−Effect Transistors、  J、Appl、Phys、、 Vol、70. No、3.@p、1531 (1991)において、AlGaAsの2つの層の間に含まれたGa InAs の層の一領域に形成される量子井戸を使用して正孔の有効質量をいっそう小さく することを提案したが、この論文のこれらの層の組成と量子井戸の幅(即ち、G alnAs層の厚さ)はHH2の高さがちょうど量子井戸の縫の高さになるよう に定義しなければならない。この論文の図9は電子程度の非常に小さな、すなわ ち0.07mqに近い(moは電子の質量)有効質量は、アルミニウム含有率X AIが0. 2以上であることを条件に達成可能であることを示している。同論 文の図8から著者らは厚さが2から5nmの間のGalnAs層の使用を推奨し ていることが演鐸されるが、ここで厚さの値が一番人きいとき、アルミニウム濃 度X^1は一番低くなる。Very recently, B. Laikhtman et al. tuIlfellValence-Band 5structure and 0 ptiIIIal Parameters for AlGaAs-1nGaA sword |AIGaAs p-Channel Field-Effect Transistors, J, Appl, Phys, Vol. 70. No, 3. @p, 1531 (1991), GaInAs contained between two layers of AlGaAs The effective mass of holes is further reduced using quantum wells formed in one region of the layer. However, the composition of these layers and the quantum well width (i.e., G The thickness of the alnAs layer) is set so that the height of HH2 is exactly the height of the thread of the quantum well. must be defined. Figure 9 in this paper shows a very small particle on the order of an electron, i.e. The effective mass, which is close to 0.07 mq (mo is the mass of electrons), is the aluminum content AI is 0. It shows that it is achievable provided that it is 2 or more. same opinion From Figure 8 of the text, the authors recommend using a GalnAs layer with a thickness between 2 and 5 nm. However, when the thickness value is the most important, aluminum concentration Degree X^1 is the lowest.

もっと正確に言うと、XAl=0.2はG a v 1 n 1−yA sの厚 さ約4から5nmに対応し、XAl=0.8はGa、In+−、Asの厚さ2. 5nm程度に対応する。To be more precise, XAl=0.2 is the thickness of G a v 1 n 1 - y A s XAl=0.8 corresponds to a thickness of about 4 to 5 nm, and XAl=0.8 corresponds to a thickness of 2.5 nm for Ga, In+-, As. It corresponds to about 5 nm.

しかしながらこの構造は、アルミニウム含有率が低い場合にも高い場合にも、あ らゆる大きな障害を抱えている。However, this structure is not suitable for both low and high aluminum content. They are facing all sorts of major obstacles.

なぜなら、アルミニウム含有率が低いとき、構造は価電子帯の不連続性が低下す る、即ち電位障壁ΔE、が低(なる。図6は平衡時(図6a)とゲートの負のバ イアス時(図6b)について、X^、=約0.2であるこのような構造の価電子 帯の概略を示している。この負のバイアス時の場合、ΔE、はO,IVより低く 、このように障壁が低いと、正孔はトンネル効果(図6bの矢印14)及び/ま たは熱イオン効果(図15)によって障壁を越えてしまう。トンネル効果と熱イ オン効果があまりに大きなゲート漏洩電流を生み出すので、トランジスタは正常 に働かなくなる。This is because when the aluminum content is low, the structure becomes less discontinuous in the valence band. In other words, the potential barrier ΔE is low. For the ias time (Fig. 6b), the valence electrons of such a structure, where X^, = approximately 0.2 The outline of the obi is shown. In this case of negative bias, ΔE, is lower than O,IV. , with such a low barrier, the holes will experience tunneling effects (arrow 14 in Figure 6b) and/or or the barrier is crossed by the thermionic effect (Fig. 15). Tunnel effect and heat The on-effect produces so large a gate leakage current that the transistor is stop working.

反対に、アルミニウム含有率が高い(XAI≧約0.7)構造は電位障壁ΔE、 が、図7aと7bに示したごとく、約0.4V以上とかなり高くなり、トンネル 効果による漏洩電流が無視できるほど充分な高さになる。しかし、この結果に至 るためには、Ga、In+−、As層の至適厚みは、Laikhtmanの前記 論文によれば、インジウム含有率(1y)+−≧約0.25で2.5nmという 低い値に減らさなければならない。On the contrary, a structure with a high aluminum content (XAI≧about 0.7) has a potential barrier ΔE, However, as shown in Figures 7a and 7b, it becomes quite high, about 0.4V or more, and the tunnel The height is high enough that the leakage current due to the effect can be ignored. However, this result In order to According to the paper, the indium content (1y)+-≧0.25 is 2.5 nm. Must be reduced to a low value.

厚さがこのように薄いといくつかの問題が出てくる、なかんずく:m;の小さな 空間内で、正孔(または電子)はそれを閉じ込めている2つの界面と深刻な相互 作用を生じ、その移動度が著しく減じる、また−他方、AlGaAs及びGa  InAs層の結晶成長の実際条件は非常に異なっているので、完全な品質の界面 を得ることが非常に困難になり、界面にある凸凹が生じ、移動度がいっそう減じ るが、量子井戸の幅が小さいときはさらに減じる。Such a thin thickness presents several problems, not least of which is the small thickness of m; In space, a hole (or electron) has severe interaction with the two interfaces that confine it. On the other hand, AlGaAs and Ga The actual conditions for crystal growth of InAs layers are very different, so that perfect quality interfaces cannot be obtained. It becomes very difficult to obtain the However, it decreases further when the width of the quantum well is small.

このように、先行技術の教示するところは、それを正孔の移動度の増加、したが ってnチャンネルトランジスタの相互コンダクタンスの増加を目的とする場合、 実際には袋小路に入ってしまうが、それはアルミニウム含有率が低いとあまりに 大きな漏洩電流が生じ、アルミニウム含有率が高いと層が薄く成りすぎて、有効 かつ、適切に製作できなくなるからである。Thus, the prior art teaches that it increases hole mobility, but When the purpose is to increase the mutual conductance of an n-channel transistor, In reality, we reach a dead end, but it is because the aluminum content is too low. Large leakage currents occur and high aluminum content makes the layer too thin to be effective. This is also because it will not be possible to manufacture the product properly.

本発明の目的はこれらの制約全体を克服し、かつ、例えば相互コンダクタンスが nチャンネルトランジスタと同じくらい高い、相互コンダクタンスが非常に大き いnチャンネルトランジスタの製作を可能にすることである。The aim of the invention is to overcome all of these limitations and to ensure that e.g. Very large transconductance, as high as an n-channel transistor The purpose of this invention is to make it possible to fabricate a thin n-channel transistor.

それは後述の2つの方法で実現可能であるが、その1つは量子井戸の従来の構造 を残すものであり、他方は性能をいっそう高めるためにその構造を変えるもので ある。This can be achieved in two ways as described below, one of which is the conventional structure of quantum wells. The other is the one that changes the structure to further improve the performance. be.

本発明の第1の実施例 本発明はA I xG a 1−XA 8層6と、G a 、I n +−yA  s層5とGaAs層4の間に形成された量子−井戸を有する、図1に示したよ うな基礎構造を使用する。First embodiment of the invention The present invention includes A I x G a 1-XA 8 layers 6, G a, I n As shown in FIG. 1, it has a quantum well formed between the S layer 5 and the GaAs layer 4. Use a basic structure.

これらの層に働く物理作用は −価電r・帯の位置と形状及びG a v I n +−yA sの層5の平面 とこれに平行な面内の正孔の有効質量に働く機械的圧力の効果、−薄膜5内に1 7t−r−側帯(レベル)の出現、−A I xG a +−xA 8層6によ って構成される電位障壁を通過するトンネル効果、である。The physical effects that act on these layers are -Position and shape of valence r/band and plane of layer 5 of G a v I n +-yA s and the effect of mechanical pressure acting on the effective mass of holes in a plane parallel to this, - 1 in the thin film 5. 7t-r- Appearance of lateral band (level), -A I x G a + - x A 8 layer 6 This is a tunnel effect that passes through a potential barrier made up of.

これら3つの効果の他に、量子井戸の幅に関する、即ち先に述べたごと(G a  v I n +−yA s層5の厚さに関する制限的考察が加わる。In addition to these three effects, there are also effects related to the width of the quantum well, i.e.  v   n    +-yA Restrictive consideration regarding the thickness of the s layer 5 is added.

実証されたごと((この点に関して、本出願人による、この現象を詳細に記載し 、説明しているフランス特許出願91−15140を参照されたい)、nチャン ネルトランジスタの場合電子が受けるトンネル効果のためにアルミニウム含有率 XAIが約07を越える組成だけを考慮してこの最後のパラメータ(量子井戸の 幅)を考察しよう。As demonstrated ((in this regard, a detailed description of this phenomenon by the applicant) , see French patent application No. 91-15140 describing In the case of channel transistors, the aluminum content increases due to the tunneling effect experienced by electrons. This last parameter (quantum well width).

まず、第1の近似として、Garln+−+Asによって作られた量子井戸が、 図88.8bに示したごとく、対称だとする。この井戸の内部に、量子側帯HH ,。First, as a first approximation, the quantum well made by Garln+-+As is Assume that it is symmetrical, as shown in Figure 88.8b. Inside this well, there is a quantum sideband HH ,.

EH2,EH3などが出現するが、それらは図8に見るごとく、井戸の幅が小さ いほどいつそうエネルギーが分離されている。側帯LH,、LHzのエネルギー レベルは、この場合がそうであるように、インジウム含有率(1y)+−が0. 2゜を越えると価電子帯のピークから非常に離れている(150mVより大きい )ので正孔LHの関与は無視できる。したがって、これらの側帯はトランジスタ 作動の通常条件においては正孔によって占められることはない。EH2, EH3, etc. appear, but as shown in Figure 8, the width of the well is small. The more energy is separated, the more energy is separated. Lateral band LH, LHz energy The level is such that, as in this case, the indium content (1y)+- is 0. If it exceeds 2°, it is very far from the valence band peak (greater than 150 mV). ), so the involvement of holes LH can be ignored. Therefore, these side bands are transistor Under normal conditions of operation, it is not occupied by holes.

正孔HH2、HHs、などの界面に平行な面内の有効質IILm”h//は正孔 HHIのそれよりも大きいことが判っている。したがって、側帯HHt、HHs などは正孔ができるだけ少ないことが有利である。La i kh tmanの 前述の論文は図8bに示したごとく、側帯HH2が井戸のちょうど縁に来るよう に充分狭い量子井戸を使用することを提案しており、その結果幅が2.5nm程 度の井戸になる。しかしこの条件は必要でもなければ1・分でもない。The effective mass IILm”h// in the plane parallel to the interface of holes HH2, HHs, etc. is the hole It is known that it is larger than that of HHI. Therefore, the lateral bands HHt, HHs For example, it is advantageous to have as few holes as possible. La i kh tman As shown in Figure 8b, the above-mentioned paper was designed so that the side band HH2 is located just at the edge of the well. proposed using sufficiently narrow quantum wells, resulting in widths of around 2.5 nm. It becomes a well of degrees. However, this condition is neither necessary nor 1 minute.

他方、先に述べたごとく、電位障壁ΔE、を通る正孔のトンネル効果のために、 アルミニウム含有率X^1が低いときはこの条件は十分ではなかった。これはn チャンネルトランジスタの場合電子が受けるトンネル効果の恐れのためにアルミ ニウム含有率X^1を約0. 7以上とすることを意味する。ところがこの条件 で、ΔE、は500mVを越え、レベルHH2が正孔で充満されないためには、 このレベルが井戸の縁、即ち井戸の底がら500mVである必要はない;ただH HtとHH,内の正孔密度の比が無視できるように側帯HHIがら充分離れてい ることが必要である。On the other hand, as mentioned earlier, due to the hole tunneling effect through the potential barrier ΔE, This condition was not sufficient when the aluminum content X^1 was low. This is n In the case of channel transistors, aluminum is used due to the fear of tunneling effect caused by electrons. The nium content X^1 is about 0. It means 7 or more. However, this condition In order for ΔE to exceed 500 mV and the level HH2 not to be filled with holes, It is not necessary that this level be at the edge of the well, i.e. at the bottom of the well; it is just H The side band HHI is sufficiently far away so that the ratio of hole densities in Ht and HH can be ignored. It is necessary to

この比について無視できる限度が数パーセントだとすると、側帯HHf内の正孔 密度が側帯HH,内の正孔密度の数パーセントになるようにHH+とHHtの間 のエネルギーレベルの差を決定することができる。If the negligible limit for this ratio is a few percent, then the holes in the sideband HHf between HH+ and HHt so that the density is a few percent of the hole density in the sideband HH, The difference in energy levels can be determined.

正孔の密度pは次の関係式に従って側帯のエネルギーレベルEHによって変化す ることが判っている。The hole density p changes depending on the energy level EH of the side band according to the following relational expression: It is known that

p=Nvexp [−(EH−EF)/kT]、 (2)と・ Nv=m”、〃kT/πh’ (3) ここで、EFはフェルミレベル、kはポルツマン定数、Tは絶対温度、hはブラ ンク定数、m″h//は正孔の有効質量である。p=Nveexp [-(EH-EF)/kT], (2) and Nv=m”, 〃kT/πh’ (3) Here, EF is the Fermi level, k is Portzmann's constant, T is the absolute temperature, and h is the Brass constant. The link constant, m″h//, is the effective mass of holes.

、11pから、−1,記の条件(HH2の正孔密度はHH,の正孔密度の数パー セントに過ぎない)はレベルHH2がHH+から約125mVの差があるとき満 たされ、そのときの晴f・井戸の幅は約5nmで、この値はLaikhtman が推奨している2、5nmの値をはるかに1を回る。, 11p, -1, condition (the hole density of HH2 is several percent of the hole density of HH, cents) is satisfied when the level HH2 differs from HH+ by about 125 mV. The width of the clear f-well at that time was approximately 5 nm, and this value was determined by Laikhtman. The value of 2.5 nm is much higher than 1, which is recommended by the authors.

もっと正確に3えば、正孔の蓄積状態で(即ち、Vc≦約−1■で、ゲートに強 L)fsのバイアスがかけられたとき)、量子井戸の形は長方形ではなく、図9 a。More precisely, in the hole accumulation state (i.e., Vc≦about-1■, the gate is strongly L) when a bias of fs is applied), the shape of the quantum well is not rectangular and is shown in Fig. a.

9bに示したような擬三角形になる。It becomes a pseudo-triangle as shown in 9b.

この条件で、副準位HH,とHH2を分離するエネルギーは長方形形状の場合よ りも少し高くなるが、この変動は125mVの差の値に対しては無視できる。Under this condition, the energy to separate the sub-levels HH and HH2 is higher than in the case of a rectangular shape. is also slightly higher, but this variation is negligible for a difference value of 125 mV.

しかしながら、擬三角形の形状は量子井戸が対称でないときはきわめて重要にな り、この−一、はL3 i l(h tmanは考察していないが、Gride rはfiij述の論文の中でち察しており、その帯同は参考として図2aから2 Cで説明した。However, the shape of the pseudotriangle becomes extremely important when the quantum well is not symmetric. ri, this -1 is L3 i l (htman has not considered it, but Glide r is found in the paper described by Fiij, and its accompanying information is shown in Figures 2a to 2 for reference. Explained in C.

図10a、10b、10cはそれぞれゲート電圧0と、2つの増加する負のゲー ト電圧について、この場合の価電子帯図をもっと詳しく記載している。Figures 10a, 10b and 10c are shown for gate voltage 0 and two increasing negative gate voltages, respectively. Regarding the gate voltage, the valence band diagram in this case is described in more detail.

Ga、I n+−vAsとGaAsの間の価電子帯の不連続性ΔE、は0.25 から040の間で変動するインジウム濃度(1y)+−に従って、80から13 ゜nlV程度になることが判る。さらに、平衡状態(図10a)で、井戸のかな り大きな幅(15pm)を計算に入れて3つの量子側帯HHI、 HHt、HH sが存在することが判る。平衡状態で、この井戸には正孔が充満していないが、 ゲート電圧が充分高くなると(図10b)、帯の曲線が多数の量子側帯HH+、 HHt、HHs、EH4、HH5の存在と共に擬三角形井戸を出現させる。フェ ルミレベル及びHH+のレベルに対してこれらの側帯のエネルギー位置を考慮し て、側帯HHl、また特に、側帯)(H3は正孔で満たされている。ところが、 M、Jaffeらが、Theoretical Formalism to U nderstand the Role of 5train in the  T≠奄撃盾窒奄獅■ of Bole Masses in p Type InxGa+−xAs  (on GaAs 5ubstrates)andInOsx、xGao +y −JS (on InP 5ubstrates) Mtxiulation− Doped Field−Ef■■モ■ Transistors、 Appl、 Phys、 Lett、、Vol、5 1. No、23. p、1943 (19B?)においてAま たLaikhtmanが前述の論文で説明しているごとく、上位の側帯HH2と HH、の正孔のイ1゛効質量は、側帯HH+のそれよりはるかに高く、質量比は 最大10倍になることがある。The valence band discontinuity ΔE between Ga, In+-vAs and GaAs is 0.25 80 to 13 according to the indium concentration (1y) +- varying from 0 to 040 It can be seen that the voltage is about ゜nlV. Furthermore, in the equilibrium state (Fig. 10a), the well The three quantum sidebands HHI, HHt, HH are calculated by taking into account the larger width (15pm). It turns out that s exists. At equilibrium, this well is not filled with holes, but When the gate voltage is high enough (Fig. 10b), the band curve becomes a large number of quantum sidebands HH+, Pseudo-triangular wells appear with the presence of HHt, HHs, EH4, and HH5. Fe Considering the energy positions of these side bands with respect to the Lumi level and the HH+ level, Therefore, the sideband HHL, and especially the sideband) (H3 is filled with holes. However, M. Jaffe et al., Theoretical Formalism to U derstand the Role of 5train in the T≠Attack shield nitsakushi■ of Bole Masses in p Type InxGa+-xAs (on GaAs 5ubstrates) andInOsx, xGao +y -JS (on InP 5ubstrates) Mtxiulation- Doped Field-Ef■■Mo■ Transistors, Appl, Phys, Lett, Vol, 5 1. No, 23. p, 1943 (19B?) A or As explained by Laikhtman in the above-mentioned paper, the upper lateral band HH2 and The effective mass of the hole in HH, is much higher than that in the side band HH+, and the mass ratio is It can increase up to 10 times.

レベルHH+、EH2、HH3111,の充填の統計を計算に入れると、Jaf feによれば、0.324mo程度の正孔の平均有効質量m”hiiが演鐸され 、この値はTL’I’の有効質量の48倍になる。Taking into account the filling statistics of levels HH+, EH2, HH3111, Jaf According to fe, the average effective mass of holes m''hii of about 0.324mo is calculated. , this value is 48 times the effective mass of TL'I'.

この結果は70m5/mmという、nチャンネルトランジスタの相互コンダクタ ンスで得られた実験結果と符合するが、この値は」ユ述の300m5/mmとい うnチャンネルトランジスタの場合の値の4.3分の1である。This results in an n-channel transistor transconductor of 70m5/mm. This value agrees with the experimental results obtained in the 300 m5/mm This is 1/4.3 of the value for an n-channel transistor.

先に証明したごと(、この障害は幅が約5nmの量子井戸の使用によって解消さ れる。As we proved earlier (this obstacle is overcome by the use of quantum wells with a width of about 5 nm). It will be done.

図11aからllcは、本発明による量子井戸の幅について、図10aから10 cと同じであり、対応する価電T−帯の状態を示している。Figures 11a to llc illustrate the width of quantum wells according to the invention in Figures 10a to 10. c, and shows the state of the corresponding valence T-band.

平衡状態(図11a)では、量P井戸の狭さとGaAsとGa1nAsの間のΔ E、値が100mV程度と低いことの重なった影響から、側帯HH1しか存在し ないことが判る。ゲートに一1V程度の充分なバイアスがかかると(図11b) 、帯の曲線に側帯HH,が出現する。量子井戸が狭いので、後者はHH,から約 100ミリボルト離れている(反対に、量子井戸が広いとき、例えばGride rの挙げている場合のように15pmのとき、側帯HH2はHHIかられずか5 0mVしか差がなく、有効質量の大きな正孔によって満たされる)。バイアス値 がもっと高いとき、例えばvG=約−1,4Vのとき(図11b)側帯HHsが 出現するかもしれないが、そのレベルは、HH,のレベルと同じく、フェルミレ ベルEpから充分離れているので、量子井戸が充分狭いときは正孔によって満た されない。In the equilibrium state (Fig. 11a), the amount P well narrowness and Δ between GaAs and Ga1nAs E, due to the combined effect of the low value of about 100 mV, only lateral band HH1 exists. It turns out there isn't. When a sufficient bias of about -1V is applied to the gate (Figure 11b) , a side band HH appears on the band curve. Since the quantum well is narrow, the latter is about HH, 100 millivolts apart (on the contrary, when the quantum well is wide, e.g. Glide At 15 pm, as in the case of (There is only a 0 mV difference and it is filled by a hole with a large effective mass). bias value When is higher, e.g. when vG = about -1.4V (Fig. 11b), the lateral band HHs It may appear, but its level is similar to the level of HH, Fermile. Since it is far enough away from Bell Ep, when the quantum well is narrow enough, it is filled with holes. Not done.

このように、量子井戸が非対称のときも、この幅を減らすことによって(一般的 には幅5nm)第1の側帯HH,Lか満たさず、他の側帯を希薄にしてお(こと ができる。約言すれば、量子井戸の幅が5nmのとき、nチャンネルトランジス タは有効質量が小さい正孔でしか作動しない。In this way, even when the quantum well is asymmetric, by reducing this width (general (width 5 nm) without filling the first side bands HH, L, and diluting the other side bands (width 5 nm). Can be done. Roughly speaking, when the width of the quantum well is 5 nm, the n-channel transistor The detector only works with holes, which have a small effective mass.

この有効質量の値はG a y I n +−yA s層5に圧力がかかるほど 、即ちインジウム濃度が高いほど小さくなる。ただし、この圧力はある限度を超 えてはならないことが判っている、それを越えるとGayln+−vAs /  G a A s層(層5と4)とGa+In+−+As/AlxGa+−xAs 層(層5と6)の界面に転位が発生する。The value of this effective mass increases as pressure is applied to G a y I n + - y A s layer 5. , that is, the higher the indium concentration, the smaller it becomes. However, this pressure exceeds a certain limit. I know that I should not exceed it, and if I exceed it, Gayln+-vAs / G a As layers (layers 5 and 4) and Ga+In+-+As/AlxGa+-xAs Dislocations occur at the interface between the layers (layers 5 and 6).

事実、この現象はG a v I n +−yA s層5の厚さに依存する(例 えば、J、W。In fact, this phenomenon depends on the thickness of the G a v I n + - y A s layer 5 (e.g. For example, J, W.

MatthewsとA、E、BlakesleeのJ、 Cryst、 Gro wth、 Vol、27゜p、 118 (1974)を参照)。この層が薄い ほど、インジウム含有率を上げることができ、側帯HH,を占める正孔の有効質 量が小さくなる。厚さが5nmのとき、インジウム含有率(1y)+−は約0. 35に達することが可能で、そのときレベルHH,の正孔の有効質ff1m″、 /7は約0.07moになり、これはほぼ電子の有効質量である。Matthews and A, E, Blakeslee's J, Crystal, Gro wth, Vol. 27°p. 118 (1974)). This layer is thin The more the indium content increases, the more effective the holes occupying the side band HH become. The amount becomes smaller. When the thickness is 5 nm, the indium content (1y)+- is approximately 0. 35, then the effective quantity of holes of level HH, ff1m'', /7 becomes about 0.07 mo, which is approximately the effective mass of an electron.

HH,とHH2のエネルギーレベルの差はインジウム濃度と共に増加し、したが って、この特性がHH,に対するH H2内の正孔密度の減少を助長することが 判る。The difference in energy level between HH, and HH2 increases with indium concentration, but Therefore, this characteristic may promote a decrease in the hole density in H H2 with respect to HH, I understand.

有効質Mm″、/7が0.07mo程度のとき、nチャンネルトランジスタはn チャンネルトランジスタと同様な相互インダクタンスを示す。このとき、G a  v I n + rA s層5の厚さが約5nmである、XAI≧約07で( 1y)+−≧約0.25のへテロ接合AlxGa+−xAs/Gal、In+− yAsで、このように対にされた相補形トランジスタ集積回路を製作できるが、 それはこの層の厚さが約15nmであるこれまで製作されたものより高速である 。When the effective quality Mm'', /7 is about 0.07mo, the n-channel transistor has n It exhibits mutual inductance similar to that of a channel transistor. At this time, G a v I n + rA s The thickness of the layer 5 is about 5 nm, and when XAI≧about 07 ( 1y) +-≧approximately 0.25 heterojunction AlxGa+-xAs/Gal, In+- Complementary transistor integrated circuits paired in this way can be fabricated using yAs, but It is faster than anything fabricated so far, where the thickness of this layer is about 15 nm. .

このように、層5の厚さが5nmのとき、nチャンネルトランジスタはほぼ正孔 HH,でしか作動しない。同様に、nチャンネルトランジスタは側帯E+の電子 でしか作動しない:E1から170mVに位置する側帯E2は非常に希薄である 。In this way, when the thickness of layer 5 is 5 nm, the n-channel transistor has almost no holes. It only works with HH. Similarly, an n-channel transistor has electrons in the sideband E+. only operates at: sideband E2, located 170 mV from E1, is very dilute. .

HHr内の正孔濃度はこの側帯の状態の密度によって制限され、同様にE1内の 電子密度も制限される。自由キャリア(nチャンネルトランジスタの場合は正孔 、nチャンネルトランジスタの場合は電子)の密度に比例するトランジスタの電 流密度は、したがって、側帯HHIだけが正孔によって満たされ、側帯E、が電 子に満たされているとき、制限される。故に、低い有効質ff1m″h//と正 孔(及び電子)の高い濃度の間にで妥協点をみいだすことになる。この観点から 、有効質量がはるかに高い(7から10倍)正孔による側帯HHsの充満を一切 排除して、nチャンネルトランジスタが側帯HH,のほぼ2から3倍高い有効質 量の正孔で満たされた側帯HHtを有することが許容される。この場合、Ga  InAsの量子井戸幅は、HH2とHH,の差が40mV程度のとき、HH3と HH+の間のエネルギー差が125mVを越えるように選択される。この条件は 約9nm未満の量子井戸幅については十分である:この量子井戸幅で、側帯E2 はElがら50mVであり、ゲートに強いバイアスがかけられたとき電子によっ て充満されることを可能にする。しかしながら、層の厚さが9nmに増加するの で、界面転位の出現を防止するためにこの層のインジウム含有率を下げなければ ならない、したがって、インジウム含有率(1y)+−を0.25から0.30 程度に下げる。The hole concentration in HHr is limited by the density of states in this sideband, and similarly in E1. Electron density is also limited. Free carriers (holes in the case of n-channel transistors) , electrons in the case of an n-channel transistor) The current density is therefore such that only the sideband HHI is filled with holes and the sideband E is filled with electric charges. When it is filled with children, it is limited. Therefore, the low effective quality ff1m″h// and the positive A compromise will be found between high concentrations of holes (and electrons). From this point of view , without any filling of sideband HHs by holes with much higher effective masses (7 to 10 times). By eliminating the n-channel transistor, the effective quality is almost two to three times higher than that of the sideband HH. It is permissible to have a sideband HHt filled with a large amount of holes. In this case, Ga The quantum well width of InAs is HH3 and HH3 when the difference between HH2 and HH is about 40 mV. The energy difference between HH+ is chosen to be greater than 125 mV. This condition is This is sufficient for quantum well widths less than about 9 nm: with this quantum well width, the sideband E2 is 50 mV from El, and when a strong bias is applied to the gate, the electron to allow it to be charged. However, as the layer thickness increases to 9 nm Therefore, in order to prevent the appearance of interfacial dislocations, the indium content of this layer must be lowered. Therefore, the indium content (1y)+- is 0.25 to 0.30 Reduce it to a certain degree.

他方、先に述べたごとく、説明した例に挙げたちの以外のIII−V合金も使用 可能であり、様々な構成成分の含有率は特に異なる合金の格子の定数を適合させ るように選択される。例えば、次の構造を考えることができる基盤1 : In P 層2から4 : X’AI=0.48であるA Ir I n+−r As と し格子定数をINFと適合させる。On the other hand, as mentioned earlier, III-V alloys other than those mentioned in the example described can also be used. It is possible, and the contents of various constituents can be specially tailored to suit the lattice constants of different alloys. selected as follows. For example, base 1 that allows you to consider the following structure: In P Layers 2 to 4: A Ir I n+-r As with X'AI = 0.48 and match the lattice constant with INF.

層5:yG、が0.12がらo、22程度の機械的圧力がががったGa+Ir+ +−yAs 層6 格子定数が適合するA Ir I n+−r As本発明の第2の実施例 図12において、本発明の第2の実施例に使用される基本構造の概略を示した。Layer 5: Ga+Ir+ with a mechanical pressure of about 0.12 to 22 +-yAs Layer 6 A Ir I n+-r As with matching lattice constant Second embodiment of the present invention FIG. 12 schematically shows the basic structure used in the second embodiment of the present invention.

この構造は第1の実施例のような(禁制帯の狭いGayln+−rAs層が禁制 帯の広いA I xG a +−zA S層と組み合わされ、全体がGaAs基 盤上にエピタキシアル成長された)へテロ接合を持つ、従来型の2元構造ではな (、禁制帯の広いA I xG a + −xA 3層6とA l zG a  +−zA 8層16との2つの層の間に挟まれた禁制帯の狭いGaylr++− yAsAs層ら成る3元構造であり、この3つの層がGaAsの基盤1,2上に エピタキシアル成長されている。このようにして得られた構造は図12に示され 、図1と同じ番号は同様な部品を示しているので、これ以上群しい説明はしない 。This structure is similar to the first embodiment (the Gayln+-rAs layer with a narrow forbidden band is forbidden). Combined with a wide band A It is not a conventional binary structure with a heterojunction (epitaxially grown on a board). (, wide forbidden band A I x G a + - x A 3 layer 6 and A l z G a +-zA 8th layer 16 and narrow forbidden band sandwiched between the two layers Gaylr++- It has a ternary structure consisting of yAsAs layers, and these three layers are placed on GaAs substrates 1 and 2. It is epitaxially grown. The structure thus obtained is shown in Figure 12. , the same numbers as in Figure 1 indicate similar parts, so no further detailed explanation will be given. .

次にこのように改造した理由と、本発明の第1の実施例に比較して有利な点を説 明する。Next, we will explain the reason for this modification and the advantages compared to the first embodiment of the present invention. I will clarify.

このため、−IV程度のゲートバイアスVcがかかった価電子帯園内に形成され た量を井戸を拡大表示している図13から16を参照する。For this reason, it is formed in the valence band with a gate bias Vc of about -IV. Reference is made to FIGS. 13-16, which zoom in on the wells.

図13aは実際、図11bの拡大図であり、本発明の第1の実施例において、5 nm程度の5を丁−井戸の場合、1i;1述のバイアス電圧では側帯HH2はイ ンジウム濃度(1y)+nが約0.35に達しない限り、側帯HH,からおよそ 100ミリボルトには存在しないことを示している。FIG. 13a is actually an enlarged view of FIG. 11b, and in a first embodiment of the invention, 5 In the case of a well of about 5 nm, 1i; at the bias voltage mentioned in 1, the sideband HH2 is i Unless the nium concentration (1y)+n reaches approximately 0.35, approximately This shows that it does not exist at 100 millivolts.

しかし、特に格子の定数の差か非常に大き(なって、冶金が困難になるので、( 1y)+n=約0635のGayln+−、As層の製作はかなり難しい。However, especially if the difference in lattice constants is very large, metallurgy becomes difficult ( 1y)+n=approximately 0635 Gayln+-, the production of the As layer is quite difficult.

そこで、インジウム含有率が低いGarln+−、As層を持つ構造も考えられ るだろう。しかし、インジウム含有率が低いG a y I n +−rA s 材料で、量子井戸幅が同じ場合、図13bに見るごとく、例えば(1y)+−= 0.20のとき、側帯HH2のレベルが側帯HH,のレベルに接近するのでGa AsとGayln+−yAsの間の価TLr・帯の非連続性はもはや65mVで なくなる・この条件では、HH,内、さらにはHHs内の正孔濃度を無視するこ とができなくなる。Therefore, a structure with a Garln+- and As layer with a low indium content may also be considered. It will be. However, G y I n +-rA s with low indium content If the material has the same quantum well width, as shown in Figure 13b, for example (1y)+-= At 0.20, the level of side band HH2 approaches the level of side band HH, so Ga The discontinuity of the valence TLr band between As and Gayln+-yAs is now 65 mV. ・Under this condition, the hole concentration in HH, and even in HHs can be ignored. and become unable to do so.

この制限を克服するために、本発明は第2の実施例において、GaAsの代わり にA1□Ga12Asなどの禁制帯が広い材料を使用して価電子帯の不連続性を 上昇させて側帯HHtとHH3を一番高いエネルギーに押し上げることを提案す る。To overcome this limitation, the present invention in a second embodiment replaces GaAs. By using a material with a wide forbidden band such as A1□Ga12As, the discontinuity in the valence band can be reduced. We propose to raise the side bands HHt and HH3 to the highest energy. Ru.

このようなA I xG a 1−XA s/Ga、 I n I−yA s/ A l zGa+−zA sシステムの価電子帯図は図14に示されている。容 易に判るように、インジウムの濃度が低いときでも、A I zG a +−z A Sのアルミニウム濃度ZAIが例えば2^+=0.30と充分高ければ、G aylr++−yAsとA I zG a +−zA Sの間の価電子帯の不連 続性は十分になって、側帯HH2とHHsの間の正孔の濃度は無視できるように なる。Such A I x G a 1-XA s/Ga, I n I-yA s/ The valence band diagram of the Al zGa+-zA s system is shown in FIG. capacity As can be easily seen, even when the concentration of indium is low, A If the aluminum concentration ZAI of A S is sufficiently high, for example 2^+=0.30, G Valence band discontinuity between aylr++-yAs and A IzG a +-zA S The continuity has become sufficient, and the hole concentration between the side bands HH2 and HHs can be ignored. Become.

このように第2の実施例ではインジウム含有率は全く臨界パラメータにはならず 、Garln+−rAs層に、冶金処理がはるかに容易なインジウム含有率が低 い材料を選択することができる。In this way, in the second example, the indium content is not a critical parameter at all. , the Garln+-rAs layer has a low indium content, which is much easier to metallurgically process. You can choose different materials.

G a r I n 1−yA s層のインジウム含有率の他に、量子井戸の幅 を決定する、層の厚さも本発明の第1の実施例よりもはるかに広い範囲から選択 することができる。In addition to the indium content of the G a r I n 1-yA s layer, the width of the quantum well The layer thickness, which determines the can do.

事実、バイアスが常にVG−−IVで、量子井戸幅が6から9nm程度の第1の 実h&例の価電r−帯同を示した図15において、側帯HH2はHH,がら約5 0mVにあり、側帯[(H3は、図13aの前述の場合と同じく、量子井戸の拡 大部分内にある。In fact, the bias is always VG--IV and the quantum well width is about 6 to 9 nm. In Figure 15, which shows the valence r-banding of the actual h & example, the side band HH2 is HH, about 5 0 mV and the sideband [(H3 is the expansion of the quantum well, as in the previous case in Fig. 13a). Mostly within.

しかしながら、この側帯HH3はHH2から40から80mVであるが(量子井 戸の深さによって、即ち025から0.30でなければならないインジウム含イ j率(1y))−によって変化する)、それでもこの側帯はその正孔濃度を無視 するためにはまだHH7に近すぎる。However, this sideband HH3 is 40 to 80 mV from HH2 (quantum well Depending on the depth of the door, the indium content must be between 0.025 and 0.30. j rate (1y)), yet this sideband ignores its hole concentration It's still too close to HH7 for that.

この制約を克服するために、図14の場合と同じく、GaAsの代わりにA I  zG a 1−zA Sなどの禁制帯が広い材料を使用して、図16に示した ごとく、帯の不連続性を上昇させ、Gayln+−、Asのインジウム含有率に かかわりなく、HH2から側帯HH,を少なくとも100mVに押し上げること ができる。In order to overcome this constraint, AI was used instead of GaAs as in the case of FIG. Using a material with a wide forbidden band, such as zG a 1-zA S, as shown in Figure 16 As shown in FIG. Regardless, pushing the sideband HH from HH2 to at least 100 mV Can be done.

ここでもA I 2G a +−zA Sのアルミニウム含有率ハ1は枢要では なく、例えば030、一般的にはZAI>0.15とすることができる。Here too, the aluminum content C1 of A I G a +-zA S is important For example, ZAI>0.15.

ここで注意するのは、」−述の合金組成は制限的ではな(、特に中央の薄い層に ついては、Ga、I旧−yAs以外の合金を有利に使用することができることで ある。It should be noted here that the alloy composition mentioned above is not limiting (especially in the central thin layer). Therefore, it is possible to advantageously use alloys other than Ga and I old-yAs. be.

例えば、Ga、Ir++−rAsよりも正孔の移動度が大きい、アンチモン系の 合金がある。この点、化合物GaSbは格子定数がInAsに類似しているので 、GaAswSbl−w(wは約0.85から0.90程度)とGavlnl− yAswsb+−v(yは約0.70から0.80程度、Wは約0.85から0 90程度)の合金も圧縮によって単軸方向の圧力を受けるだろう。For example, antimony-based materials have higher hole mobility than Ga, Ir++-rAs. There is an alloy. In this respect, the compound GaSb has a lattice constant similar to InAs, so , GaAswSbl-w (w is about 0.85 to 0.90) and Gavlnl- yAswsb+-v (y is about 0.70 to 0.80, W is about 0.85 to 0 90) alloys will also be subjected to uniaxial stress due to compression.

F(GjOa FIG−11a フロントページの続き (51) Int、 C1,’ 識別記号 庁内整理番号HOIL 29106  8427−4M29/66 8427−4M 9171−4M (81)指定国 EP(AT、BE、CH,DE。F (GjOa FIG-11a Continuation of front page (51) Int, C1,' Identification symbol Internal office reference number HOIL 29106 8427-4M29/66 8427-4M 9171-4M (81) Designated countries EP (AT, BE, CH, DE.

DK、ES、FR,GB、GR,IE、IT、LU、MC,NL、 PT、 S E)、JP、 USI HOIL 29/80 EDK, ES, FR, GB, GR, IE, IT, LU, MC, NL, PT, S E), JP, USI HOIL 29/80 E

Claims (10)

【特許請求の範囲】[Claims] 1.pチャンネル電界効果トランジスタ型の部品において、禁制帯が広いIII −V半導体材料を含む層(6)と、構造の残りの部分との結晶格子の不一致によ って禁制帯が狭い材料を含む層が層の面内で圧縮単軸方向圧力を受ける、禁制帯 が狭いIII−V半導体材料を含む層(5)の間に形成されたヘテロ接合を有し 、このヘテロ接合がヘテロ構造の価電子帯図内の、禁制帯の狭い材料を含む層の レベルで、HH型の副帯を作る量子井戸を形成する部品であって、 ゲートに負の電圧(VG)が印加されたとき、量子井戸内に副帯HH1とHH2 、また場合によって高い次数の副帯HH3、...が出現するように本質的に選 択され、これら名種の副帯は一番高い有効質量m■h//に対応する副帯が副帯 HH1を占める正孔よりもはるかに低い密度で正孔によって占められるようなエ ネルギーによって分離され、量子井戸内に有効質量m■h//が低い正孔の蓄積 状態が作り出され、それに従って部品の相互コンダクタンスが増加するように禁 制帯の狭い材料を含む層の厚みが、実質上選択されていることを特徴とする部品 。1. III, which has a wide forbidden band in p-channel field effect transistor type components - due to the crystal lattice mismatch between the layer (6) containing the V semiconductor material and the rest of the structure. The forbidden zone is a narrow forbidden zone in which a layer containing a material is subjected to compressive uniaxial pressure within the plane of the layer. has a heterojunction formed between layers (5) containing narrow III-V semiconductor material; , this heterojunction is a layer containing a material with a narrow forbidden band in the valence band diagram of the heterostructure. A component that forms a quantum well that creates an HH type subband at the level, When a negative voltage (VG) is applied to the gate, subbands HH1 and HH2 are created in the quantum well. , and possibly higher order subbands HH3, . .. .. is essentially selected so that The subband of these famous species is the subband corresponding to the highest effective mass m h//. The hole is occupied by holes at a much lower density than the holes occupying HH1. accumulation of holes with low effective mass m h// in the quantum well separated by energy A condition is created that inhibits the mutual conductance of the components to increase accordingly. Part characterized in that the thickness of the layer containing the material with a narrow band is substantially selected . 2.請求項1に記載の部品において、材料がGaAsの基盤(1)上にエピタキ シアル成長した、禁制帯が広い材料がAlxGa1−xAsであり、禁制帯が狭 い材料がGayIn1−yAsであることことを特徴とする部品。2. Component according to claim 1, in which the material is epitaxially deposited on a substrate (1) of GaAs. AlxGa1-xAs is a sial-grown material with a wide forbidden band, and the forbidden band is narrow. A component characterized in that the material is GayIn1-yAs. 3.請求項1に記載の部品において、材料がInPの基盤(1)上にエピタキシ アル成長した、禁制帯が広い材料がAlxIn1−xAsであり、禁制帯が狭い 材料がGayIn1−yAsであることことを特徴とする部品。3. Component according to claim 1, characterized in that the material is epitaxied on a substrate (1) of InP. Al-grown material with a wide forbidden band is AlxIn1-xAs, and the forbidden band is narrow. A component characterized in that the material is GayIn1-yAs. 4.pチャンネル電界効果トランジスタ型の部品において、−連続して、基盤( 1)上にエピタキシアル成長した:・禁制帯が広いIII−V半導体材料を含む 第1の層(16)と、・禁制帯が狭いIII−V半導体材料を含む層(5)と、 ・禁制帯が広いIII−V半導体材料を含む第2の層(6)とから成り、これら の層の間の結晶格子の不一致によって禁制帯が狭い材料を含む層が層の面内で圧 縮単軸方向圧力を受け、この層のレベルで、価電子帯図内にHH型の副帯を作る 量子井戸を形成し、 −禁制帯の狭い材料を含む層の厚みと禁制帯の広い材料の組成が、ゲートに負の 電圧(VG)が印加されたとき、量子井戸内に副帯HB1とHH2、また場合に よって高い次数の副帯HH3、...か出現するように本質的に選択され、これ ら各種の副帯は一番高い有効質量m■h//に対応する副帯が副帯HH1を占め る正孔の密度よりもはるかに低い密度の正孔によって占められるようなエネルギ ーによって分離され、量子井戸内に有効質量m■h//が低い正孔の蓄積状態が 作り出され、それに従って部品の相互コンダクタンスが増加するように選択され ていることを特徴とする部品。4. In components of the p-channel field effect transistor type, - successively the substrate ( 1) Epitaxially grown on: Contains a III-V semiconductor material with a wide forbidden band a first layer (16); a layer (5) containing a III-V semiconductor material with a narrow forbidden band; ・A second layer (6) containing a III-V semiconductor material with a wide forbidden band; A layer containing a material with a narrow forbidden band due to the crystal lattice mismatch between the layers is compressed in the plane of the layer. Under the pressure in the uniaxial direction, an HH-type subband is created in the valence band diagram at the level of this layer. form a quantum well, −The thickness of the layer containing the material with a narrow forbidden band and the composition of the material with a wide forbidden band have a negative effect on the gate. When a voltage (VG) is applied, there are subbands HB1 and HH2 in the quantum well, and in some cases Therefore, the higher order subbands HH3, . .. .. or essentially selected to appear, this Among the various sub-bands, the sub-band corresponding to the highest effective mass m h// occupies the sub-band HH1. energy that is occupied by holes with a much lower density than that of holes. The accumulation state of holes with low effective mass m h// is separated by selected such that the transconductance of the components increases accordingly. Parts characterized by: 5.請求項4に記載の部品において、材料がGaAsの基盤上にエピタキシアル 成長した、第2の層の禁制帯が広い材料がAlxGa1−xAsであり、禁制帯 が狭い材料がGayIn1−yAsであり、第1の層の禁制帯が広い材料がAl zGa1−zAsであることことを特徴とする部品。5. 5. A component according to claim 4, wherein the material is epitaxial on a substrate of GaAs. The grown second layer material with a wide forbidden band is AlxGa1-xAs, and the forbidden band is The material with a narrow forbidden band is GayIn1-yAs, and the material with a wide forbidden band in the first layer is Al. A component characterized by being zGa1-zAs. 6.請求項1または4のいずれか一つに記載の部品において、禁制帯の狭い材料 がGaAswSb1−wであることを特徴とする部品。6. A component according to any one of claims 1 or 4, characterized in that the material has a narrow forbidden band. A component characterized in that is GaAswSb1-w. 7.請求項1または4のいずれか一つに記載の部品において、禁制帯の狭い材料 かGayIn1−yAswSb1−wであることを特徴とする部品。7. A component according to any one of claims 1 or 4, characterized in that the material has a narrow forbidden band. or GayIn1-yAswSb1-w. 8.請求項2または5のいずれか一つに記載の部品において、GayIn1−y Asを含む層の厚みが、副帯HH2内の正孔密度が副帯HH1内の密度よりはる かに低くなるように、インジウムのモル分率(1−y)Inが0.15と0.3 5の間のとき、約4nmと約6nmの間にほぼ含めることができることを特徴と する部品。8. Component according to any one of claims 2 or 5, wherein GayIn1-y The thickness of the layer containing As is such that the hole density in the subband HH2 is greater than the density in the subband HH1. The mole fraction of indium (1-y)In is 0.15 and 0.3 so that it is very low. 5, the wavelength can be approximately included between about 4 nm and about 6 nm. parts. 9.請求項2または5のいずれか一つに記載の部品において、GayIn1−y Asを含む層の厚みが、副帯HH3内の正孔密度が副帯HH1とHH2内の密度 よりはるかに低くなるように、インジウムのモル分率(1−y)Inが0.15 と0.30の間のとき、約6nmと約9nmの間にほぼ含めることができること を特徴とする部品。9. Component according to any one of claims 2 or 5, wherein GayIn1-y The thickness of the layer containing As is such that the hole density in subband HH3 is the same as the density in subbands HH1 and HH2. The mole fraction of indium (1-y)In is much lower than 0.15 and 0.30, it can be included approximately between about 6 nm and about 9 nm. Parts featuring: 10.pチャンネルトランジスタについて正孔の平均有効質量m■h//を下げ 、それに従って相互コンダクタンスとその電流密度を増すように、上記いずれか の請求項に従って製作された少なくとも1つのpチャンネル電界効果トランジス タを含むことを特徴とする、pチャンネル及びnチャンネル電界効果トランジス タ型の相補形部品の集積回路。10. Lowering the average effective mass of holes m h // for p-channel transistors , any of the above so as to increase the transconductance and its current density accordingly at least one p-channel field effect transistor made according to the claims of p-channel and n-channel field effect transistors, characterized in that they include An integrated circuit with complementary components of the type ta.
JP5512972A 1992-01-22 1993-01-21 Integrated circuit with quantum well p-channel field effect transistor and complementary transistor Pending JPH07506461A (en)

Applications Claiming Priority (5)

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FR92/00668 1992-01-22
FR9200668A FR2686455A1 (en) 1992-01-22 1992-01-22 Heterojunction, p-channel, field-effect transistor, and integrated circuit with complementary transistors
FR92/08985 1992-07-21
FR9208985A FR2694132B1 (en) 1992-07-21 1992-07-21 P-channel field effect transistor with quantum well, and integrated circuit with complementary transistors.
PCT/FR1993/000061 WO1993015523A1 (en) 1992-01-22 1993-01-21 Quantum well p-channel field effect transistor, and integrated circuit having complementary transistors

Publications (1)

Publication Number Publication Date
JPH07506461A true JPH07506461A (en) 1995-07-13

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JP5512972A Pending JPH07506461A (en) 1992-01-22 1993-01-21 Integrated circuit with quantum well p-channel field effect transistor and complementary transistor

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EP (1) EP0623244A1 (en)
JP (1) JPH07506461A (en)
WO (1) WO1993015523A1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2189345A (en) * 1986-04-16 1987-10-21 Philips Electronic Associated High mobility p channel semi conductor devices
FR2619250B1 (en) * 1987-08-05 1990-05-11 Thomson Hybrides Microondes DOUBLE HETEROJUNCTION HYPERFREQUENCY TRANSISTOR
DE68926256T2 (en) * 1988-01-07 1996-09-19 Fujitsu Ltd Complementary semiconductor device
JPH02202029A (en) * 1989-01-31 1990-08-10 Sony Corp Compound semiconductor device

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EP0623244A1 (en) 1994-11-09
WO1993015523A1 (en) 1993-08-05

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