JPH0750561A - Semiconductor circuit device - Google Patents

Abstract

PURPOSE:To provide a compact semiconductor circuit device while maintaining both rise and fall times. CONSTITUTION:A semiconductor circuit device 1 consists of a clock pulse generating circuit 21, and a time control circuit 2 which applies a control means 22 and a buffer means 24. The circuit 21 serves as an RC oscillating circuit which transmits a binary clock pulse 21a of the frequency about 100 times as high as a drive pulse 5a, etc. There pulses 5a are supplied directly or via an inverter 23C to the control terminals of the clocked inverters 23A and 23B of the means 22. Thus the inverter 23A inverts the pulse 21a in accordance with the pulse 5a, and the inverter 23B transmits the pulse 21a which is inverted again by an inverter 23D to the control terminal of the means 24 in accordance with the pulse 5a. The means 24 serves as a clocked buffer which transmits an intermittent gate signal 4a, etc., when the pulse 5a has a high level and then set in a high impedance state when the pulse 5a has a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure suitable for miniaturization of a semiconductor circuit device configured to reduce switching noise.

[0002]

2. Description of the Related Art As a device for driving an inductive load device such as a spindle motor for a hard disk drive device, a field effect transistor (hereinafter sometimes abbreviated as MOS) and a drive for turning on / off this MOS. It is well known that a driving device composed of a semiconductor circuit composed of a circuit is already widely used. Figure 4
FIG. 5 is a circuit diagram showing such a general drive device together with peripheral devices, and FIG. 5 is a circuit configuration diagram showing a semiconductor circuit device of a conventional example as the drive device shown in FIG. 4 together with related peripheral devices. Is. In addition, in FIGS. 4 and 5, in the devices having the same configuration, only the typical reference symbols are given to the symbols assigned to one device.

First, in FIG. 4, 3 is a three-phase electric motor as a load device having a first-phase fixed winding 3A, a second-phase fixed winding 3B, and a third-phase fixed winding 3C. Yes, terminals 3a, 3b and 3c are provided for inputting the respective fixed windings 3A, 3B and 3C. 7 is each fixed winding 3A, 3B and 3C
In addition, the semiconductor circuit device is a driving device that outputs the respective driving currents 7A, 7B and 7C with a phase difference of 2π / 3 [rad] in electrical angle. As the voltage generated in the three-phase electric motor 6, for example, a voltage 61 generated at the terminal 3a is input, the frequency output from the semiconductor circuit device 7 is detected from the waveform of the voltage 61, and this frequency is illustrated. The control circuit device compares the frequency command value 62 from the non-control command device and outputs individual control commands 6A, 6B and 6C to the respective semiconductor circuit devices 7 from the comparison result.

As shown in detail in FIG. 5, the semiconductor circuit device 7 is provided with terminals 7a, 7b, 7c and 7d, and an individual control command 6A (however, the fixed winding of the three-phase motor 3 is carried out through the terminal 7d. This is the case of the semiconductor circuit device which supplies the drive current 7A to the line 3A) is input to the drive pulse generation circuit 5. The drive pulse generation circuit 5 uses the individual control command 6
(Hereinafter, when the individual control commands 6A, 6B, and 6C are collectively referred to, this may be said.), And the high level shown in FIG. 6 (hereinafter, abbreviated as “H”). Drive pulses 5a and 5b having binary levels of low level (hereinafter, may be abbreviated) and low level (hereinafter, may be abbreviated as "L") are generated and output to the separate time adjustment circuit 8. The drive pulses 5a and 5b are, as shown in FIG.
Each frequency corresponds to the rotation speed of the three-phase motor 3;
f, and therefore, a period corresponding to this frequency (f); T ₀ , time; H, period having T _ON , and time; L period having T _0FF alternate. Repeated in a rectangular shape. However, the drive pulse 5a and the drive pulse 5b have a phase difference of π [rad] in electrical angle.

Each of the time adjustment circuits 8 has a buffer 8
1, an electric resistance element 82 and a capacitor element 83, and the electric resistance element 82 and the capacitor element 83 are
At the time of CR in cooperation with the gate capacitance of the enhancement type n-type MOS (hereinafter sometimes referred to as nEMOS) 4A or the enhancement p-type MOS (hereinafter sometimes referred to as pEMOS) 4B. A delay circuit based on a constant (hereinafter, may be abbreviated as CR delay circuit) is configured. Each of these time adjustment circuits 8 inputs the driving pulse 5a or the driving pulse 5b,
By using the well-known function of the CR delay circuit after buffering the drive pulse 5a or 5b in the buffer 81, the rise time when the drive pulse 5a, 5b is switched from "L" to "H". , And the fall time when switching from “H” to “L” is adjusted to the length required by the system shown in FIG. 4 and output as the gate signals 4a and 4b, respectively.

The nEMOS 4A and the pEMOS 4B have a well-known structure, and are connected to each other at their drains and then between the power source 9A and the ground 9B. The power supply 9A is connected to the terminal 7a, the ground 9B is connected to the terminal 7b, and the connection point between the pEMOS 4B and the nEMOS 4A is connected to the terminal 7c. Again, pE
The gate signal 4b given to the MOS4B is pEMOS.
It is supplied via the inverter 71 in order to match the characteristics of 4B.

The semiconductor circuit device 7 having the above-mentioned structure is adapted to the drive pulses 5a and 5b by the time adjusting circuit 8.
Moreover, the gate signals 4a and 4b having the rise time and the fall time adapted to this system are supplied to the nEMOS 4A and pEM.
Give to OS4B. To this end, nEMOS 4A and p
The EMOS 4B is turned on / off gradually and alternately by the above-described rising time and falling time of the gate signals 4a and 4b. As a result, the voltage of the terminal 7c is gradually switched to a voltage close to the voltage of the power source 9A and the voltage of the ground 9B alternately in the cycle (T ₀ ) by the above-described rising time and falling time. The value of the frequency (f) corresponding to the period (T _0), the number [kH _z] to several tens [k
H _z ].

As a result, the drive currents 7A, 7B and 7C flowing through the fixed windings 3A, 3B and 3C of the three-phase motor 3 increase or decrease with a phase difference of 2π / 3 [rad] in electrical angle. The current becomes a current and the three-phase motor 3 is operated at a desired rotation speed, and the rate of change of the current value of each drive current; di / dt is relaxed to an appropriate value. As a result, in proportion to the current value change rate (di / dt), the reactance of the fixed windings 3A, 3B and 3C; the counter electromotive force generated in L; v [= -L · (di / dt)] By reducing the value, the noise component superimposed on the voltage 61 is reduced, and the control circuit device 6 is operated without being affected by noise.

By the way, the semiconductor circuit device 7 is an nEMOS.
As a matter of course, 4A and pEMOS 4B are MOS, for example, the drive pulse generating circuit 5, the inverter 71,
A semiconductor used in the manufacture of a semiconductor integrated circuit, such as a MOS is used as an active element forming the buffer 81, a diffusion resistance is used as the electric resistance element 82, and a MOS gate oxide film is used as a dielectric of the capacitor element 83. A small-sized circuit device is often manufactured by applying the manufacturing process to manufacture a so-called one-chip product.

Further, the semiconductor circuit device has either nEMOS 4A or pEMOS 4B as a MOS, and is provided with a drive pulse generating circuit 5 and one time adjusting circuit 8 to supply an intermittent current to the load device. The device made into is also known.

[0011]

In the above-described semiconductor circuit device according to the prior art, it is possible to operate the system including the control circuit device 6 without being affected by noise, and also to reduce the size to some extent. Has already been achieved, but there are the following problems. That is, a CR delay circuit capable of obtaining a rise time and a fall time of 200 [μS] for the semiconductor circuit device 7 will be described below by taking as an example a case where a semiconductor manufacturing process of the 2 [μm] rule is applied. In this case, the area occupied by the capacitor element of unit capacity on the semiconductor substrate is about 800 [μm ² / pF].
The area occupied by the electric resistance element having a unit resistance value on the semiconductor substrate is about 1000 [μm ² / kΩ]. nEM
The gate capacitance of OS4A and pEMOS4B is about 300 [p
Considering that F], the values of the electric resistance element 82 and the capacitor element 83, which occupy the minimum area on the semiconductor substrate, are examined. The values are about 270 [kΩ] and about 4 respectively.
The required area per CR delay circuit, which is the sum of these elements, is about 300 × 10 ³ [μF].
m ² ].

However, for example, in hard disk drive devices, miniaturization is rapidly progressing, and accordingly, further miniaturization is strongly demanded for semiconductor circuit devices as devices for driving the spindle motor. Is becoming popular. The present invention has been made in view of the problems of the above-mentioned conventional technology, and its object is to:
An object of the present invention is to provide a miniaturized semiconductor circuit device while maintaining a desired length of rise time and fall time.

[0013]

SUMMARY OF THE INVENTION In the present invention, the above objects are as follows: 1) a gate signal having a binary signal level of "H" and "L" for turning on and off the MOS. Is provided to the gate of the MOS, the drive circuit is configured to output a binary drive pulse, and the drive pulse is from “L” to “H”.
And a time adjusting circuit for adjusting the length of the rising time when switching to "L" and the length of the falling time when switching from "H" to "L", and giving the gate to the gate of the MOS. In the semiconductor circuit device, the time adjustment circuit included in the drive circuit outputs a clock pulse (hereinafter, may be abbreviated as CP) having a binary pulse level (hereinafter, abbreviated as CP) (hereinafter abbreviated as CP generation circuit). , And a drive pulse and CP, and outputs a multi-bit binary number that increases or decreases according to the value of the drive pulse, a switching element, and an electrical resistance. A resistance circuit section comprising a unit electric resistance element combined with an element, the resistance circuit section being inserted between a power supply terminal and a ground terminal, Has an intermediate connection point between the end on the power supply side and the end on the ground side, and has a plurality of unit electric resistance elements between the end on the power supply side and the end on the ground side, and between the end on the intermediate side and the ground side. The switching elements included in the resistance circuit section are connected in series, and are turned on / off in accordance with the binary value output from the up / down counter circuit section. It is configured to output a gate signal from the connection point to the gate provided in the MOS, and 2) in the means described in the above item 1, the unit electric resistance element included in the resistance circuit unit is an electric resistance element, A first switching element connected in series with the electric resistance element and a second switching element connected in parallel with a series connection circuit of the electric resistance element and the first switching element. The first switching element and the second switching element correspond to the binary value of each bit output from the up / down counter circuit section when one of the switching elements is turned on. The other switching element is configured to be turned off, and 3) the unit electric resistance element of the resistance circuit section in the means described in 1 above, wherein the switching element is a field effect transistor, and The field-effect transistor also functions as an electric resistance element, and 4) a MOS and a gate signal having a binary signal level of "H" and "L" for turning the MOS on or off. , A drive circuit for giving to a gate provided in the MOS, the drive circuit including a drive pulse generation circuit for outputting a binary drive pulse, Motion pulse is from "L" to "H"
And a time adjusting circuit for adjusting the length of the rising time when switching to "L" and the length of the falling time when switching from "H" to "L", and giving the gate to the gate of the MOS. In the semiconductor circuit device, the time adjustment circuit included in the drive circuit has a CP having a binary pulse level.
Is provided with a CP generating circuit, a buffer means having a control terminal, and a controlling means. The buffer means receives the drive pulse output from the drive pulse generating circuit and outputs a gate signal corresponding to the drive pulse to a MOS. When the signal corresponding to CP is input to the control terminal, the pulse level of CP is "H".
When the gate signal of “H” is output, and when the pulse level of CP is “L”, the gate signal of “L” is output and the signal corresponding to CP is not input to the control terminal. Is in a high impedance state, the control means inputs the drive pulse output from the drive pulse generation circuit, and when the drive pulse is “H”,
When the signal corresponding to CP is transmitted to the control terminal provided in the buffer means and the drive pulse is "L", C
It is achieved by stopping the transmission of the signal corresponding to P to the buffer means.

[0014]

According to the present invention, in the semiconductor circuit device, the time adjustment circuit of the drive circuit is inputted with the CP generation circuit for outputting the CP having the binary pulse level and the drive pulse and the CP. An up-down counter circuit unit that outputs a multi-bit binary number that increases or decreases in accordance with a value, and a resistance circuit unit that includes a unit electric resistance element in which a switching element and an electric resistance element are combined are provided. The resistor circuit section is inserted between the power supply terminal and the ground terminal, has an intermediate connection point between the power supply side end and the ground side end, and is connected to the power supply side end. A plurality of unit electric resistance elements are connected in series between the connection points and between the intermediate connection point and the end portion on the ground side, and the unit electric resistance elements are, for example, electric resistance elements. And a first switching element connected in series to the electric resistance element, and a second switching element connected in parallel to the series connection circuit of the electric resistance element and the first switching element. And the first switching element and the second switching element are
According to the binary value of each bit output from the up / down counter circuit unit, when one switching element is turned on, the other switching element is turned off. The switching element is turned on / off in response to the binary value output from the up / down counter circuit section, and is configured to output a gate signal from the intermediate connection point of the resistance circuit section to the gate of the MOS. Therefore, when the drive pulse output from the drive pulse generation circuit of the drive circuit is “H”, the up / down counter circuit unit increases the multi-bit binary number each time CP is received. Is output. According to the binary number, the resistance circuit portion receiving this output turns off the second switching element when the first switching element turns on and turns off the second switching element when the first switching element turns off. When the second switching element is turned on, the resistance value of the unit electric resistance element is set to the resistance value of the electric resistance element in the former case, and to almost zero in the latter case. The first switching element and the second switching element of each unit electric resistance element are sequentially turned on and off in accordance with a multi-bit binary number to sequentially turn on and off between the end on the power supply side and the intermediate connection point. The combined resistance value is sequentially decreased for each CP cycle, and the combined resistance value between the intermediate connection point and the end on the ground side is sequentially increased for each CP cycle. As a result, the voltage at the intermediate connection point determined by the ratio of the combined resistance value between the end on the power supply side and the end on the ground side to the combined resistance value on the end on the ground side is equal to the drive pulse. Immediately after switching to "H", the ground voltage is increased stepwise in every CP cycle, and at "H" at the maximum value of the multi-bit binary number of the up-down counter circuit unit. A voltage difference between a certain power supply voltage and the ground voltage is reached. The voltage obtained at such an intermediate connection point is given to the gate of the MOS as a gate signal. In the MOS, the gate voltage is the gate signal due to the action of the gate capacitance existing in the gate portion of the MOS. Since the voltage rises with a delay with respect to the voltage at the point, the current value change rate (di / dt) when the drive current supplied to the load device by the MOS increases is gradual.

When the drive pulse output from the drive pulse generating circuit of the drive circuit becomes "L", the up-down counter circuit section sequentially decreases from the maximum value every time it receives CP, and is a multi-bit binary number. Is output. The resistance circuit section that receives this output basically operates in the same manner as when the drive pulse is "H", and the voltage at the intermediate connection point is changed to the power supply immediately after the drive pulse is switched to "L". The difference voltage between the voltage and the ground voltage is reduced stepwise in every CP cycle, and the ground voltage is “L” at the minimum value of the multi-bit binary number output from the up / down counter circuit unit. Descend to. The voltage obtained at such an intermediate connection point is given to the gate provided in the MOS.
Due to the function of the gate capacitance of the device, its gate voltage drops with a delay with respect to the voltage at the intermediate connection point, so the current value change rate (di / dt) when the drive current supplied to the load device by the MOS decreases. Will be loose.

In the unit electric resistance element of the resistance circuit section, the switching element is a MOS and
By adopting a configuration in which the OS also serves as an electric resistance element, it becomes possible to reduce the required area of the resistance circuit section when obtaining the action according to the above item. The time adjustment circuit included in the drive circuit includes a CP generation circuit that outputs a CP having a binary pulse level, buffer means having a control terminal, and control means, and the buffer means outputs the drive pulse generation circuit. A drive pulse is input, and a signal corresponding to this drive pulse is given to the gate of the MOS. When a signal corresponding to CP is input to its control terminal, the pulse level of CP is "H". When the gate signal of “H” is output, and when the pulse level of CP is “L”, the gate signal of “L” is output and the signal corresponding to CP is not input to the control terminal. Is in a high impedance state, the control means inputs the drive pulse output from the drive pulse generation circuit, and when the drive pulse is "H", it corresponds to CP. By outputting the signal to the control terminal provided in the buffer means, and stopping the output of the signal corresponding to CP to the buffer means when the drive pulse is “L”. When the drive pulse output from the drive pulse generation circuit included in the drive circuit is “H”, the control unit outputs a signal corresponding to CP to the control terminal provided in the buffer unit. In the buffer means, since the signal corresponding to CP is input to the control terminal, the gate signal which is “H” is output during the period when CP is “H”, and the “gate” is output during the period when CP is “L”. It outputs a gate signal that is "L". Such a CP "H" /
Corresponding to "L", a comb-tooth-shaped gate signal alternately switching between "H" and "L" is given to the gate of the MOS. However, in the MOS, the function of the gate capacitance existing in the gate portion works. As a result, the gate voltage rises gently every period when CP is “H”, and rises to “H” within the period when the drive pulse is “H”.
As a result, the current value change rate (di / dt) when the drive current supplied to the load device by the MOS increases becomes gentle.

When the drive pulse output from the drive pulse generating circuit of the drive circuit is "L", the control means stops outputting the signal corresponding to CP to the buffer means. In the buffer means, a signal corresponding to CP is not input to the control terminal, so that it enters a high impedance state. Therefore, in this case, the gate of the MOS is connected to the voltage of "L" through the high-impedance buffer means. As a result, the charge accumulated in the gate capacitance of the MOS during the period when the drive pulse is “H” is “L” in the gate portion of the MOS.
Is "L" through the leakage resistance with respect to the voltage which is "L" and the leakage resistance with respect to the voltage which is "L" of the buffer means.
Is discharged to a voltage that is As a result, the gate voltage of the MOS gently drops, so that the current value change rate (di / dt) when the drive current supplied by the MOS to the load device decreases becomes gentle.

[0018]

Embodiments of the present invention will be described in detail below with reference to the drawings. Embodiment 1 FIG. 2 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claims 1 and 2 together with related peripheral devices. 2, the same parts as those of the semiconductor circuit device according to the conventional example shown in FIG. 5 and related peripheral devices are designated by the same reference numerals, and the description thereof will be omitted. In addition, in FIG. 2, about the code | symbol attached in FIG. 5, only the typical code | symbol was described. In addition, in FIG. 2, in the devices having the same configuration, only the typical reference signs are given to the reference signs assigned to one device.

In FIG. 2, 1A is the conventional one shown in FIG.
For the semiconductor circuit device 7 according to the example, the time adjustment circuit 8
Semiconductor circuit in which the time adjustment circuit 2A is used instead
It is a device. The time adjustment circuit 2A includes the CP generation circuit 21.
And the up / down counter circuit section 25 and the resistance circuit section 2
6 and. The CP generation circuit 21 uses the drive pulse 5
For the frequency (f) of a and 5b, for example, 100
Double high frequency; f _CAnd has a binary pulse
It outputs the CP21a with a level of 20
Capacitor element of [pF] and electric resistance of 10 [kΩ]
A so-called RC oscillator circuit including an element and a MOS
It

The up / down counter circuit section 25 includes a well-known 3-bit binary up / down counter and CP21a.
Is input and a well-known counter that transmits a stop signal when eight pulses of CP21a are counted, and CP21a is input and always outputs this pulse 21a toward a binary up / down counter. When it is transmitted, a well-known switching circuit that stops the output of the pulse 21a toward the binary up / down counter is provided. Binary up / down counter is CP2
The drive pulse 5a or 5b is input together with 1a, the drive pulse 5a, 5b is used as a control signal to perform up-counting / down-counting, and a 3-bit binary number and its complement D ₀ , D ₀ B (2 ⁰ Binary digit and its complement), D
₁ , D ₁ B (2 ^1- digit binary number and its complement) and D ₂ , D
Outputs ₂ B (2 ² digit binary number and its complement). The counter that outputs the stop signal is reset when the drive pulse 5a or 5b is input and the drive pulse 5a or 5b is switched to "H" → "L" or "L" → "H".

In the up-down counter circuit section 25 having the above-mentioned circuit configuration, when the drive pulses 5a and 5b are switched from "L" to "H", for example, the counter which issues the stop signal is reset and the CP21a Since the switching circuit is on for up to 7 pulses, the binary up / down counter counts up and outputs a sequentially increasing 3-bit binary number (D ₀ , to D ₂ B). When CP21a reaches the 8th pulse, the switching circuit is turned off, and the counting thereafter is stopped.
The advance up / down counter continues to output the 3-bit binary number (D ₀ , to D ₂ B) of the seventh pulse. At this time, if the drive pulses 5a and 5b are switched to, for example, "L", the counter that transmits the stop signal is reset and the CP
The binary up / down counter down-counts by the pulse from 21a, and outputs a 3-bit binary number (D ₀ , up to D ₂ B) which is sequentially decreased. In addition, 8 of CP21a
After the pulse, the binary up / down counter continues to output the 3-bit binary number (D ₀ , to D ₂ B) of the 7th pulse.

The resistance circuit section 26 includes six unit electric resistance elements (hereinafter, may be simply referred to as resistance elements) 27A,
To 27F in a series connection circuit, the end 26a on the side of the resistance element 27A is connected to the power supply 9A, the end 26b on the side of the resistance element 27F is connected to the ground 9B, and the resistance element 27 is connected.
Intermediate connection point 26c which is a connection point between C and the resistance element 27D
Are connected to the gates of nEMOS 4A and pEMOS 4B. Each unit electric resistance element 27 (hereinafter, this may be said when the unit electric resistance elements 27A and 27F are collectively referred to) is referred to as an electric resistance element 271.
A well-known transmission gate (hereinafter, sometimes abbreviated as TG) 272, which is a first switching element connected in series to the electric resistance element 271, and a series connection circuit of the electric resistance element 271 and the TG 272. TG which is the second switching element connected in parallel to
273 and. The outputs from the up / down counter circuit unit 25 are input to the TGs 272 and 273 as shown in the figure, and among the 3-bit binary numbers (D ₀ , to D ₂ B) output by the up / down counter circuit unit 25, Corresponding to the binary number of each digit and the value of its complement, the operation is such that when one TG is on, the other TG is off.

The resistance values of the electric resistance elements 271 included in the resistance elements 27A and 27F are, for example, the electric resistance elements 27 included in the resistance elements 27A and 27F.
The resistance value of 1 is 4 [kΩ], the resistance element 27B and the resistance element 2
The resistance value of the electric resistance element 271 included in 7E is 2 [k
Ω], and the resistance value of the electric resistance element 271 included in the resistance element 27C and the resistance element 27D is 1 [kΩ]. On the basis of the value of the resistance element 27C, the value of the resistance element 27D is set to a single value, the values of the resistance elements 27B and 27E are set to a double value, and the values of the resistance elements 27A and 27F are set to a quadruple value. .
These values are significantly smaller than the resistance value of about 270 [kΩ] of the electric resistance element 82 used in the conventional semiconductor circuit device 7.

From the intermediate connection point 26c of the resistance circuit section 26 of the time adjustment circuit 2A, the nEMOS 4A is connected.
And a gate signal 4a and a gate signal 4b applied to the gates of the pEMOS 4B and pEMOS 4B, respectively. Furthermore, the gate signal 4b given to the pEMOS 4B
Is supplied via the inverter 71 in order to match the characteristics of the pEMOS 4B, as in the case of the semiconductor circuit device 7 of the conventional example.

The semiconductor circuit device 1A having the above structure operates as follows. Here, the case of the gate signal 4a given to the gate of the nEMOS 4A will be mainly described. First, when the drive pulse 5a is "H", the up-down counter circuit unit 25 performs up-counting, for each pulse of CP21a, successively 3 bit binary number which increases (D _0, to D ₂ B ) Is output. As shown in FIG. 2, these binary numbers (D ₀ , to D ₂ B) are input to the respective resistance circuit elements 27 included in the resistance circuit unit 26. For example, if the first CP 21a is input,
Since D ₀ , D ₁ B and D ₂ B are 1, it becomes “H”,
Since D ₀ B, D ₁ and D ₂ are 0, it becomes “L”. As a result, the TG 272 included in the resistance elements 27A, 27B and 27D is turned on, and the resistance elements 27C and 27C are turned on.
The TG 272 included in E and 27F is turned off.

On the contrary, the resistance elements 27A, 27
TG273 provided in B and 27D is turned off, and TG27 provided in resistance element 27C and resistance elements 27E and 27F.
3 turns on. Therefore, the end portion 26 of the resistance circuit portion 26 is
The electric resistance value between a and the intermediate connection point 26c is the resistance element 2
6 times the value of 7C, the intermediate connection point 26c and the end 26
The electric resistance value between b and 1 is a value that is one time the value of the resistance element 27C. As a result, the voltage at the intermediate connection point 26c is
It becomes 1/7 of the voltage between the ground and 9B. After that, CP
The voltage at the intermediate connection point 26c is stepped by 1/7 of the voltage between the power supply 9A and the ground 9B for each pulse of CP21a by repeating the predetermined ON / OFF of the TG272 and TG273 for each pulse of 21a. Rise to the shape. When the voltage of the intermediate connection point 26c receives the CP21a of the 7th pulse which is the maximum value of the 3-bit binary number, it receives the power supply 9A and the ground 9
The voltage between B and that is, "H". The voltage at the intermediate connection point 26c is nEMO as the gate signal 4a.
It is given to the gate provided in S4A.

However, in the gate part of the nEMOS 4A,
As described above, there is a gate capacitance of about 300 [pF]. Since the voltage obtained by charging the gate capacitance with the voltage of the gate signal 4a is the gate voltage of the nEMOS 4A, this gate voltage is delayed with respect to the voltage of the gate signal 4a and rises. As a result, the rate of change in current value (di / dt) when the drive current supplied to the load device by the nEMOS 4A increases becomes gradual.

Next, when the drive pulse 5a is "L", the up / down counter circuit section 25 causes the CP 21a to operate.
The down-counting is performed for each pulse of, and a 3-bit binary number (D ₀ , to D ₂ B) that sequentially decreases from the maximum value 7 is output. Each resistance circuit element 27 included in the resistance circuit unit 26 that receives this output basically operates in the same manner as when the drive pulse is “H”, and the voltage at the intermediate connection point 26c is changed to
Immediately after the drive pulse 5a is switched to "L", the power source 9
What was between the voltage of A and the ground 9B was changed to C
It gradually decreases in a stepwise manner for each period of P, and at 0, which is the minimum value of the 3-bit binary number output from the up / down counter circuit unit 25, drops to the ground voltage which is “L”. The voltage obtained at the intermediate connection point 26c is applied to the gate of the nEMOS 4A as the gate signal 4a.

However, in the gate capacitance of the nEMOS 4A, charges corresponding to the gate voltage are accumulated during the period when the drive pulse 5a is "H", and the reduced voltage value of the gate signal 4a and the gate voltage are generated. The gate voltage of the nEMOS 4A is in a relationship of being lowered by discharging this charge due to the difference voltage. For this reason, this gate voltage drops with a delay with respect to the voltage at the intermediate connection point 26c, so that nE
The current value change rate (di / dt) when the drive current supplied to the load device by the MOS 4A decreases is moderate.

In the semiconductor circuit device 1A, if the time adjustment circuit 2A used in place of the time adjustment circuit 8 provided in the semiconductor circuit device 7 is obtained by applying the semiconductor manufacturing process of the 2 [μm] rule, The area occupied on the semiconductor substrate is as follows. That is,
If the diffusion resistance is used for the electric resistance element and the MOS gate oxide film is used for the dielectric of the capacitor element, the CP generation circuit 21 requires a required area of about 140 × 10 ³ [μm ² ]. Further, the up / down counter circuit unit 25 is a MOS
The number of required circuit elements is about 50 in terms of CMOS. Further, in the resistance circuit unit 26, the TGs 272 and 273 are of course composed only of CMOS, and a diffusion resistance is used for the electric resistance element 271. In the case of this configuration, the total required area of the up / down counter circuit section 25 and the resistance circuit section 26 is about 40 × 10 ³ [μm ² ]. Therefore, the total required area per circuit of the time adjustment circuit 2A is about 1
It is reduced to 80 × 10 ³ [μm ² ].

Embodiment 2; FIG. 3 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claims 1 and 3 together with related peripheral devices. 3, the same parts as those of the semiconductor circuit device according to the present invention corresponding to claims 1 and 2 shown in FIG. 2 and the semiconductor circuit device according to the conventional example shown in FIG. The description is omitted. In addition, in FIG. 3, in the devices having the same configuration, only the typical reference signs are given to the reference signs assigned to one device.

In FIG. 3, 1B is a semiconductor circuit device 1A according to the present invention corresponding to claims 1 and 2 shown in FIG.
However, instead of the time adjustment circuit 2A, the resistance circuit unit 28
Is a semiconductor circuit device including a time adjustment circuit 2B adapted to use. The resistance circuit unit 28 includes unit electric resistance elements (hereinafter, may be abbreviated as resistance elements) 29A, ...
A series connection circuit body of 29F, and six resistance elements 29 (hereinafter, the resistance elements 29A and 29F are collectively referred to as the resistance circuit section 26 included in the time adjustment circuit 2A. The end 28a on the side of the resistance element 29A is connected to the power source 9A, and the resistance element 2 is provided.
The end 28b on the 9F side is connected to the ground 9B, and the intermediate connection point 28c, which is a connection point between the resistance element 29C and the resistance element 29D, is connected to the gates of the nEMOS 4A and pEMOS 4B.

Each resistance element 29 is a well-known depletion type n-type MOS which also serves as a switching element.
(Hereinafter, it may be abbreviated as nDMOS.). The nDMOS 29 uses the channel portion as an electric resistance element and selects the width dimension and the length dimension of the channel portion to set the electric resistance value. The electric resistance value is, for example, nD as in the resistance circuit unit 26.
The electric resistance value of the MOS 29A and the nDMOS 29F is 4 [k
Ω], the electric resistance value of nDMOS 29B and nDMOS 29E is 2 [kΩ], and nDMOS 29C and nDMOS
The electric resistance value of 29D is 1 [kΩ]. nDMOS2
Based on the value of 9C, the value of the nDMOS 29D is set to a value of 1, the value of the nDMOSs 29B and 29E is set to a value of 2 times, and the value of the nDMOS 29A and 29F is set to a value of 4 times.

At the gate of each nDMOS 29,
The output from the up / down counter circuit unit 25 is input as shown in the figure, and among the 3-bit binary numbers (D ₀ , to D ₂ B) output by the up / down counter circuit unit 25,
ND corresponding to the binary number of each digit and its complement
The MOS 29 is turned on / off. Also, the time adjustment circuit 2
From the intermediate connection point 28c of the resistance circuit unit 28 included in B, the gate signal 4a and the gate signal 4 provided to the gates included in the nEMOS 4A and pEMOS 4B, respectively.
b is output. Further, the gate signal 4b given to the pEMOS 4B is supplied via the inverter 71 in order to match the characteristics of the pEMOS 4B.
This is similar to the case of the semiconductor circuit device 7 of the conventional example. The operation of the semiconductor circuit device 1B having the above structure is
The case of the gate signal 4a given to the gate of 4A will be mainly described. The operation of the semiconductor circuit device 1B is basically the same as that of the semiconductor circuit device 1A. That is,
When the drive pulse 5a is “H”, for example, when the first CP 21a is input, D ₀ , D ₁ B and D ₂ are input.
Since B is 1, it becomes “H” and D ₀ B, D ₁ and D ₂
Is 0, it becomes “L”. This enables the nDMOS
29C, 29E and 29F turn on, and nDMOS29
Although the A, nDMOS 29B and 29D are turned off, the electric resistance between the drain and the source of the turned-on nDMOS 29 is about 100 [Ω], and the electric resistance between the drain and the source of the turned-off nDMOS 29 is the electric resistance of the above-mentioned channel portion. It is almost the same as the value. Therefore, the electric resistance value between the end portion 28a of the resistance circuit unit 28 and the intermediate connection point 28c is 6 times the value of the nDMOS 29C, and the electric resistance value between the intermediate connection point 28c and the end portion 28b is nDM
It is a value 1 times the value of OS29C.

As a result, the voltage at the intermediate connection point 28c is the same as in the semiconductor circuit device 1A, that is, the power source 9A and the ground 9
It is 1/7 of the voltage between B and. After that, 1 of CP21a
The nDMOS 29 repeats predetermined ON / OFF for each pulse, so that the voltage at the intermediate connection point 28c becomes 1 of CP21a.
1/7 of the voltage between the power supply 9A and the ground 9B for each pulse
It is the same as in the case of the semiconductor circuit device 1A in that the voltage of the intermediate connection point 28c is applied to the gate of the nEMOS 4A as the gate signal 4a as the gate signal 4a. Therefore, by utilizing the gate capacitance of the nEMOS 4A, the current value change rate (di / dt) when the driving current supplied to the load device by the nEMOS 4A increases.
Will be gradual.

Also, when the drive pulse 5a is "L", the operation is basically the same as that of the semiconductor circuit device 1A, so the description thereof will be omitted, but in this case also CP2
For each pulse of 1a, the voltage of the intermediate connection point 28c, which decreases in a stepwise manner, is given to the gate of the nEMOS 4A as the gate signal 4a, and is supplied to the load device by the nEMOS 4A by using the gate capacitance of the nEMOS 4A. Current value change rate (di / d
t) becomes gradual.

In the semiconductor circuit device 1B, assuming that the time adjustment circuit 2B is obtained by applying the semiconductor manufacturing process of the 2 [μm] rule, the area occupied on the semiconductor substrate is as follows. That is, the resistance circuit section 28 composed of the nDMOS 29 that also serves as a switching element and an electric resistance element, and the up / down counter circuit section 2
The total required area for each of the time adjustment circuits 2B is about 170 × 10 ³ [μm ² ], which is about 30 × 10 ³ [μm ² ]. It is further reduced than in the case of 2A.

In the above description of the first and second embodiments,
Although the up-down counter circuit unit 25 has been described as outputting a 3-bit binary number and its complement, it is not limited to this and outputs a 4-bit or higher multi-bit binary number and its complement. Needless to say, the larger the number of bits, the slower the current value change rate (di / dt) when the drive current increases or decreases.

Embodiment 3 FIG. 1 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claim 4 together with related peripheral devices. In FIG. 1, the same parts as those of the semiconductor circuit device according to the present invention corresponding to claims 1 and 2 shown in FIG. 2 and the semiconductor circuit device according to the conventional example shown in FIG. The description is omitted. In addition, in FIG. 1, in the apparatus having the same configuration, only the representative reference numerals are given to the reference numerals assigned to one apparatus.

In FIG. 1, reference numeral 1 is a buffer means 24 in place of the time adjusting circuit 2A in the semiconductor circuit device 1A according to the present invention corresponding to claims 1 and 2 shown in FIG.
And a semiconductor circuit device including the time adjustment circuit 2 configured to use the control means 22. The buffer means 24 is a well-known clocked buffer, receives the drive pulse 5a or 5b, and outputs the gate signal 4a or 4b corresponding to the drive pulse 5a or 5b to the nEMOS 4A or p.
This is given to the gate included in the EMOS 4B. CP
When the signal corresponding to 21a is input to the control terminals 24a and 24b, when the pulse level of CP21a is "H", the gate signals 4a and 4b of "H" are output, and the pulse level of CP21a is "L" for "L"
The gate signals 4a and 4b of
When the signal corresponding to is not input to the control terminals 24a and 24b, the high impedance state is set.

The control means 22 includes two well-known clocked inverters 23A and 23B and two well-known inverters 23C and 23D. The clocked inverter 23A is configured to directly input the CP 21a, to one control terminal thereof via the inverter 23C, and to the other control terminal thereof directly to the drive pulses 5a and 5b. There is. Clocked inverter 23
B is that the circuit configuration is such that the CP 21a is input via the inverter 23D.
Different from A.

When the driving pulses 5a and 5b are "H", the control means 22 thus constructed is directed from the clocked inverter 23A to one control terminal 24a of the buffer means 24. , CP21a is inverted and then output as signal 22a.
From the inverter 23B, the CP 21a is re-inverted toward the other control terminal 24b of the buffer means 24 and then output as a signal 22b. These signals 22a
The signal 22b and the signal 22b have the same waveform as that of the CP 21a, and have a relationship in which they are mutually inverted. Further, when the drive pulses 5a and 5b are "L", the clocked inverters 23A and 23B are both in the high impedance state, and the output of the signals 22a and 22b is stopped.

The gate signal 4b given to the pEMOS 4B is supplied via the inverter 71 in order to match the characteristics of the pEMOS 4B, as in the case of the semiconductor circuit device 7 of the conventional example. The semiconductor circuit device 1 having the above configuration operates as follows. First,
When the driving pulse 5a or 5b is "H",
The control means 22 receives the signals 22a,
22b is output to the control terminals 24a and 24b. In the buffer means 24, since the signals 22a and 22b are input to the control terminals 24a and 24b, the gate signal which is "H" is output while the CP21a is "H", and the CP21a is "L". The gate signal 4a. 4b is output.

In this way, the CP21a "H" / "L"
Corresponding to the comb-shaped gate signal 4a. 4b is nEMOS4A or pE
It is given to the gate of the MOS 4B. However, nE
As described above, the gate capacitance of the MOS 4A and pEMOS 4B has a gate capacitance of about 300 [pF].
The voltage obtained by charging the gate capacitance with the voltage in the “H” period by the gate signals 4a and 4b is nEMO.
Since it is the gate voltage of S4A and pEMOS4B, this gate voltage gradually rises due to the interruption of the gate signals 4a and 4b, and the gate voltage of the power source 9A and The voltage will rise to "H", which is the voltage between the ground 9B. As a result, nE
The current value change rate (di / dt) when the drive current supplied to the load device by the MOS 4A and the pEMOS 4B increases is moderate.

Next, when the drive pulse 5a or 5b is "L", the control means 22 outputs the signals 22a and 22b to the control terminals 24a and 24b as described above.
Stop outputting to. In the buffer means 24, the signals 22a and 22b are not input to the control terminals 24a and 24b, so that they are in a high impedance state. Therefore, the gates of the nEMOS 4A and pEMOS 4B are connected to the ground 9B of "L" via the buffer means 24 having high impedance. In this case, the charges stored in the gate capacitances of the nEMOS 4A and pEMOS 4B while the drive pulses 5a and 5b are “H” are nEMOS 4A and pEMOS.
Leakage resistance between the 4B gate and the ground 9B,
Alternatively, it is discharged to the ground 9B through a leakage resistance between the buffer means 24 and the ground 9B. As a result, the gate voltages of nEMOS4A and pEMOS4B are
Since it will fall slowly, nEMOS4A, p
The current value change rate (di / dt) when the drive current supplied to the load device by the EMOS 4B decreases is gradual.

In the semiconductor circuit device 1, assuming that the time adjustment circuit 2 is obtained by applying the semiconductor manufacturing process of the 2 [μm] rule, the area occupied on the semiconductor substrate is as follows. That is, the required area of the control means 22 and the buffer means 24, both of which can be composed of CMOS, is about 10 × 10 ³ [μm ² ], and therefore the total time per circuit of the time adjusting circuit 2 is the total. The required area is about 150 × 10 ³ [μm ² ], which is further reduced as compared with the case of the time adjustment circuit 2B.

Moreover, it is possible to easily generate the finely interrupted gate signals 4a and 4b by using the CP21a for the drive pulses 5a and 5b while reducing the required area in this way, so that the drive current is increased or decreased. It is possible to easily make the current value change rate (di / dt) with time gentle. In the above description of Examples 1 to 3, C
Although the P generation circuit is provided in each time adjustment circuit, the present invention is not limited to this. For example, the CP generation circuit may be provided in only one time adjustment circuit, or may be provided separately from the time adjustment circuit. This is the only one
The CP may be supplied from all the CP generation circuits to all the time adjustment circuits.

[0048]

The present invention has the following effects due to the above-mentioned configuration. In other words, by using only the gate capacitance of the field effect transistor that outputs the drive current as the delay element, the desired length of rise time and fall time is maintained and the required area of the time adjustment circuit is About 60 in case of conventional example
[%] Or less, it is possible to downsize the semiconductor circuit device.

Since the rate of change of the current value when the drive current is increased or decreased can be made more gradual, the problem due to noise can be further reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claim 4 together with related peripheral devices.

FIG. 2 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claims 1 and 2 together with related peripheral devices.

FIG. 3 is a circuit configuration diagram showing a semiconductor circuit device according to an embodiment of the present invention corresponding to claims 1 and 3 together with related peripheral devices.

FIG. 4 is a circuit diagram showing a general driving device together with peripheral devices.

FIG. 5 is a circuit configuration diagram showing a semiconductor circuit device of a conventional example together with related peripheral devices.

FIG. 6 is a waveform diagram of the drive pulse shown in FIG.

[Explanation of symbols]

 1 Semiconductor Circuit Device 1A Semiconductor Circuit Device 1B Semiconductor Circuit Device 2 Time Adjustment Circuit 2A Time Adjustment Circuit 2B Time Adjustment Circuit 21 Clock Pulse Generation Circuit 21a Clock Pulse 22 Control Means 23A Clocked Inverter 23B Clocked Inverter 23C Inverter 23D Inverter 24 Buffer means 4A Field effect transistor 4B Field effect transistor 4a Gate signal 5 Drive pulse generation circuit 5a Drive pulse

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/687 17/695

Claims (4)

[Claims] 1. A field effect transistor, and a drive circuit for applying a gate signal having a binary signal level of a high level and a low level for turning on or off the field effect transistor to a gate provided in the field effect transistor. The drive circuit includes a drive pulse generation circuit that outputs a binary drive pulse, and a rise time length when the drive pulse is switched from a low level to a high level,
And a time adjusting circuit which adjusts the length of the fall time when switching from the high level to the low level and then gives the time to the gate of the field effect transistor. In the semiconductor circuit device, the time adjusting circuit included in the drive circuit is provided. Is a clock pulse generation circuit that outputs a clock pulse having a binary pulse level, a drive pulse and a clock pulse that are input, and outputs a multi-bit binary number that increases or decreases according to the value of the drive pulse. An up / down counter circuit unit, and a resistance circuit unit including a unit electric resistance element in which a switching element and an electric resistance element are combined,
It is inserted between the terminal for power supply and the terminal for ground, has an intermediate connection point between the end on the power supply side and the end on the ground side, and between the end on the power supply side and the intermediate connection point, and A plurality of unit electric resistance elements are connected in series between the intermediate connection point and the end on the ground side, and the switching element included in the resistance circuit section outputs 2 from the up / down counter circuit section. A semiconductor which is turned on / off according to a value of a base number, and is configured to output a gate signal from an intermediate connection point of a resistance circuit section to a gate provided in a field effect transistor. Circuit device. 2. The semiconductor circuit device according to claim 1, wherein the unit electric resistance element included in the resistance circuit section includes an electric resistance element, a first switching element connected in series to the electric resistance element, and an electric resistance. A second switching element connected in parallel to a series connection circuit of the element and the first switching element, wherein the first switching element and the second switching element are up-down counter circuits. A semiconductor circuit characterized in that, when one switching element is turned on, the other switching element is turned off in accordance with the binary value of each bit output by the unit. apparatus. 3. The semiconductor circuit device according to claim 1, wherein, in the unit electric resistance element of the resistance circuit section, the switching element is a field effect transistor, and the field effect transistor also serves as an electric resistance element. A semiconductor circuit device characterized by the above. 4. A field effect transistor, and a drive circuit for applying a gate signal having a binary signal level of a high level and a low level for turning on or off the field effect transistor to a gate provided in the field effect transistor. The drive circuit includes a drive pulse generation circuit that outputs a binary drive pulse, the length of the rise time when the drive pulse switches from the low level to the high level, and the fall time when the drive pulse switches from the high level to the low level. In the semiconductor circuit device, the time adjustment circuit included in the drive circuit has a time adjustment circuit that adjusts the length of A clock pulse generation circuit for outputting, a buffer means having a control terminal, and a control means. The buffer means receives the drive pulse output from the drive pulse generation circuit, and applies a gate signal corresponding to the drive pulse to the gate of the field effect transistor, and a signal corresponding to the clock pulse. Is input to the control terminal, a high-level gate signal is output when the pulse level of the clock pulse is high level, and a low-level gate signal is output when the pulse level of the clock pulse is low level. At the same time, when the signal corresponding to the clock pulse is not input to its control terminal, it enters a high impedance state, and the control means inputs the drive pulse output from the drive pulse generation circuit, and the drive pulse When it is at a high level, the buffer means is provided with a signal corresponding to the clock pulse. Transmitted towards your terminal, when the driving pulse is at the low level is to cease to transmit the signal corresponding to the clock pulse to the buffer means, the semiconductor circuit device, characterized in that.