JPH0750406A - Semiconductor device with self arc-extinguishing function - Google Patents

Abstract

PURPOSE:To reduce the turn-off loss by a method wherein the thickness of the second conductivity type emitter layers is specified within specific range as well as the thickness of low resistant short-circuit regions is specified to be thicker than said emitter layers by not less than specific amount. CONSTITUTION:This semiconductor device is provided with the four layer structure successicely laminated in order of the first conductivity type emitter layers 3, the second conductivity type base layer 2, the first conductivity type base layer 1 and the second conductivity type emitter layers 4. Within the semiconductor device provided with a semiconductor base substance four layer structured having both surfaces thereof to be the second main surfaces 7, 8, plural stripped n type emitter layers 3 are separately arranged on the first main surface side 7 so as to from respective p<+> type gate contact regions 6 on the p type base layer 2 exposed between the emitter layers 3. On the other hand, p type emitter layers 4 within the thickness range of 10mum-30mum as well as low resistant n<+> type shortcircuit regions 5 thicker than the emitter layers 4 by 20mum on larger are selectively arranged on the second main surface 8. Accordingly, the turn-off loss can be notably extenuated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a self-arc-extinguishing function, and particularly when reducing turn-off loss of the semiconductor device, consideration is given to the thickness of an emitter layer and the thickness of a short-circuit region of low resistance. The present invention also relates to a semiconductor device having a self-erasing function that prevents abnormal firing characteristics.

[0002]

2. Description of the Related Art Generally, a gate turn-off thyristor (hereinafter referred to as a GTO thyristor) is known as a semiconductor device having a self-erasing function. This GTO
The thyristor is a p-type emitter layer, an n-type base layer, a p-type
-Type base layer and n-type emitter layer are sequentially stacked 4
A semiconductor substrate having a layered structure is provided. An anode electrode is connected to the p-type emitter layer, a gate electrode is connected to the p-type base layer, and a cathode electrode is connected to the n-type emitter layer. It has a structure in which a plurality of these units (units) are formed and arranged.

When manufacturing this GTO thyristor, first, an n-type base layer is used as a substrate, and an impurity is injected and diffused into this substrate to form a p-type base layer and an n-type on one surface side. Type emitter layers are sequentially formed, and a p-type emitter layer is formed on the other surface side to obtain the semiconductor substrate. Then, when forming the p-type base layer, for example, gallium is used as an impurity for implantation and diffusion, and when forming an n-type emitter layer, for example, phosphorus is used as an impurity for implantation and diffusion. To be Further, in order to simplify the impurity implantation / diffusion process, the p-type emitter layer and the p-type base layer are simultaneously formed by the impurity implantation / diffusion performed at the same time.

In such a GTO thyristor, one of its operating characteristics is turn-off loss. This turn-off loss is caused by the residual current existing in the n-type base layer at the junction between the n-type base layer and the p-type emitter layer (hereinafter referred to as J1 junction) when the GTO thyristor turns off. In order to reduce the turn-off loss, the carrier injection efficiency of carriers injected from the p-type emitter layer is suppressed so that it exists in the n-type base layer at the J1 junction. It is known that the carrier density should be reduced, and some means are also known as means for suppressing the carrier injection efficiency of carriers from the p-type emitter layer.

Here, one of the means for suppressing the injection efficiency is an anode short-circuit method in which the anode electrode and the n-type base layer are partially short-circuited by a low-resistance n-type short-circuit region. The low-resistance n-type short-circuit region is formed by implanting and diffusing a large amount of impurities such as phosphorus into a part of the p-type emitter layer and replacing the p-type emitter layer with the low-resistance n-type short-circuit region. To be formed. When the p-type emitter layer and the p-type base are simultaneously formed by implanting and diffusing an impurity when forming the n-type short-circuit region, the above-mentioned process is performed prior to the implanting and diffusing the impurity. An n-type short circuit region is formed.
Another means for suppressing the injection efficiency is to form a thin p-type emitter layer.
The type emitter layer is formed by forming various layers including a low-resistance n-type short-circuit region by implanting and diffusing impurities, and then additionally implanting and diffusing boron or the like. If such forming means is adopted, it is several μm.
It is possible to form a p-type emitter layer having a thickness of about
This suppresses the injection efficiency of carriers injected from the p-type emitter layer.

In addition, as a means for reducing the turn-off loss in the GTO thyristor, a means for controlling the lifetime of the carrier is known, and a heavy metal such as gold is included in the means for performing the lifetime control. That controls the lifetime of the carrier by diffusing it,
Alternatively, there is one that controls the lifetime of the carrier by irradiating γ-rays or electron beams, and all of these means are intended to shorten the lifetime of the carrier and accelerate the decrease of the carrier. is there. However, any of the means for controlling the lifetime of the carrier shortens the lifetime of all carriers existing inside the GTO thyristor. The carrier concentration in the n-type base layer in the vicinity of the junction with the base layer (hereinafter referred to as the J2 junction) decreases when the current is conducting, and is not much different from the carrier density on the J1 junction side. Or lower. Therefore, the turn-off loss of the GTO thyristor is reduced, but at the same time, there is a problem that the turn-on voltage is significantly increased.

In order to solve this problem, JP-A-64-9658 discloses a GTO thyristor in which heavily charged particles such as protons are implanted to locally control the carrier lifetime. . The means for controlling the carrier lifetime by implanting heavily charged particles such as protons has a significantly smaller transmittance into the GTO thyristor than that which irradiates with γ-rays or electron beams. Heavy charged particles can be stopped at a predetermined depth of the semiconductor substrate. Then, in the implantation region of heavily charged particles such as protons, many generation and recombination centers that become lifetime killer are formed, so that it becomes possible to locally control the lifetime of the carrier. The J
By selectively shortening only the carrier lifetime of the n-type base layer near one junction, turn-off loss can be reduced without increasing turn-on voltage.

[0008]

Generally, in a GTO thyristor, in order to establish high breakdown voltage characteristics, impurities are diffused at high temperature for a long time when forming a p-type base layer. For example, when gallium is selected as an impurity and the p-type base layer is formed by the implantation diffusion of gallium, the diffusion is performed for 23 hours in an oxygen atmosphere at a high temperature of 1250 ° C., and the n-type base layer is formed. The depth of the junction with (J2 junction) reaches about 60 μm from the surface of the n-type emitter layer. When the p-type emitter layer and the p-type base layer are simultaneously formed by impurity diffusion, the p-type emitter layer is also formed to a thickness of about 60 μm. By the way, when the impurities are diffused at a high temperature for a long time in such an oxygen atmosphere, the GT
Oxygen penetrates into the semiconductor substrate of the O thyristor, and an n-type diffused oxygen region reaching a depth of about 30 μm from the surface is generated. At this time, in the n-type diffused oxygen region generated on the p-type emitter layer side, the concentration of diffused oxygen is orders of magnitude lower than the carrier concentration of the p-type emitter layer, and the existence range thereof is the p-type. Since it is limited to the inside of the emitter layer, the influence of the formation of the n-type diffused oxygen region hardly appears.

However, in order to reduce the turn-off loss of the GTO thyristor, when a thin p-type emitter layer is formed, a situation different from the above case occurs. That is, p
When the thickness of the emitter layer of the mold is about several μm, n
The diffused oxygen region of the type penetrates into the inside of the n-type base layer beyond the thin p-type emitter layer to diffuse oxygen into the n-type base layer. Since the concentration of oxygen diffused in the n-type base layer is higher than the impurity concentration of the n-type base layer, the influence of the n-type diffused oxygen region cannot be ignored. Usually, in the manufacturing process of a GTO thyristor, some heat treatment steps are performed even after the impurity diffusion step is completed. However, if the heat treatment temperature at that time is around 400 ° C. Oxygen diffused in is activated and becomes a donor.
As a result, the semiconductor substrate is not merely a pnpn four-layer structure, but an insulator layer i (actually a high resistance n
A GTO thyristor having an abnormal gate trigger current, for example, a GTO thyristor with a low ignition sensitivity, or a GTO thyristor that does not ignite even if the gate trigger current is increased. Will be done. As described above, in the GTO thyristor having the thin p-type emitter layer, the carrier injection efficiency can be suppressed and the turn-off loss can be reduced, but the influence of the n-type diffused oxygen region formed inside the semiconductor substrate. Therefore, there is a problem that a GTO thyristor having an insufficient ignition state may be obtained.

On the other hand, in the case of locally controlling the carrier lifetime by implanting heavy charged particles such as protons, the depth and amount of implantation of the heavy charged particles have been considered so far. However, the profile after implanting the heavy charged particles, in particular, the relationship between the deepest part of the distribution region of the heavy charged particles and the thickness of the p-type emitter layer or the low-resistance n-type short-circuit region. Since no consideration has been given to the above, there is a problem that a sufficient function cannot always be exerted when used in combination with the formation of the low resistance n-type short-circuit region.

The present invention eliminates the above-mentioned problems, and an object thereof is to make full use of each function and reduce turn-off loss without causing an abnormality in the gate trigger current. It is to provide a semiconductor device having a self-extinguishing function.

[0012]

In order to achieve the above object, the present invention provides a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type base layer, and a second conductivity type base layer. The semiconductor substrate has a four-layer structure in which emitter layers are stacked in this order, and both sides of the four-layer structure have a first main surface and a second main surface, respectively. Type emitter layer is composed of a plurality of strip-shaped ones separated from each other, and a second conductivity type base layer is exposed between the plurality of separated first conductivity type emitter layers. On the second main surface side, the second conductivity type emitter layer and the first conductivity type base layer reach the first conductivity type base layer, and alternate with the first conductivity type short-circuit region having a lower resistance than the first conductivity type base layer. The exposed second-type emitter layer has a thickness of 10 μm.
To 30 μm, and the thickness of the short-circuit region of low resistance is 20 μm greater than the thickness of the second-conductivity-type emitter layer.
The first means having the above-described thick structure is provided.

In order to achieve the above object, according to the present invention, the thickness of the second conductive type emitter layer is the thickness of a diffusion region of oxygen generated when the first conductive type base layer is formed. The second means is provided that is ⅓ or more of the height and does not exceed the thickness.

Further, in order to achieve the above object, the present invention implants heavily charged particles from the first main surface side of the semiconductor substrate, and forms the deepest portion of the distribution region of the heavily charged particles formed by this implantation. However, the third means is provided, which is shallower than the thickness of the short circuit region of the first conductivity type and deeper than the thickness of the emitter layer of the second conductivity type.

[0015]

According to the first means, the thickness of the second conductivity type emitter layer is in the range of 10 μm to 30 μm, and the thickness of the low resistance first conductivity type short-circuit region is set. Is at least 2 than the thickness of the second conductive type emitter layer.
It is configured to be thicker than 0 μm. Therefore, the efficiency of carrier injection from the relatively thin second-conductivity-type emitter layer is effectively suppressed, and the original function of the low-resistance first-conductivity-type short-circuit region is sufficiently exerted. Therefore, the turn-off loss of the semiconductor device having the self-extinguishing function can be significantly reduced.

According to the second means, the thickness of the second conductivity type emitter layer is ⅓ of the thickness of the diffusion region of oxygen generated when the first conductivity type base layer is formed. Above,
Moreover, it is configured so as to be within a range not exceeding its thickness. Therefore, oxygen diffused into the semiconductor substrate (first conductivity type base layer) during formation of the second conductivity type base layer is
Within the range of up to several μm from the surface of the semiconductor substrate, the impurity concentration is sufficiently higher than the impurity concentration of the semiconductor substrate, and when the range exceeds about 10 μm from the surface of the semiconductor substrate, the difference from the impurity concentration of the semiconductor substrate is reached. Becomes smaller,
Even if the oxygen diffused in the semiconductor substrate is made into a donor in the semiconductor substrate by the subsequent heat treatment, the effect of the diffused oxygen that has become a donor is about 10 μm from the surface of the semiconductor substrate.
Since it is limited to the region of m or less, as a result, it is not affected by the diffused oxygen and the diffused oxygen region converted to a donor, and the firing sensitivity is lowered, or the gate trigger current is abnormal such as not firing. It is possible to remarkably reduce the turn-off loss of the semiconductor device having the self-extinguishing function without causing the above phenomenon.

Further, according to the third means, the deepest part of the heavily charged particle distribution region is shallower than the thickness of the low resistance first conductivity type short-circuit region, and the second conductivity type emitter layer. It is configured to be deeper than the thickness of. Therefore, it is possible to effectively use the generated recombination formed by the implantation of the heavy charged particles, so that the self-sensitivity can be improved without lowering the firing sensitivity or causing an abnormality in the gate trigger current such as not firing. It is possible to significantly reduce the turn-off loss of the semiconductor device having the arc extinguishing function.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing a part of the configuration of a first embodiment of a semiconductor device having a self-arc extinguishing function according to the present invention.
It shows an example of configuring a TO thyristor.

In FIG. 1, 1 is an n-type (first conductivity type) base layer, 2 is a p-type (second conductivity type) base layer, and 3 is n.
-Type emitter layer, 4 is a p-type emitter layer, 5 is a low-resistance high-concentration n-type (n + -type) short-circuit region, and 6 is a high-concentration p-type (p
(+ Type) gate contact region, 7 is the first main surface, and 8 is the second main surface.

The p-type emitter layer 4, the n-type base layer 1, the p-type base layer 2, and the n-type emitter layer 3 form a four-layered semiconductor substrate that is sequentially stacked. In this semiconductor substrate, the n-type emitter layer 3 side forms the first main surface 7, and the p-type emitter layer 4 side forms the second main surface 8. On the side of the first main surface 7, the n-type emitter layer 3 is composed of a plurality of strip-shaped ones that are separated from each other, and the exposed p-type base layer between the n-type emitter layers 3 is exposed. A p + type gate contact region 6 is formed on each of the two. On the second surface side 8, the p-type emitter layer 4 and the low-resistance n + -type short-circuit region 5 are formed.
Are formed so as to be alternately exposed, and the non-exposed portion of the n + type short-circuit region 5 penetrates into the n type base layer 1. Here, the p-type emitter layer 4 is selectively formed to have a thickness within the range of 10 μm to 30 μm, and the n + type short-circuit region 5 has a thickness smaller than that of the p-type emitter layer 4. Is also selectively formed to have a thickness of 20 μm or more. Although not shown, n
A cathode electrode is provided on the surface of the p-type emitter layer 3, an anode electrode is provided on the surfaces of the p-type emitter layer 4 and the n + type short-circuit region 5, and a gate electrode is provided on the surface of the p + type gate contact region 6. The GTO as a whole
A thyristor is constructed.

2 (a) to 2 (d) and FIG.
(A) thru | or (d) is process explanatory drawing which shows each manufacturing process which shows an example at the time of manufacturing the GTO thyristor of 1st Example. However, for convenience of explanation, in FIG. 2 and FIG.
Only the structure of one unit of the GTO thyristor is shown.

2 and 3, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The GTO thyristor of the first embodiment is generally manufactured as follows.

In the first step 1, as shown in FIG. 2A, a silicon substrate having a substantially constant impurity concentration and having a high resistance characteristic to be the n-type base layer 1 is prepared.
An appropriate amount of gallium as an impurity is implanted (deposited) into the first surface 7 side of the silicon substrate, and then gallium is diffused in an oxygen atmosphere at a temperature of 1250 ° C. for 23 hours to form the first silicon substrate. P on the surface 7 side
The base layer 2 of the mold is formed. At this time, the thickness of the p-type base layer 2 is about 60 μm.

In the subsequent step 2, as shown in FIG. 2B, an appropriate amount of phosphorus as an impurity is selectively implanted (deposited) into a plurality of locations on the second surface 8 side of the silicon substrate. An n + type short-circuit region 5 is formed at the phosphorus injection point.

Next, in step 3, as shown in FIG. 2C, an appropriate amount of phosphorus as an impurity is implanted (deposition) into the surface of the p-type base layer 2 already formed.
Then, the n-type emitter layer 3 is formed.

Next, in step 4, as shown in FIG. 2 (d), the n-type emitter layer 3 formed in step 3 is partially removed by etching, and the p-type base is added to these removed portions. Expose layer 2.

In the subsequent step 5, as shown in FIG. 3A, an appropriate amount of phosphorus as an impurity is selectively implanted (deposition) into the surface of the p-type base layer 2 exposed in the step 4. The p + type gate contact region 6 is formed by the implantation of phosphorus.

Next, in step 6, as shown in FIG. 3B, the first impurity diffusion is performed in an oxygen atmosphere at a temperature of 1200 ° C. for about 15 to 35 hours, whereby p + Not only the type gate contact region 6 but also the n-type emitter layer 3 and the n + type short-circuit region 5 are increased in thickness.

Subsequently, in step 7, as shown in FIG. 3C, an appropriate amount of boron is selectively used as an impurity in the non-arranged portion of the n + type short-circuit region 5 on the second surface 8 side of the silicon substrate. Then, a p-type emitter layer 4 is formed at the boron injection point. At this time, the thickness of the p-type emitter layer 4 is about 4 μm.

Next, in step 8, as shown in FIG. 3D, a second diffusion of each impurity is performed in an oxygen atmosphere at a temperature of 1200 ° C. for about 15 to 20 hours. Although the thicknesses of the n-type emitter layer 3, the p-type emitter layer 4, the n + type short-circuit region 5 and the p + type gate contact region 6 increase, the p-type emitter layer 4 has a thickness of about 20 μm. , N + type short-circuit region 5 has a thickness of about 45 μm.

Although the steps 1 to 8 include steps of adjusting the thickness of the silicon substrate, cleaning, oxidizing, photo-etching, etc., these steps are included for simplification of description. The description of the steps is omitted.

After the steps 1 to 8 are completed, a step of forming a protective film such as an oxide film, aluminum (Al)
An electrode forming step of forming a cathode electrode, an anode electrode, and a gate electrode, which are formed of, etc., on the surface of the n-type emitter layer 3, the surface of the p-type emitter layer 4, and the surface of the p + -type gate contact region 6, respectively. The GTO thyristor manufacturing process is completed through a pellet cutting process for cutting pellets from the wafer, a lifetime control process, a packaging process, and the like.

Next, FIG. 4 is an impurity distribution characteristic diagram showing the impurity concentration in the p-type emitter layer 4 arrangement portion on the second main surface 8 side (anode side) in the GTO thyristor of the first embodiment.

In FIG. 4, the horizontal axis represents the depth (μm) from the second main surface 8 (anode surface), and the vertical axis represents the magnitude of each impurity concentration. In this case, the depth of 0 to 20 μm from the anode surface is the formation region of the p-type emitter layer 4, and the depth of more than 20 μm from the anode surface is the formation of the n-type base layer 1. Area.

Then, as shown by the solid line in FIG.
The impurity concentration in the formation region of the p-type emitter layer 4 is
The maximum depth is 0 (surface) from the anode surface, and the depth decreases as the depth from the anode surface increases, and becomes almost 0 when the depth from the anode surface reaches 20 μm. . The impurity concentration in the formation region of the n-type base layer 1 is almost 0 at a depth of 20 μm from the anode surface and is 20 μm from the anode surface.
When it slightly exceeds m, it rapidly increases to a certain value, and
The distribution is such that the certain value is maintained even when the depth from the anode surface becomes deep.

Further, when the p-type base layer 2 is formed in the above step 1, if an impurity diffusion treatment is performed for 23 hours at a temperature of 1250 ° C. in an oxygen atmosphere, G
As described above, oxygen is diffused inside the TO thyristor, but this diffused oxygen is maximum at a depth of 0 (surface) from the anode surface, as shown by the dotted line in FIG. Therefore, the depth gradually decreases as the depth from the anode surface becomes deeper, and becomes almost 0 when the depth from the anode surface becomes 30 μm. That is,
The diffused oxygen infiltrates up to about 30 μm from the anode surface. In the first embodiment, however, the p-type emitter layer 4 has a thickness of 20 μm. J between the layer 4 and the n-type base layer 1
The diffused oxygen in the vicinity of the junction 1 does not cause an increase in the impurity concentration due to conversion to a donor.

As described above, according to the first embodiment, a GTO thyristor having a reduced turn-off loss can be obtained without causing an abnormality in the gate trigger current such as a reduction in ignition sensitivity or an ignition failure. To be

Next, FIG. 5 shows the first embodiment.
The impurity concentration of the p-type emitter layer 4 disposed portion on the second main surface 8 side (anode side) in the GTO thyristor of the second embodiment of the present invention in which the thickness of the p-type emitter layer 4 is 10 μm is shown. It is an impurity distribution characteristic diagram.

In FIG. 5, the horizontal axis represents the depth (μm) from the second main surface 8 (anode surface), and the vertical axis represents the magnitude of each impurity concentration. In the case of the second embodiment, the range from 0 to 10 μm in depth from the anode surface is the formation region of the p-type emitter layer 4, and the range from the anode surface in excess of 10 μm is: This is a formation region of the n-type base layer 1. In this case, the thickness of the p-type emitter layer 4 is set to the first
In order to form a thin film having a thickness of 10 μm, which is thinner than 20 μm in the embodiment of FIG.
The time for the impurity diffusion for the second time may be set to be shorter than about 15 to 20 hours.

Then, as shown by the solid line in FIG.
The impurity concentration in the formation region of the p-type emitter layer 4 is
The maximum depth is 0 (surface) from the anode surface, and the depth decreases sharply as the depth from the anode surface becomes deep, and becomes almost 0 when the depth from the anode surface is 10 μm. The impurity concentration in the formation region of the n-type base layer 1 is almost 0 at a depth of 10 μm from the anode surface, and when the depth from the anode surface slightly exceeds 10 μm, it rapidly increases to a certain value. However, hereinafter, the distribution is such that the above-mentioned certain value is maintained even if the depth from the anode surface becomes deep.

Further, in the second embodiment, the diffused oxygen has a maximum depth 0 (surface) from the anode surface, as shown by the solid line in FIG. The depth gradually decreases as the depth increases, and becomes almost zero when the depth from the anode surface is 30 μm.
Therefore, also in the second embodiment, the diffused oxygen penetrates up to about 30 μm from the anode surface. For this reason, the depth from the anode surface is 10 μm
At this point, a small amount of diffused oxygen that has become a donor appears in the n-type base layer 1 near the J1 junction between the p-type emitter layer 4 and the n-type base layer 1. The impurity concentration increases by the amount of the converted diffused oxygen, but since the amount of the diffused oxygen converted into the donor is not so large, it is hardly affected by the diffused oxygen converted into the donor.

As described above, according to the second embodiment, although the gate trigger current may be slightly larger than the design value, the gate trigger current may be lowered or ignition failure may occur. 1st without causing current abnormality
As in the case of the above embodiment, the GT with reduced turn-off loss
O thyristor is obtained.

Next, referring to FIG. 6, in the first embodiment, the second diffusion of impurities at a high temperature of 1200 ° C. in the step 8 is omitted, and the thickness of the p-type emitter layer 4 is set to about 10. Four
A first reference example (inappropriate example) of a GTO thyristor configured to have a thickness of μm is shown. (a) is a cross-sectional view showing a part of the configuration of the GTO thyristor, and (b) is its G
Second main surface 8 side of TO thyristor (anode side)
6 is an impurity distribution characteristic diagram showing the impurity concentration in the portion where the p-type emitter layer 4 is arranged.

In FIG. 6, reference numeral 9 is an n-type layer containing diffused oxygen that has been made into a donor, and the same components as those shown in FIG. 1 are designated by the same reference numerals.

In the first reference example, G
On the second main surface 8 side of the TO thyristor, a p-type emitter layer 4 having a thickness of 4 μm and an n + type short-circuit region 5 thicker than that are provided, and further deeper than the deepest part of the n + type short-circuit region 5. , An n-type layer 9 containing diffused oxygen is formed even inside the n-type base layer 1.

According to the GTO thyristor of the first reference example, since the thickness of the p-type emitter layer 4 is too thin as about 4 μm, as shown in FIG. A large amount of diffused oxygen that has become a donor is generated in the n-type base layer 1 in the vicinity of, and the amount of the diffused oxygen that has become a donor is not negligible as compared with the impurity concentration in the n-type base layer 1. In such a state, as shown in FIG. 6A, the n layer 21 formed by the diffused oxygen that has become a donor is formed of the p-type emitter layer 4 (and the n + -type short-circuit region 5) and the n-type base layer 1. 5 formed between and consisting essentially of pnipn
It has a layered structure.

Therefore, in the GTO thyristor of the first reference example, not only the gate trigger current becomes extremely large,
The ignition sensitivity is significantly reduced, and further ignition failure occurs.

Here, FIG. 7 is a characteristic diagram showing an example of the correlation between the thickness of the p-type emitter layer 4 and the gate trigger current and turn-off loss in the GTO thyristor.

In FIG. 7, the horizontal axis represents the p-type emitter layer 4
(Μm), and the vertical axis represents the gate trigger current and turn-off loss. The gate trigger current has a design value of 1 with respect to the thickness of each p-type emitter layer 4, and the turn-off loss is intended for those having the same on-voltage.

According to the characteristic diagram shown in FIG. 7, regarding the gate trigger current, the thickness of the p-type emitter layer 4 is 30.
When the thickness is equal to or larger than μm, the diffusion depth of oxygen diffused when the p-type base layer 2 is formed is about 30 μm, so that the influence of the diffused oxygen is not exerted and the design value is matched. . Next, if the thickness of the p-type emitter layer 4 is made thinner than 30 μm, the gate trigger current is not affected by the design value because it is not affected by the diffused oxygen as in the above case during the initial period. However, when the thickness of the layer 4 becomes about 20 μm or less, the layer 4 is gradually affected by the diffused oxygen, and the gate trigger current gradually becomes larger than the designed value. Then, when the thickness of the p-type emitter 4 is reduced to about 10 μm or less, it is directly affected by the diffused oxygen, and the gate trigger current becomes extremely larger than the designed value.

On the other hand, the turn-off loss is maintained at a relatively small value when the thickness of the p-type emitter layer 4 is small, because the carrier injection efficiency from the p-type emitter layer 4 is suppressed. However, as the thickness of the p-type emitter layer 4 increases, the effect of suppressing the carrier injection efficiency gradually weakens as the thickness increases, so the turn-off loss gradually increases and is relatively large from a certain point. It will increase. The branch point where the increase gradient of the turn-off loss becomes large is near the thickness of the p-type emitter layer 4 of about 30 μm.

In summary, with respect to the gate trigger current, the preferable range is the thickness of the p-type emitter layer 4 of about 10 μm or more, and the preferable range of the turn-off loss is the p-type emitter layer 4. Is about 30 μm or less, and a preferable range for both the gate trigger current and the turn-off loss is within the range of 10 μm to 30 μm for the p-type emitter layer 4. Therefore, in the present invention, The thickness of the p-type emitter layer 4 is selectively configured so as to be in the range of 10 μm to 30 μm.

Further, in the present invention, the reason why the thickness of the p-type emitter layer 4 is selected to be in the range of 10 μm to 30 μm is due to the following reasons in addition to the above reasons.

As will be described later, when the n + type short-circuit region 5 is formed, its thickness is preferably at least 20 μm or more than the thickness of the p type emitter layer 4. Therefore, if the thickness of the p-type emitter layer 4 is to be 30 μm or more, the thickness of the n + type short-circuit region 5 must be 50 μm or more. However, it cannot be formed by a normal manufacturing process, and a special process must be used. Therefore, the thickness of the n + type short-circuit region 5 is set to 50
Even if a GTO thyristor with a size of μm or more is manufactured,
Since the manufacturing cost will increase, it is not realistic to set the thickness of the n + type short-circuit region 5 to 50 μm or more,
The thickness of the p-type emitter layer 4 is preferably kept within the range of 10 μm to 30 μm.

By the way, the thickness of the p-type emitter layer 4 is 10
μm corresponds to approximately 1/3 of the thickness of the oxygen diffusion region generated when the p-type base layer 2 is formed, and the thickness 30 μm of the p-type emitter layer 4 is the thickness of the oxygen diffusion region. If a GTO thyristor is manufactured under heat treatment conditions different from those used in the first embodiment, the thickness of the p-type emitter layer 4 is The thickness of the p-type emitter layer 4 is set to be 10 μm to 30 μm instead of defining the thickness.
It may be prescribed that the thickness is within about 1/3 of the thickness of the oxygen diffusion region generated when the p-type base layer 2 is formed and does not exceed the thickness of the oxygen diffusion region. .

Next, FIG. 8 shows a third embodiment of the GTO thyristor according to the present invention in which the thickness of the p-type emitter layer 4 is set to 10 μm, and (a) is a partial cross sectional view thereof. FIG. 6B is an impurity distribution characteristic diagram showing the impurity concentration including the generated recombination on the second main surface 8 side (anode side), and the horizontal axis is the depth from the second main surface 8 (anode surface). Sa (μ
m), and the vertical axis represents each impurity concentration and the size of generated recombination. Note that, in FIG. 8B, illustration of diffused oxygen is omitted for simplification of description.

In FIG. 8, reference numeral 10 denotes a region where protons that have become donors exist (low resistance region), and the same components as those shown in FIG. 1 are denoted by the same reference numerals.

Then, as shown in FIG. 8B, in the third embodiment, the depth from the anode surface is 0 μm (surface).
The range from 10 μm to 10 μm is the formation region of the p-type emitter layer 4, and the range where the depth from the anode surface exceeds 10 μm is the formation region of the n-type base layer 1. Also in this case,
Since the p-type emitter layer 4 is formed to have a thickness of 10 μm,
The time of the second impurity diffusion at the high temperature of 1200 ° C. in the step 8 is set to be shorter than about 15 to 20 hours.

According to the GTO thyristor according to the third embodiment, as shown by the solid line in FIG. 8B, the impurity concentration in the formation region of the p-type emitter layer 4 is the depth from the anode surface. The maximum is at 0 μm (surface), and it rapidly decreases as the depth from the anode surface becomes deep, and becomes almost 0 at the depth from the anode surface of 10 μm. Further, as shown by the solid line in FIG. 8B, the impurity concentration in the formation region of the n-type base layer 1 is almost zero at a depth of 10 μm from the anode surface.
However, when the depth from the anode surface slightly exceeds 10 μm, it rapidly increases to a certain value, and thereafter, the distribution is such that the above value is maintained even if the depth from the anode surface becomes deep. ing. On the other hand, as shown by the dotted line in FIG. 8B, the impurity concentration in the n + type short-circuit region 5 is maximum at a depth of 0 μm (surface) from the anode surface, and the depth from the anode surface is large. Gradually decreases with increasing depth, and becomes almost zero at a depth of 45 μm from the anode surface.

In this case, the recombination generated by the implantation of protons is relatively small at the depth of 0 μm (surface) from the anode surface, as shown by the solid line in FIG. The depth from the anode surface increases gradually as the depth from the anode surface increases.
It becomes maximum at the μm (generation recombination center), and sharply decreases as the depth from the anode surface exceeds 25 μm, and becomes almost 0 at the depth from the anode surface of 40 μm.
It will be. In order to obtain the characteristics shown in FIG. 8B, in the third embodiment, the proton implantation amount is set to 1 × 10 ¹² / cm ² , and the heat treatment is performed at a temperature of 350 ° C. for 3 hours after the proton implantation. And the center of the depth of proton implantation (generation recombination center) is 25 μm.
It was made to become.

As described above, in the GTO thyristor according to the third embodiment, the center of the depth of proton implantation (generation recombination center) is 15 μm deeper than the J1 junction inside the n-type base layer 1. As shown in FIG. 8B, the increment of the generated recombination density in the vicinity of the J1 junction and before and after the J1 junction, that is, in the range of the depth from the anode surface of 0 μm (surface) to about 20 μm is: The number of generated recombination densities is extremely low and almost constant. In the region where the generated recombination density is almost constant, the diffused oxygen does not become a donor, so that the GTO thyristor according to the third embodiment has a depth from the anode surface of 0 μm to about 20 μm.
Diffused oxygen that has become a donor does not occur within the range of
Therefore, the abnormality of the gate trigger current did not occur.

Further, in the GTO thyristor according to the third embodiment, the thickness of the n + type short-circuit region 5 is 45 μm, and the deepest part thereof is about 35 μm deeper than the J1 junction part, so that it is formed by proton implantation. The generated recombination centers thus generated remain completely within the thickness of the n + type short-circuit region 5. Then, as shown in FIG. 8A, the generated recombination centers obtained by the implantation of the protons are turned into donors by the subsequent heat treatment to become the low resistance regions 10. The low resistance regions 10 turned into donors are separated. Since the n + type short-circuit regions 5 arranged are connected to each other with low resistance, the original function of the n + type short-circuit regions 5 is increased. Therefore, in the GTO thyristor according to the third embodiment, the turn-off loss can be remarkably reduced as compared with the GTO thyristor in which the proton is not implanted even if the gate trigger current may be slightly increased.

Next, referring to FIG. 9, in the first embodiment,
The first diffusion of impurities at a high temperature of 1200 ° C. in step 6 is omitted, the thickness of the p-type emitter layer 4 is about 10 μm, and the thickness of the n + -type short-circuit region 5 is about 20 μm.
A second reference example (inappropriate example) of a GTO thyristor configured to have a length of m is shown. (a) is a cross-sectional view showing a part of the configuration of the GTO thyristor, (b) is its GT
It is an impurity distribution characteristic view which shows the impurity concentration of the 2nd main surface 8 side (anode side) in an O thyristor.

In FIG. 9, the same components as those shown in FIG. 8A are designated by the same reference numerals.

Then, as shown in FIG. 9B, in the second reference example, the depth from the anode surface was 0 μm (surface).
The range from 10 μm to 10 μm is the formation region of the p-type emitter layer 4, and the range where the depth from the anode surface exceeds 10 μm is the formation region of the n-type base layer 1.

According to the GTO thyristor according to the second reference example, as shown by the solid line in FIG.
The impurity concentration in the formation region of the emitter layer 4 of the mold is maximum at a depth of 0 μm (surface) from the anode surface, and sharply decreases as the depth from the anode surface becomes deeper. Becomes almost 0 at a depth of 10 μm. Further, as shown by the solid line in FIG. 9B, the impurity concentration in the formation region of the n-type base layer 1 is almost zero at a depth of 10 μm from the anode surface.
However, when the depth from the anode surface slightly exceeds 10 μm, it rapidly increases to a certain value, and thereafter, the distribution is such that the above value is maintained even if the depth from the anode surface becomes deep. ing. Further, as shown by the dotted line in FIG. 9B, the impurity concentration in the n + type short circuit region 5 is
The depth from the anode surface is maximum at 0 μm (surface), and gradually decreases as the depth from the anode surface becomes deeper, and becomes almost 0 at the depth from the anode surface at about 20 μm. There is. At this time, when the proton implantation was performed on the second reference example under the same conditions as in the third embodiment, as shown by the solid line in FIG. 9B, the generation caused by the proton implantation occurred. The recombination center was located at a depth of about 25 μm from the anode surface, and the recombination center generated was beyond the thickness range of the n + type short-circuit region 5.

The GTO thyristor of this second reference example is
Although the thickness of the p-type emitter layer 4 satisfies the minimum allowable range of 10 μm, the thickness of the n + type short-circuit region 5 does not meet the requirement of 20 μm than the thickness of the p-type emitter layer 4, As shown in FIG. 9A, the low resistance region 1 which has been made into a donor by the heat treatment after the proton implantation.
0 exists in a portion deeper than the n + type short-circuit region 5. Therefore, the low resistance region 10 that has become a donor is
It does not function to connect the n + type short-circuit regions 5 that are separately arranged with low resistance, and does not increase the original function of the n + type short-circuit regions 5. Although the GTO thyristor of the second reference example does not increase the gate trigger current, it cannot reduce the turn-off loss remarkably as in the third embodiment, and the GTO thyristor is the same as the reference example. It remains.

Continuing with FIG. 10, the p-type emitter layer 4 has a thickness of about 10 μm, and the n + type short-circuit region 5 has a thickness of about 20 μm. GT smaller than that of the second reference example
The 3rd reference example (inappropriate example) of an O thyristor is shown, (a) is a transverse cross-sectional view showing a part of the structure of the GTO thyristor, (b) is the second of the GTO thyristor.
It is an impurity distribution characteristic view which shows the impurity concentration of the main surface 8 side (anode side).

In FIG. 10, the same components as those shown in FIG. 9A are designated by the same reference numerals.

In the third reference example, the energy of proton implantation is made smaller than that of the second reference example, and the generated recombination center (center of implantation depth) is deeper than the anode surface. Is about 12 μm so that the generated recombination center is located at a position shallower than the thickness of the n + type short-circuit region 5. In this case, in the third reference example, the generated recombination center exists at a position shallower than the thickness of the n + type short-circuit region 5, as in the third embodiment.
Since the thickness of the emitter layer 4 of the mold is 10 μm, the generated recombination center exists up to the vicinity of the J1 junction. Therefore, in the GTO thyristor according to the third reference example, the heat treatment after the implantation of protons causes the diffusion of oxygen to the vicinity of the J1 junction into a donor, as shown in FIG. Similar to the example, there was an abnormality in the gate trigger current such that the gate trigger current increased abnormally, the firing sensitivity was lowered, or in some cases, no firing was performed at all. Furthermore, the GTO thyristor according to the third reference example has a much lower turn-off loss than the known one in which the lifetime control is not performed by proton implantation and the lifetime control is performed by γ-ray or electron beam irradiation. However, this GTO thyristor is also a reference example.

Here, FIG. 11 is a characteristic diagram showing the relationship between the turn-on voltage and the turn-off loss of the GTO thyristor.

In FIG. 11, the horizontal axis represents the turn-on voltage,
The vertical axis represents the turn-off loss, and the depth of the proton implantation and the thickness of the n + type short-circuit region 5 are used as parameters. The curves do not perform local lifetime control by the proton implantation and A known GTO thyristor subjected to lifetime control by electron beam irradiation, a curved line of the GTO thyristor according to the third reference example, a curved line of the GTO thyristor according to the second reference example, and a curved line of the third embodiment. By GTO thyristor.

According to FIG. 11, as shown by the curves, the third recombination center is located at a position deeper than the J1 junction and shallower than the thickness of the n + type short-circuit region 5. The turn-off loss in the example GTO thyristor is, as shown in the curve, compared to the turn-off loss exhibited by a known GTO thyristor in which lifetime control is not performed by proton implantation, but lifetime control is performed by γ-ray or electron beam irradiation. It can be seen that a remarkable reduction effect can be obtained. On the other hand, as shown by the curve, the position of the generated recombination center is the n + type short-circuit region 5
The GTO thyristor of the second reference example in a position deeper than the thickness of the n + -type short-circuit region 5 as shown in the curve, but J1 The GTO thyristor of the third reference example in which the junction and the generated recombination center are not sufficiently separated from each other has the effect of reducing the turn-off loss as compared with the known GTO thyristor shown in the curve, but the third shown in the curve. Compared to the GTO thyristor of the above embodiment, the effect of reducing the turn-off loss is smaller.

From the above results, when local lifetime control is performed by implanting heavily charged particles such as protons, the generated recombination center is at a position considerably deeper than the J1 junction, and the n + type It can be seen that a GTO thyristor capable of significantly reducing turn-off loss can be obtained at a position shallower than the thickness of the short circuit region 5 without causing an abnormality in the gate trigger current. In order to obtain the GTO thyristor, the n + type short-circuit region 5
Is at least 20 times greater than the thickness of the p-type emitter layer.
It must be thicker than μm.

In the above description, it is assumed that the thicknesses of the p-type emitter layer 4 and the n + type short-circuit region 5 are accurately known in advance, and that the proton implantation depth does not vary. It is a thing. By the way, when actually manufacturing a GTO thyristor, the p-type emitter layer 4
Regarding the thicknesses of the n + type short-circuit region 5 and the n + type short-circuit region 5, it is sufficient to set the minimum difference in thickness between the J1 junction and the n + type short-circuit region 5 in the process design stage. However, with respect to the proton implantation depth, the implantation depth varies by approximately ± 5 μm with respect to the design value due to variations in the implantation energy and the thickness of the electrode layer on the substrate surface. In consideration of the variation in the depth of the p-type emitter layer 4, the design value of the proton implantation depth may be deeper than the thickness of the p-type emitter layer 4 by at least 20 μm or more.

Although the n + type short-circuit regions 5 are deposited (deposited) before the n type emitter layer 4 in each of the embodiments and the reference examples, the order is reversed. Or may be simultaneous.

Further, in each of the above-described embodiments, the GTO thyristor has been described as an example of the semiconductor device having the self-arc extinguishing function, but in the present invention, the semiconductor device having the self-arc extinguishing function is limited to the GTO thyristor. It is needless to say that the present invention can be similarly applied to other semiconductor devices having a similar self-extinguishing function.

[0080]

As described above, according to the present invention, the thickness of the second-conductivity-type (p-type) emitter layer 4 is set within the range of 10 μm to 30 μm, and the resistance is low. Since the thickness of the first conductivity type (n-type) short-circuit region 5 is set to be at least 20 μm or more than the thickness of the second conductivity type emitter layer 4, the second region is formed to be relatively thin.
The efficiency of carrier injection from the conductive-type emitter layer 4 is effectively suppressed, and the original function of the low-resistance first conductive-type short-circuit region 5 can be sufficiently exerted, so that the self-extinguishing function can be achieved. There is an effect that the turn-off loss of the semiconductor device included can be significantly reduced.

Further, according to the present invention, the distribution region of the heavy charged particles (protons) is a low resistance first conductivity type short-circuit region 5.
Is shallower than the thickness of the second conductivity type and deeper than the thickness of the second-conductivity-type emitter layer 4, so that recombination generated by implantation of heavy charged particles can be effectively used. It is possible to significantly reduce the turn-off loss of a semiconductor device having a self-extinguishing function without causing an abnormality in the gate trigger current such as a decrease in ignition sensitivity or no ignition. effective.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a part of the configuration of a first embodiment of a semiconductor device (GTO thyristor) having a self-extinguishing function according to the present invention.

FIG. 2 is a process explanatory view showing a first half process in each manufacturing process showing an example in the case of manufacturing the GTO thyristor shown in FIG. 1.

3A to 3D are process explanatory views showing a latter half of the respective manufacturing processes showing an example of manufacturing the GTO thyristor shown in FIG.

4 is a second diagram of the GTO thyristor shown in FIG.
It is an impurity distribution characteristic view which shows the impurity concentration of the p-type emitter layer arrangement | positioning part on the main surface side.

FIG. 5 is an impurity distribution characteristic diagram showing the impurity concentration in the p-type emitter layer arrangement portion on the second main surface side in the second embodiment of the GTO thyristor according to the present invention.

6A and 6B are a configuration diagram and a characteristic diagram showing a first reference example of a GTO thyristor configured such that a p-type emitter layer has a thickness of about 4 μm.

FIG. 7 is a characteristic diagram showing an example of the correlation between the thickness of the p-type emitter layer and the gate trigger current and turn-off loss in the GTO thyristor.

8A and 8B are a configuration diagram and a characteristic diagram showing a third embodiment of the GTO thyristor according to the present invention configured so that the p-type emitter layer 4 has a thickness of 10 μm.

FIG. 9 shows a p-type emitter layer 4 having a thickness of 10 μm and n +
It is a block diagram and a characteristic view showing the 2nd reference example of the GTO thyristor constituted so that the thickness of short circuit field 5 of a type may be set to 20 micrometers.

10A and 10B are a configuration diagram and a characteristic diagram showing a third reference example of the GTO thyristor in which the proton implantation energy is reduced in the second reference example shown in FIG.

FIG. 11 is a characteristic diagram showing a relationship between a turn-on voltage and a turn-off loss of a GTO thyristor.

[Explanation of symbols]

 1 n-type (first conductivity type) base layer 2 p-type (second conductivity type) base layer 3 n-type emitter layer 4 p-type emitter layer 5 low resistance high-concentration n-type (n + type) short circuit Region 6 High-concentration p-type (p + -type) gate contact region 7 First main surface 8 Second main surface 9 N-type layer containing diffused oxygen as donor 10 Region where protons as donor are present (low resistance region)

Claims (3)

[Claims] 1. A four-layer structure in which a first-conductivity-type emitter layer, a second-conductivity-type base layer, a first-conductivity-type base layer, and a second-conductivity-type emitter layer are stacked in this order. The layer structure is provided with a semiconductor substrate having both first and second main surfaces, and the first main surface side of the semiconductor substrate is a plurality of strip-shaped semiconductor layers in which first conductivity type emitter layers are separated from each other. A second conductive type base layer is exposed and formed between the plurality of separated first conductive type emitter layers, and the second main surface side of the semiconductor substrate has a second conductive type emitter layer. , The first conductivity type base layer is reached, and the first conductivity type short-circuit regions having a lower resistance than the first conductivity type base layer are alternately exposed and formed, and the thickness of the second conductivity type emitter layer is 10 μm.
To 30 μm, and the thickness of the short-circuit region of low resistance is 20 μm greater than the thickness of the second-conductivity-type emitter layer.
A semiconductor device having a self-erasing function, characterized in that it is configured to have a greater thickness. 2. The semiconductor device having a self-erase function according to claim 1, wherein the thickness of the second conductivity type emitter layer is:
A semiconductor having a self-erasing function, which is not less than ⅓ of the thickness of a diffusion region of oxygen generated when the first conductivity type base layer is formed, and is within a range not exceeding the thickness. apparatus. 3. The semiconductor device having a self-erasing function according to claim 1, wherein heavily charged particles are implanted from the first main surface side of the semiconductor substrate, and the heavily charged particles formed by this implantation are formed. A semiconductor having a self-erasing function, characterized in that the deepest part of the distribution region of the particles is shallower than the thickness of the short circuit region of the first conductivity type and deeper than the thickness of the emitter layer of the second conductivity type. apparatus.