JPH07501636A - liquid crystal display device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] liquid crystal display device Technical field The present invention solves vertical "crosstalk" in dot matrix liquid crystal display devices. It is concerned with the realization of gradation by reduction and pulse height modulation.

More specifically, the present invention provides for surfaces that are held at a defined spacing and facing each other. A liquid crystal material placed between two supporting plates and N row electrodes provided on one surface. pattern and a pattern of column electrodes provided on the other surface, and the row electrodes are In a display device in which a matrix is formed that intersects column electrodes and uses the intersections as display elements. related. This display device further includes a control circuit that applies data signals to the column electrodes, and a control circuit that applies data signals to the column electrodes. Consists of a row scanning circuit that periodically scans the electrodes and applies an appropriate row selection voltage. .

Background technology The above-mentioned display devices are well known and usually have multiple addresses in so-called RMS mode. It operates in a specified manner.

Regarding the addressing method (based on the so-called RMS behavior of liquid crystal materials), see All and If! by PleshkO! EE Trans, published papers (El, Dev , HD 21. 1974 edition, pp. 146-155), Neahing and Kme Paper published in IEEE Trans by tz (El, Dev, ED2 6. 1979 edition, pp. 795-802) and 5ID-IEI! by Youdo et al. Explained in the paper published in the biennial display conference report of H. (1976 edition, pages 50-52) has been done. This addressing method uses a matrix of display elements that correspond to pixels. It is widely used as an addressing method in the above-mentioned liquid crystal display device configured as It is used. In the devices described above, active electronic switches (e.g. thin film transistors) ) is not provided in each display element.

In the above addressing method, the display element corresponding to the pixel also has the magnitude of Vs. A row scanning circuit that periodically scans the row electrodes with one row selection pulse, and a row scanning circuit that periodically scans the row electrodes with a row selection pulse, and a second state that is optically different from the first state by a control circuit for applying the can be switched to The control circuit provides a voltage of ±Vd in magnitude while the row electrodes are being scanned. By supplying a motor voltage to the column electrodes, the optical state of the display element can be changed by It is set based on the root mean square (RMS) voltage value. .

The RMS voltage value V2 of the selected display element, that is, the display element in the on state, is calculated by the following formula: I can't stand it.

V22 = (Vs+Vd)2 /N+(N-1)XVd2 /N (1) Not selected The RMS voltage value v1 of the display element, that is, the display element in the off state, can be calculated using the following formula. It will be done.

V12 = (Vs-Vd)2 /N+(N-1)XVd2 /N (2) Figure 2 shows , illustrates the transmittance versus voltage characteristics of an image cell belonging to the above display device.

Alt and Pleshko are calculated for a given value of the ratio S = V2/Vl (transmittance vs. voltage The relationship showing the maximum number of rows Nmax for the characteristic (also called the threshold slope value) is calculated. Ta. Here, the maximum number of lines is the same as above while maintaining the preset contrast. It is the number of rows that can be addressed by the method, and the voltage Vs of the row selection pulse and the data The number of rows is determined by the voltage Vd.

These relationships are shown below.

Nmax=((S2+1)/(52-1)l 2(3)(Vs/Vd)2 = Nmax (4) vd2 = V12 X [0,5/(1-Q) + (5) Here, Q2 is equal to Nmax-1.

Set the row selection voltage Vs and data voltage Vd according to the above formulas (2) and (3), When the number of rows is Nmax, the RMS voltage between the selected display elements is equal to ■2, The RMS voltage between non-selected display elements will be equal to Vl.

As the degree of multiplexing increases, that is, as the value of Nt+ax increases, the transmission The slope of the rate vs. voltage characteristic becomes steep, that is, the value of 5=V2/Vl approaches 1.0. Ku.

N max can be set to a very large value. The threshold slope S of the transmittance vs. voltage characteristic is set to 1. ．． This is because it can be set to a value very close to 0.

FIG. 1 shows a part of a matrix display device l equipped with an NIIax selection line (stroke force) 2. and illustrates the operating principle of the RMS multiple addressing method described above. addressing The method is usually referred to as ``simultaneous-row J RMS multiple addressing''. .

Information to be displayed is placed on data lines (column electrodes) 3. The display element 4 is a selection line 2 and data line 3. The information on data line 3 causes the display element to 4 is either on or off. A row or row electrode is selected by the row selection voltage Vs. At the same time, image information (data voltage Vd above) is supplied. In this way, [1 time During the t1 period (also called the waiting time) from , line 2a is selected. This line's electricity voltage and the information on data lines 3a, 3b and 3c (i.e. ±Vd) Determine the optical states of 4aa, 4bb and 4cc.

Line 2a is selected [During one period, display elements comparable to row electrodes 2b, 20, etc. A voltage Vd is applied between all display elements.

Line 2a is selected during the t1 period from (2 time (t2-tl=tl). The information on the tangent line 3 (i.e. ±Vd) is displayed on the display elements 4aa, 4bb and 4cc. Determine the state.

After the waiting time tl has elapsed, the next line is selected. In this way, the entire image is displayed line by line. One is written. Once the line corresponding to the last row of the matrix is selected, cycle The entire file is repeated (so-called "repeated scanning procedure"). single write cycle The frame period is called the rask time or frame time. rask time or frame Time is expressed as tf:tf=NXtl. Here, N is scanned continuously Indicates the number of lines.

In the above RMS addressing method, the rise time and fall time of the optical action The transition time (or state transition time between on and off states) is the It is significant that it is much longer than time. Under these conditions, the display element is exposed to a large number of It responds to the cumulative effect of address pulses (or selection pulses). In this case, the liquid In particular, the crystal display element has an on-voltage v2 and an off-voltage determined by equations (1) and (2). by a sinusoidal or square wave signal exhibiting an RMS voltage value equal to the voltage v1. It exhibits similar response characteristics as when addressed.

As already discussed, the maximum number of selected rows Na+ax is determined by the value of the ratio V2/Vl (threshold slope value).

I have described a recent new addressing method, which is similar to the ``simultaneous row address In contrast to the reply specification method, row electrodes are selected in a "simultaneous multi-row" method during the rask time. It is.

For information on this multi-line addressing method, please refer to the following document:

! , Dutch patent application No. 9200606 in the name of Welzen, 2, 5chef rsID-IEI by fer and Cl1fton! E-Display Conference Newsletter (Bost) (USA), May 1992 edition, pp. 228-231), and 3. Bulletin of the rsID-IEEE Display Conference by Ihara et al. (Boston (USA), 1 May 1992 edition, pp. 232-235) using the above multi-line addressing method. to reduce or eliminate so-called "frame response" operations. The above [Frame] The behavior characteristics of "system response" are particularly important when the degree of multiplexing is high (the number of multiplexed rows is large). ), a fast-switching liquid crystal display employing standard simultaneous-row addressing. It occurs. "frame response" behavior causes loss of contrast and brightness. Become.

According to multi-row addressing method, multiple rows are selected simultaneously while scanning the matrix . Therefore, the number of units required to perform simultaneous row addressing for each row at each rask time is One highly selective pulse is divided into multiple smaller pulses distributed regularly during the rask time. Replaced.

Multiple selection pulses with short pulse widths are generated, and the selection pulse in multi-line addressing is The r-frame response behavior is reduced both because of the lower voltage levels on the Or be removed. On the other hand, RMS operation is reliably expressed optically.

By appropriately selecting the voltage form (and amplitude) of the selection voltage and data wave signal, Therefore, even if you perform multi-line addressing, the maximum number of lines that can be addressed will decrease. is not connected. For a given transmittance versus voltage characteristic with slope V2/Vl, Nma x is set based on Equation (3) regarding RMS operation.

Simultaneous - All display elements are on for both row and multi-row addressing. The actual RMS voltage for the on element (i.e., the selected display element) on the column in the state The pressure value is determined for a selected display element on a column in which the display elements alternately turn on and off, for example. It is different from the RMS voltage value.

This difference means that the supplied address voltage signals (especially the data signals) are more or less Resistive action and capacitive action caused by applying voltage to the display element of interest in a "deformed" state Due to the action.

This "deformation" causes a decrease in the RMS voltage value, and the RMS voltage value between the display elements. A decrease in the number of on-off state transitions (including off-on state transitions) occurring on the column increases. It is obvious that it will get bigger as time goes on.

(The transmittance is low in non-selected elements, that is, off elements, and the transmittance is low in selected elements, that is, on elements. In the case of so-called negative contrast display devices (characterized by high As shown in Figure 2, the image content differs (on-off) depending on the above factors. This results in significant brightness differences between on-devices on a column (with different number of state transitions). .

This difference in brightness (usually called the "crosstalk" phenomenon and the "ghost" phenomenon) ) is particularly noticeable in dot matrix liquid crystal display devices with high multiplicity. .

Crosstalk due to differences in data voltage patterns (so-called vertical crosstalk) A method for reducing the May 990 edition, pages 412-415, author (Kaneka et al.) .

This is a method that utilizes a spatial polarity reversal sequence. This spatial polarity reversal sea According to Kens, the address voltage signal increases every time two rows are scanned during rask scanning. Reverse gender. The starting point of polarity reversal changes or moves every frame. let

Disclosure of invention The purpose of the invention described in this patent application is to Another object of the present invention is to provide a display device that can suppress the above-mentioned crosstalk effect to the maximum extent possible. .

In order to achieve the above object, the display device according to the present invention is characterized by a column control circuit. data voltages with different amplitudes can be applied to separate column electrodes using This is possible. Different data signals have different on-off state transition times in the column of interest. selected according to the number.

The control circuit registers the number of on-off state transitions for each column of the display device matrix. It consists of a counter section.

By modifying (increasing) the amplitude of the data voltage during rask scanning, The loss of RMS voltage value of a specific display element due to the increase in the number of on-off state transitions in (increase in) loss can be compensated for.

Instead of modifying the data voltage during the rask scan, for example, for a certain period of time (e.g. , a time comparable to the waiting time t1), each time frame scanning ends, the Simultaneously send voltage pulses whose amplitudes depend on the number of on-off state transitions to separate columns. The above compensation can also be achieved by applying . These voltage pulses and on The application of different data voltages as described above is applied to driver ICs used in multi-row addressing. executed by

Brief description of the drawing FIG. 2 shows the transmission characteristics of a so-called negative contrast display device.

FIG. 3 shows the relationship between the voltage VLC between the LC elements and the elapsed time.

48 and 4B show the waveforms of the voltage across element A and the voltage across element B, respectively.

BEST MODE FOR CARRYING OUT THE INVENTION The present invention, which can reduce crosstalk effects, will be described in detail below.

The explanation will proceed in view of the simultaneous row addressing method. However, the present invention uses the simultaneous-row addressing method. but not limited to. Those with some knowledge of the art will appreciate that the present invention It is clear that it can also be used in response methods.

Figure 3 shows that the voltage Vlc across the LC element (shown as capacitor C) is It shows the increase over time until the voltage is raised to Vin voltage due to the current. ■Time dependence of IC is shown by the following formula.

V1c=VinX (1-exp(-t/r)) (6) Here, τ is the RC time It is a constant.

The RMS voltage value is calculated as follows.

VRMS2 = (Win2 / T) C (1-exp (-t / r)) 2d t (7) Through mathematical processing, the RMS voltage value (value normalized to Win ) is as follows:

VRMS2=　l-r　/2TX　CexpC-2T/　r　)-1)+2r/ Tx (exp(-T/r)-1) (8) (values etc. on actual display device) ) The actual values of τ and T are considered to be values that satisfy the relationship τ/T<<1.

By this, transforming formula (8), we get VRMS2=1/Tx (T-3r/2) (9) Wavelengths T1, T2. ,,,,T A square wave voltage sequence of square waves where n represents the relationship Tl+T2+, , Tn=TT. Taking into account the cost, the VRMS can be calculated by the following formula:

VRMS2 = (72 in TI-3) TT+ (T2-3τ/2) TT+, .

+(Tn-3r/2)/TT=1-nX3r/2TT(10 ) As mentioned above, the effective (RMS) voltage is the number of pulses of the square wave voltage, i.e. the real In some cases, it is set based on the number of times it passes through zero.

For example, if two selection elements A and B on columns i and j of a dot matrix display device Considering this, the elements in column i repeatedly turn on and off. Between elements A during rask time The voltages are reproduced in Figure 4A.

FIG. 4B shows the device assuming that the on-off state transition occurs only once on column j. Indicates the voltage between B.

The transformation of the square wave voltage (as a result of the RC operation described on page 8) is shown in Figures 4A and 4B. are reproduced in both. The VRMS of device A is equal to the RMS voltage corresponding to device B. It is clearly seen that the difference is small.

The decrease in VRMS is due to the relationship between Alt and Pleshko's theory (ideal deformation). If the data voltage signal has a larger amplitude than the one described in compensated by using pressure.

For columns i and j, different levels of data voltages must be used.

To compensate for the loss of VRMS voltage (make the VRMS voltages of elements A and B equal) , an arbitrarily selected column k in which on-off state transitions occur an arbitrary number of times. In order to equalize the VRMS voltages of the elements Whether or not it should be increased is determined based on the degree of deformation of the square wave voltage.

The high level of the data voltage to compensate for VRMS losses is Measuring the transmittance (or brightness) of an on-element as a function of the number of transitions determined experimentally. The procedure in this case is as follows.

1. Determine the transmittance of the on-element on the column where the selected display element is present.

This transmittance value is used as a reference value.

2. According to the function of the number of on-off state transitions, the basis of the on-element described in the first item is Determine the data voltage level required to obtain quasi-transmission.

In this way, the relationship Vd=Vd(Xau) is experimentally established (here , Xau = number of on-off state transitions).

Basically, this compensation method needs to handle a large number of data voltage levels. this Therefore, a multi-level TPT column driver is used.

In reality, the number of voltage levels required may be much smaller. For example, from Xau to (X Even if the same value Vd is used for the state transition up to au+1), the There is no visible difference in brightness.

Defining the range of on-off state transition makes it easier to implement the above compensation method. sand That is, the range from Xau to (Xau 10n) is defined.

Here, n takes the value of ■, 2.31.6. Makes a discernible difference in brightness If there is no such factor, the voltage Vd can be set to the same value.

In the above compensation method, during rask scanning, different Vd for different Xau values for each column Set the voltage value.

Set Vd to the same value while scanning an N row matrix for columns with different Xau values. Then, frame scanning is performed during a certain time tx (e.g., a time equal to the waiting time [l)]. Each time, a voltage pulse whose amplitude Vj (Xau) differs depending on the Xau value of the column of interest is generated. By simultaneously applying voltages to separate columns j, an on-off state transition can be achieved. VRMS loss can be compensated for. During this time tx, the same voltage, e.g. (Fig. In the addressing mode shown in Figure 1, the unselected row voltage (equal to zero) is applied to all rows. added. The pulse height of the supplied voltage pulse Vj (Xau) is as explained at the beginning. Following a similar procedure for setting the different column voltages Vd(Xau) used in the compensation method. It can be set relatively easily experimentally by measuring the transmittance.

Defining the range of on-off state transitions makes it easier to implement the second compensation method. sand That is, the range from Xau to (Xau 10n) is defined. Here, n takes values such as 1.2.3. There are no factors that cause a noticeable difference in brightness. If not, the voltage Vj can be set to the same value.

Simultaneous - In the case of row addressing, both the polarity of the data signal and the polarity of the row select signal are For example, it is reversed every time the rask time ends. This prevents the generation of DC voltage components It is necessary for It actually reverses the polarity after a certain number of waiting periods . The fixed number of times is less than N.

Therefore, the number of on-off state transitions (including the number of off-on state transitions) is Now, the polarity of the voltage Vd reproduced in Figures 1 and 4 is reversed (or the voltage level of Vd is It does not have to be equal to the number of fluctuations in the

Two compensation methods have been explained, and Xau is the extreme value of Vd that occurs during the rask Interpreted as the number of gender reversals or, more generally, the number of changes in the data voltage level. be done.

The latter interpretation of Xau has particularly important meaning in multiline addressing.

It is possible to apply voltage pulses with different amplitudes to different columns each time a frame scan is completed. By making full use of the concept 1, the dot matrix explained in this patent application It is possible to realize gradations in a display device with a base structure.

This method will be described in detail below.

Currently, gray scale is achieved by performing frame modulation (FM) or pulse width modulation (PWM). That has been realized.

FM Nitsuiteha, SID Technical Document Handbook XIV (1983 edition, pages 32-33) It is listed in Nat. The disadvantage of FM is that the high-speed switching liquid crystal display does not flicker. ” will occur. Regarding PWM, see SID Technical Document Handbook XI (198 2006 edition, pages 28-29). For PWM, increase the number of gradation steps. It has the disadvantage that it requires a high frequency signal for the addition.

The third method to achieve gradation is to use pulse height modulation (PHM), For display devices in which each display element is equipped with an active electronic switch such as a thin film transistor. used. In such actively controlled matrix display devices, Corresponds to the display element by supplying a voltage with a constant amplitude to the target element. Achieving pixel gradations of However, this method requires simultaneous-row RMS addressing The matrix display device described in this patent application using multi-row RMS addressing cannot simply be applied.

In other words, fluctuations in column voltage amplitude are detected for all elements in the column of interest. It is. For example, for a particular column, during the row selection time the amplitude is fXVd (where When realizing pixel gradation by applying a data voltage of -1≦f≦+1) (For ease of understanding, consider the simultaneous row addressing case.) ). For the ON elements in this column, the following formula holds.

Von2 = (Vs+Vd)2/N+ (N-2) x Vd2/N+ (f xVd)2/N (11) According to formula (11), the RMS voltage of the on-element is It depends on the (absolute) value of the meter f. This is clearly not desirable.

After the frame scan ends (for example, after the row time tl has elapsed), a voltage pulse is applied to the column of interest. The loss of RMS voltage can be compensated for by supplying

In this case, the pulse height of the voltage pulse is, for example, a certain gray level expressed as a coefficient f value. It depends on the number of elements on the column of interest that correspond to pixels with values.

Here, the state values of a completely on state and a completely off state are also considered as gradation values.

If the number of elements corresponding to grayscale pixels and each grayscale value are given, on elements and off elements The formula for the RMS voltage of is derived, and the calculated RMS voltage value is expressed as formula (1) and ( By equating according to 2), the pulse height of the voltage pulse can be determined (calculated). Wear.

Next, an example of the procedure for setting the pulse height will be shown. Compensation pulse Vc during row time t1 Consider the case where .

Example) In a 4-row matrix, one ON display element on a certain column and the other display elements When the tone values (or f values) of corresponding pixels are different For a 4-row matrix, the RMS voltage of the on-element (and off-element) is Alt According to the simultaneous-row addressing method by Pleshko and .

Von2=(S4+D4)2/4+3x D42/4 (12) Voff2 = (S4-D4)2/4+3XD42/4 (13) Here, S4 is D Equal to 4 x 5QRT(4), S4 represents the row select voltage and D4 is the data voltage represents.

When performing PHM (and using compensation voltage pulses) to achieve gray scale, the fifth Add rows to the 4-row matrix. This line does not have to exist. virtual Lines are fine.

The following RMS voltage is applied to the ON element in this example.

Von2=(S5+D5)215+(flxD5)215+(f2xD5 ) 215 + (f3xD5) 215 + Vc215 (14) Here, fiXD 5 represents the amplitude of the data voltage. This data voltage is denoted by the parameter value fi It is applied to the pixel of interest i corresponding to the pixel having the gradation value.

When the fifth (virtual) row is selected, a constant voltage is applied to the corresponding column. Therefore, the value of Vc215 increases.

The value of Vc is such that Von2 according to formula (12) is equal to Von2 according to formula (14). Occurs when a value is indicated.

When selected, S5 = S4 X 5QRT (5/4) (15) and D5 = D4 x 5QRT (5/4) (16) Therefore, 3X D42/4=(115)X(flxD4)2x(5/4)+( 115) X (f2xD4) 2x (5/4) + (115) X (f3x D4) 2X (5/4) + Vc215 (17) or Vc215=D42x (3-fl2-f22-f32)/4 (18) Vc 215 = D42 x (3-Σf12)/4 (19) In this way, the formula ( 19), the resulting Von2 is equal to V in equation (12). Shows the same value as on2. Even if we focus on off-devices instead of on-devices, the results are It's the same. For example, if we focus on a pixel whose gradation value corresponds to rl, The RMS voltage ■fl of the corresponding display element can be calculated as follows.

Vf 12 = (S5 + f 1xD5) 215 + D5215 + (f2xD5 )215+(f3xD5)215+Vc215 (20) Equations (18) and (15 ) and (16) into formula (20), Vf 12 = (S4 + f 1x D4) 215 + (4/4) X D42 - (1/4) x (flxD4)2 (21) If S4 is replaced with 5QRT(4) x D4, Vf12=[8+2xSQR T(4)xfll　XD42/4　(22) Also, if you transform the above formula, Von2=[8+2xSQRT(4)] x D42/4 (23) Formula (2 2) and formula (23), it is found that when fl<1, the RMS voltage Vf12 It can be seen that Von2 is smaller than Von2. The equation for a general N-row matrix is It is also possible to set In this case, the value of Vc is determined according to the procedure above. Ru. That is, SN+l = 5QRT ((N+1)/N) X SN and ON +1=SQRT((N+t)/N)xDNThe i-th element placed in a certain column is turned on. Then, when specifying the address of the virtual (N+1) row matrix, this The RMS voltage of the i-element is calculated as follows.

VON2=(SN+1fDN+1)2/(N+1)+ΣfK2x DN+1 2/(N+1)+　Vc2/(N+1)　(24)K=1 (K≠2) By replacing the relationship between SN+1 and SN above with the relationship between DN+1 and DN, the standard Equating according to All and Pleshko's N-row RMS addressing scheme, V on2=(SN+0N)2/N+(N-1) x DN2/N where, SN 2 is equal to NXDN2.

Therefore, Vc2/(N+1)=DN2X [(N-1)-Σfk21/N (25)k =1 (k≠i) =DN2X (N-Σfk2] /N (26) k=1 Here, the coefficient fi is l as described above. i.e. information (about a particular column) information, while keeping the RMS voltage between the on and off elements at the correct value. , determine the pulse height of the voltage pulse that enables the PHM to reliably achieve gradation. Can be determined.

In one typical embodiment of the display device of the present invention, the display device includes a display element. The parameter X defined as above for each rask scan for each column j of the matrix It is characterized by being composed of an electronic circuit that registers the value of au (D).

The display device of the present invention further provides a data voltage ±Vd (simultaneous - row add) during rask scanning. The amplitude Vd of the voltage between the display elements during the non-selection period in the response designation is different from Xa It is characterized by being different between columns with u values.

In the case of multi-row addressing, there is no problem with Vd on the Nilepel data voltage, but There is a problem with the bell data voltage. For example, in the case of 3-line addressing, there are 4 types of voltages. The level is used with two types of amplitudes: ±v3 and 3/3.

However, the value of v3 is set as described above.

Claims (8)

[Claims] 1. Placed between two support plates held at a specified distance and with their surfaces facing each other. The placed liquid crystal material, the pattern of N row electrodes provided on one surface, and the pattern of N row electrodes provided on one surface, and the It consists of a pattern of column electrodes provided on the surface, and the row electrodes intersect with the column electrodes. This is a display device in which a matrix is formed using intersection positions as display elements. A control circuit that applies a square wave data signal to the column electrodes and periodically scans the row electrodes. a row scanning circuit for applying a square wave row selection voltage signal; A display device comprising: 2. Furthermore, the parameter Xau( j) consists of an electronic circuit section that registers the value (value defined in the description of the invention). The display device according to claim 1, characterized in that: 3. During raster scanning, data voltage ±Vd (non-select period in simultaneous single row addressing) The amplitude Vd of the voltage between the display elements (between display elements) may differ between columns with different Xau values. A display device according to claim 1 or 2, characterized in that: 4. The selected value of Vd increases with Xau and is considered in particular to be in the same state. is a display element in which the VRMS voltage of display elements existing in columns with different Xau values is , Vd=Vd(Xau ) Claims 1, 2, or The display device according to item 3. 5. The range of Xau values from Xau to (Xau+n) (where n=1, 2, 3...) In the claims 1, 2, 3, and 3, Vd is set to the same value. or the display device according to item 4. 6. An appropriate voltage whose amplitude AMPc is set based on the Xau value of the column of interest is Claim characterized in that the voltage is applied to separate columns for a certain period of time each time data scanning is completed. The display device according to item 1 or 2. 7. The range of Xau values from Xau to (Xau+n) (where n=1, 2, 3...) In the claims 1, 2, and 3, AMPc is set to the same value. or the display device according to item 6. 8. Furthermore, it is composed of an electronic circuit section that realizes gradations by pulse height modulation, and has an amplitude A. MPg applies an appropriate voltage set based on the image content of the column of interest at the end of the raster scan. Claim 1, characterized in that the voltage is applied to separate columns for a certain period of time each time the signal is applied. The display device described in .