JPH0749827A - Generating device for response signal of cpu - Google Patents

Abstract

PURPOSE:To minimize the circuit scale when many peripheral circuits are connected to the CPU and to generates the response signal which shows the width of a bus used between the CPU and a peripheral circuit and is used to detect the end of data transfer operation on the peripheral circuit side without any circuit alteration according to the access time and bus width of the peripheral circuit. CONSTITUTION:When the CPU accesses one of the peripheral circuits A-D, respective decoders read the bus width of an accessed peripheral circuit out of 8-circuit D flip-flops and a bus width setting circuit 20 outputs signals BS0 and BS1 showing the bus width. Simultaneously, the respective decoders and a wait quantity setting circuit 16 reads the wait quantity of the accessed peripheral circuit out of the 8-circuit D flip-flops and an ACK signal generating circuit 22 outputs the signals BS0 and BS1 as attack signals ACK0 and ACK1 to the CPU after a time corresponding to the read wait quantity lapses.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention represents the bus width used between a CPU and a peripheral circuit according to the access time of the peripheral circuit accessed by the CPU, and the CPU controls the data transfer operation on the peripheral circuit side. The present invention relates to a response signal generation device for a CPU that generates a response signal for detecting the end.

[0002]

2. Description of the Related Art Conventionally, as a typical CPU that performs so-called asynchronous data transfer with peripheral circuits such as ROM and RAM, for example, there is a Motorola 68000 series CPU.

Here, the outline of this asynchronous data transfer will be described with reference to FIG. As a premise, C
PU transfers 1 of system clock CLK when transferring data.
Eight operations (hereinafter, referred to as states) S0 to S7 are executed with the / 2 cycle as one unit.

First, in data transfer from a peripheral circuit to a CPU (hereinafter referred to as a read cycle), as shown in FIG. 9A, first, in a state S1, the CPU sends an address corresponding to the peripheral circuit to be accessed. In the subsequent state S2, an address strobe signal (not shown) indicating that a valid address is present on the address bus and a data strobe signal DS indicating that the data on the data bus is valid are output. Output at active low level respectively. At this time, the CPU 2 also outputs the read / write signal R / W indicating the transfer direction of the data bus at a high level indicating a read cycle.

Then, the peripheral circuit recognizes that it is accessed by the address on the address bus and outputs the data on the data bus. The time from the access of the peripheral circuit to the end of the data output depends on the access time peculiar to each peripheral circuit (the time required from the designation of its own address to the end of the data transfer operation). There are various.

Then, the CPU does not output a new signal in the states S3 and S4, and immediately after the state S4 (at the falling edge of the system clock CLK), a response signal (hereinafter also referred to as an ACK signal) input from the outside. ) ACK
Detect the level of. At this time, the AC signal AC
If K is at the low level, it is recognized that the data transfer operation on the peripheral circuit side has ended, and the data on the data bus is read immediately after states S5 and S6 in which no new signal is output, and in the subsequent state S7. , The address strobe signal and the data strobe signal DS are returned to the high level,
One read cycle is completed.

On the other hand, as shown in FIG.
However, when the ACK signal ACK is detected to be at the high level immediately after the state S4, the CPU determines that the state S
Until the ACK signal ACK becomes low level by repeating 3 and S4, the end operation of the read cycle after the state S5 is not performed.

Next, in data transfer from the CPU to the peripheral circuits (hereinafter referred to as a write cycle), FIG.
As shown in, the CPU first outputs the address corresponding to the peripheral circuit to be accessed in the state S1, and outputs the address strobe signal (not shown) in the subsequent state S2.
Output at low level and read / write signal R / W
Is output at a low level that indicates a write cycle. Then, in the subsequent state S3, the data is output onto the data bus, and in the state S4, the data strobe signal DS is output at a low level.

Then, the peripheral circuit recognizes that it is accessed by the address on the address bus and reads the data on the data bus. In addition, the time from the access of the peripheral circuit to the end of the data reading is also
It varies depending on the access time of each peripheral circuit.

Immediately after the state S4, the CPU detects the level of the ACK signal ACK input from the outside, and if the ACK signal ACK is at the Low level, the data transfer operation on the peripheral circuit side is completed. Then, after the states S5 and S6 in which no new signal is output, in the subsequent state S7, the address strobe signal and the data strobe signal DS are returned to the high level, and one write cycle is completed. The CPU immediately after the state S4, in other words, immediately before the state S5,
When it is detected that the ACK signal ACK is at the high level, the states S5 and S6 are repeated, and the write cycle of the state S7 is ended until it is detected that the ACK signal ACK is at the low level as in the read cycle. It does not operate.

As described above, in the CPU which performs asynchronous data transfer, the ACK signal ACK input from the outside is Low.
The end operation of the data transfer is not started until the level is detected, and accordingly one cycle of the data transfer is extended by one cycle unit of the system clock CLK. In the following, one cycle of data transfer is referred to as a data transfer cycle, and the number of system clock cycles by which the data transfer cycle is extended is referred to as the number of waits.

More recently, among CPUs that perform such asynchronous data transfer, the bus width (data bus) used between the CPU and peripheral circuits, such as the Motorola 68020 and 68030, is used. CPU that uses a 2-bit signal representing the bit number of
There is.

That is, this type of CPU is provided with, for example, two ACK signal input terminals, and when at least one of the two ACK signal input terminals becomes low level after the peripheral circuit is accessed, The operation of ending the data transfer is started, and the bus width used for the peripheral circuit is based on the 2-bit data input from the ACK signal input terminal at this time. If the data is "10", the 8-bit bus is used, if the data is "01", the 16-bit bus is used, and if the data is "00", the 32-bit bus is used.

Therefore, when a microcomputer is constructed by connecting peripheral circuits having different access times and different bus widths to a CPU which uses such a signal representing the bus width as an ACK signal, each peripheral circuit is controlled by the CPU. After the access is detected, a predetermined time (hereinafter referred to as wait time) corresponding to the access time of each peripheral circuit is counted from the time of detection, and then the signal representing the bus width corresponding to the peripheral circuit is used as an ACK signal. It is necessary to output the data to the CPU, which makes it possible to ensure the data transfer between the CPU and each peripheral circuit. A response signal generation device is provided for this purpose.

Therefore, conventionally, the response signal generating apparatus of this type detects from a NAND circuit (nand gate) for detecting that all the predetermined bits on the address bus corresponding to the peripheral circuit are activated, and the NAND gate. 2-bit data output other than "11" that represents the bus width of the timing circuit such as a multivibrator or shift register that counts a predetermined wait time when a signal is output, and the peripheral circuit accessed when the timing circuit completes the timing Each of these circuits is provided for each peripheral circuit, and each bit output of each logic circuit that outputs 2-bit data representing the bus width is output in the wired OR format from the CPU. It was designed to be input to each ACK signal input terminal.

[0016]

However, in the above-mentioned conventional device, a clock circuit and a bus width for counting the wait time by the number of peripheral circuits connected to the CPU are represented.
It is necessary to provide a logic circuit for outputting bit data, which causes a problem that the circuit scale of the microcomputer becomes large.

In addition, when the peripheral circuits connected to the CPU are changed to those having different access times or bus widths, there is a problem that the circuit configuration of the clock circuit and the logic circuit must be changed each time. The present invention has been made in view of such a problem, and when a large number of peripheral circuits are connected to a CPU, the circuit scale can be minimized, and the peripheral circuits can be accessed without changing the circuit. The response of the CPU, which represents the bus width used by the CPU with the peripheral circuit and can generate a response signal for detecting the end of the data transfer operation on the peripheral circuit side according to the time and the bus width. An object is to provide a signal generation device.

[0018]

SUMMARY OF THE INVENTION That is, the present invention, which has been made to achieve the above object, is connected to a plurality of peripheral circuits, accesses arbitrary peripheral circuits, and transfers data to and from the peripheral circuits. At the time of execution, it is used for the CPU which detects the end of the data transfer operation on the peripheral circuit side by the response signal representing the bus width used with the peripheral circuit input from the outside and starts the end operation of the data transfer. A response signal generation device for a CPU, which detects that the CPU has accessed any of the peripheral circuits, and generates the response signal according to the access time of the accessed peripheral circuit. Wait time storage means for storing the wait time corresponding to each access time, bus width storage means for storing the bus width corresponding to each of the peripheral circuits, and each of the peripheral circuits described above. A detecting unit that detects access by the PU and, when the detecting unit detects that one of the peripheral circuits is accessed, the bus width corresponding to the accessed peripheral circuit is set to the bus width storage unit. And a bus width reading means for outputting a response signal indicating the bus width, and when the predetermined wait time is set, the wait time is measured and after the wait time elapses,
When the response signal generating means for outputting the response signal output by the bus width reading means to the CPU and the access means detect any of the peripheral circuits, the access is made. Wait time setting means for reading the wait time corresponding to the peripheral circuit from the wait time storage means and setting the wait time in the response signal generating means.
The gist is the response signal generator of the PU.

[0019]

In the response signal generating device for a CPU of the present invention having the above-described structure, the wait time storage means has a wait time corresponding to the access time of each peripheral circuit connected to the CPU. The bus width is stored and the bus width corresponding to each peripheral circuit is stored in the bus width storage means. Then, the detecting means detects that the CPU has accessed each peripheral circuit.

When the detecting means detects that any of the peripheral circuits is accessed, the bus width reading means reads the bus width corresponding to the accessed peripheral circuit from the bus width storing means, A response signal representing the bus width is output. At the same time, the wait time setting means reads the wait time corresponding to the accessed peripheral circuit from the wait time storage means and sets the read wait time in the response signal generating means.

Then, the response signal generating means measures the wait time set by the wait time setting means, and after the wait time has elapsed, outputs the response signal output by the bus width reading means to the CPU. To do. That is, in the response signal generating device for a CPU of the present invention, when any of the peripheral circuits is accessed by the CPU, the bus width corresponding to the peripheral circuit is read from the bus width storage means and the wait time storage means stores the bus width. After the wait time corresponding to the access time of the peripheral circuit is read and the wait time is commonly measured by the response signal generation means, the response signal representing the bus width read from the bus width storage means is output to the CPU.

Therefore, according to the response signal generating device of the CPU of the present invention, as in the conventional device, the clock circuit for measuring the wait time for each peripheral circuit connected to the CPU and the data representing the bus width are output. It is not necessary to provide a logic circuit for this purpose, and it is possible to minimize an increase in circuit scale due to an increase in peripheral circuits.

Furthermore, when the peripheral circuit connected to the CPU is replaced with one having a different access time or a different bus width to be used, the contents stored in the wait time storage means and the bus width storage means are simply changed. Since the wait time and the bus width can be set according to the peripheral circuit, it is not necessary to change the circuit unlike the conventional device.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a microcomputer of an embodiment to which the present invention is applied.

As shown in FIG. 1, the microcomputer of this embodiment includes a CPU 2 for performing asynchronous data transfer using a 2-bit signal representing a bus width as an ACK signal, as described in the section "Prior Art". , CPU2 A0-A31
32-bit address bus 4 and 32 of D0 to D31
A plurality of (four in this embodiment, four for convenience of explanation) peripheral circuits A to D connected via a bit data bus 6
And a cycle control unit 8 which detects that the CPU 2 has accessed any of the peripheral circuits A to D and outputs 2-bit ACK signals ACK0 and ACK1 representing the bus width of the peripheral circuit to the CPU 2. I have it. Incidentally, the breakdown of the peripheral circuits A to D is, for example, an EPROM (hereinafter, simply referred to as ROROM) in which the peripheral circuit A can rewrite programs and data.
Peripheral circuit B is a RAM, and peripheral circuits C and D are other I / O devices.

A read / write signal R / W indicating the transfer direction of the data bus 6 and an address strobe signal AS indicating that a valid address is present on the address bus 4 are sent from the CPU 2 to the peripheral circuits A to D. , And various signal lines required for data transfer such as a data strobe signal DS indicating that the data on the data bus 6 is valid. The address bus 4 and the data bus 6 are connected to the cycle controller 8, and the system clock CLK from the CPU 2 and the address strobe signal AS are connected.
Also, a data strobe signal DS, a write protect signal WP and a register control signal RC, which will be described later, are input.

Here, in the peripheral circuit A (ROM), 8-bit data representing the number of weights corresponding to the access times of the peripheral circuits A to D and the peripheral circuits A to D are stored in advance.
A total of 16-bit data consisting of 8-bit data representing the corresponding bus width and are stored in the data lines of D0 to D15 of the data bus 6 at power-on and reset start. It is designed to output above.

In this 16-bit data, the data value of every 2 bits from the least significant bit to the 8th bit (D0 to D7) directly represents the number of weights corresponding to the peripheral circuits A to D, respectively. , If the data value for each 2 bits from the 9th bit to the 16th bit (D8 to D15) is 0, it is an 8-bit bus, if it is 1, it is a 16-bit bus, and if it is 2,
Each peripheral circuit A, such as a 2-bit bus, is indirectly
The bus widths corresponding to D are shown. For example, the 16-bit data is "00010010,0
0011001 ”, the number of weights corresponding to the peripheral circuits A to D is 1, 2, 1, 0, respectively, and the bus widths corresponding to the peripheral circuits A to D are 32 bits, 8 bits, 16 respectively. 8 bits. In this embodiment, the number of weights larger than 2 and the bus width larger than 32 bits are not set.

When the power is turned on and the reset is started, the CPU 2 outputs the write protect signal WP to the cycle control unit 8 at the high level and then changes the register control signal RC from the low level to the high level. . Then, in the microcomputer of this embodiment, the CPU 2 outputs the address data corresponding to any of the peripheral circuits onto the address bus 4 as well as the read / write signal, as described in detail in the section "Prior Art". By outputting R / W in response to a read cycle or a write cycle and setting the address strobe signal AS and the data strobe signal DS to the low level, data transfer with a desired peripheral circuit is started, which will be described later. To the ACK signal ACK0 output from the cycle control unit 8,
When it is detected that at least one of ACK1 is at the Low level, it recognizes that the data transfer operation on the accessed peripheral circuit side is completed and starts the data transfer end operation.

Next, as shown in FIG. 1, the cycle control unit 8 which is a main part relating to the present application detects that the CPU 2 has accessed any of the peripheral circuits A to D, and determines the accessed peripheral circuit. Access detection section 10 as detection means for outputting detection signals EXA-EXD shown, and ACK signal generation for generating ACK signals ACK0, ACK1 based on detection signals EXA-EXD from this access detection section 10 and outputting them to CPU2 And a part 12.

As shown in FIG. 2, the access detection unit 10
Is composed of four NAND gates NAND1 to NAND4, and a NOR gate NOR that takes the NOR of the address strobe signal AS and the data strobe signal DS from the CPU2.
The output signal of the NOR gate NOR is commonly input, the address signal on the address bus 4 corresponding to the peripheral circuit A is input to the NAND gate NAND1, and the address signal corresponding to the peripheral circuit B is input to the NAND gate NAND2. As described above, the address signals corresponding to the peripheral circuits A to D are respectively input.

The access detection unit 10 thus configured
In the above, when the CPU 2 accesses any of the peripheral circuits A to D, all the address signals on the address bus 4 corresponding to the peripheral circuit become High level, and the address strobe signal AS and the data strobe signal DS become
Each NAND gate NAND1 to 4 becomes low level.
Of the output signals of, only the signal corresponding to the accessed peripheral circuit becomes low level. The output signals of the NAND gates NAND1 to NAND4 represent the detection signals EXA to EXD representing the peripheral circuits A to D accessed by the CPU2.
Is output to the ACK signal generator 12.

Then, as shown in FIG. 3, the ACK signal generator 12 receives 16-bit data D0 to D15 input from the peripheral circuit A (ROM) via the data bus 6 at the time of power-on and reset start. Out of D0 to D7
The number of weights corresponding to each of the peripheral circuits A to D is stored based on the 8-bit data of
Based on the detection signals EXA to EXD from 0, the number of weights corresponding to the peripheral circuits A to D accessed from the CPU 2 is searched, and the search signals AWT0, AWT1, AWT2 to D are searched.
A weight number search circuit 14 for outputting WT0, DWT1, DWT2, and a search signal A from the weight number search circuit 14.
WT0, AWT1, AWT2-DWT0, DWT1, D
Based on WT2, setting signals WT0 and WT representing the number of weights corresponding to the peripheral circuits accessed from CPU2
1 and WT2, a wait number setting circuit 16 as a wait time setting means, and a peripheral circuit A (ROM) to the data bus 6 at power-on and reset start.
Based on the 8-bit data of D8 to D15 among the 16-bit data of D0 to D15 input via the, the corresponding bus width is stored in each of the peripheral circuits A to D, and the detection signal from the access detection unit 10 is stored. The bus width corresponding to the peripheral circuits A to D accessed from the CPU 2 is searched based on the EXA to EXD, and the search signals ABS0, ABS1, and AB are searched.
A bus width search circuit 18 that outputs S2 to DBS0, DBS1, and DBS2, and a search signal A from the bus width search circuit 18
BS0, ABS1, ABS2-DBS0, DBS1, D
2-bit signals BS0 and BS1 representing the bus width corresponding to the peripheral circuit accessed from CPU2 based on BS2
When the access width is detected by the bus width setting circuit 20 as a bus width reading unit and the access detection unit 10 detects that one of the peripheral circuits is accessed, the setting signals WT0 and WT1 from the weight number setting circuit 16 are output. , WT2, the time corresponding to the number of waits is counted, and the 2-bit signal BS output from the bus width setting circuit 20 to the CPU 2 is output.
0, BS1 as ACK signals ACK0, ACK1 and ACK signal generation circuit 2 as response signal generation means
2 and.

First, as shown in FIG. 4, the number-of-waits search circuit 14 is an OR gate OR1, an eight-circuit D flip-flop 24 as a wait time storage means, and four decoders 26, 28 as wait time setting means. , 3
It is composed of 0 and 32.

The eight-circuit D flip-flop 24 is a well-known circuit incorporating eight D flip-flops that use the signal from the clock terminal CK as a common clock, and the rising timing of the signal input from the clock terminal CK The input signals from the input terminals 1D to 8D are latched and output from the output terminals 1Q to 8Q, respectively.

The decoders 26, 28, 30, 32 are also provided.
Is a well-known line decoder having two input terminals IS0 and IS1, three output terminals Y0, Y1 and Y2, and an enable terminal E. When the input signal from the enable terminal E is at a low level If the input signals from the input terminals IS0 and IS1 are both at the low level, a low level signal is output only from the output terminal Y0, the input signal from the input terminal IS0 is at the high level, and the input signal from the input terminal IS1 is If it is low level, a low level signal is output only from the output terminal Y1 and the input signal from the input terminal IS0 is low.
If it is at the w level and the input signal from the input terminal IS1 is at the high level, the low level signal is output only from the output terminal Y2. Further, when the input signal of the enable terminal E is High level, all the output terminals Y0, Y1, Y2 are High regardless of the input signals from the input terminals IS1, IS0.
Output level signal.

As shown in FIG. 4, 8-bit data D0 to D7 on the data bus 6 are input to the input terminals 1D to 8D of the 8-circuit D flip-flop 24, respectively, and the output terminals 1Q are output. 8Q are connected to the input terminals IS0 and IS1 of the decoders 26, 28, 30, and 32 in units of two, respectively. Further, the OR gate OR1 has a C
The write protect signal WP and the register control signal RC from PU2 are input, and the output signal of the OR gate OR1 is input to the clock terminal CK of the 8-circuit D flip-flop. Furthermore, the detection signals EXA to EXD from the access detection unit 10 are input to the enable terminals E of the decoders 26, 28, 30, and 32, respectively.

In the weight number search circuit 14 thus constructed, when the write protect signal WP from the CPU 2 and the register control signal RC are both at the high level at power-on and reset start, the OR gate OR1 rises. An edge is output, and the 8-circuit D flip-flop 24 latches each data D0 to D7 which the peripheral circuit A (ROM) is outputting to the data bus 6 at that time, and outputs each data to the output terminals 1Q to 8Q, respectively. Output from. That is, at this time, the number of weights stored in the peripheral circuit A (ROM) is represented by 8
The bit data is stored in the 8-circuit D flip-flop 24.

As described above, the write protect signal W
The CPU 2 stores the data in the 8-circuit D flip-flop 24 only when both P and the register control signal RC become High level.
For some reason, when proper data is not output on the data bus 6, the register control signal RC is set to Hi.
Even if it is changed to gh level, the write protect signal WP
8 circuit D flip-flop 24
This is to prevent the stored contents of the item from being changed.

When any of the detection signals EXA to EXD from the access detection unit 10 becomes low level,
The decoders 26 to 32, to which the detection signal is input, decode the 2-bit data from the 8-circuit D flip-flop 24 as described above, and output the decoded output signal.
Search signals AWT0, AWT1, AWT2 to DWT0, D
It is output to the weight number setting circuit 16 as WT1 and DWT2.

For example, "000" indicating that the number of weights of the peripheral circuits A to D is 1, 2, 1, 0 in the order of 8Q to 1Q from the output terminal of the 8-circuit D flip-flop 24, respectively.
When the peripheral circuit B is accessed by the CPU 2 and the detection signal EXB becomes Low level while "11001" is output, the search signals AWT0, AWT1, AWT2 to
Of DWT0, DWT1, DWT2, only BWT2 is Lo
If the peripheral circuit D is accessed and the detection signal EXD becomes Low level, only DWT0 becomes Low level.
w level.

That is, the search signals AWT0, AWT1, A
The leading alphabet and the ending numeral of WT2 to DWT0, DWT1, and DWT2 correspond to the peripheral circuit and the number of weights thereof, respectively, and when any peripheral circuit is accessed by the CPU 2, the accessed peripheral Only the search signal corresponding to the number of circuit weights is output at Low level.

Next, the weight number setting circuit 16 is composed of three AND gates AND1 to AND3, as shown in FIG. 5, and the weight number search circuit 14 outputs to each AND gate AND1 to AND3. Search signal AWT0,
AWT1, AWT2-DWT0, DWT1, DWT2
Are input for each signal corresponding to each weight number.
The output signals of the NAND gates NAND1 to NAND3 are
It is output to the ACK signal generation circuit 22 as setting signals WT0, WT1, and WT2, respectively.

That is, the setting signals WT0, WT1, WT2
The number at the end of the number corresponds to the number of weights of the peripheral circuit accessed by the CPU 2, and the setting signal WT0,
Of WT1 and WT2, only the signal corresponding to the number of waits of the accessed peripheral circuit is output at the Low level.

On the other hand, the bus width search circuit 18, as shown in FIG. 6, is constructed in exactly the same way as the wait number search circuit 14, and receives the write protect signal WP and the register control signal RC from the CPU 2. A bus for decoding an OR gate OR2 and an output signal of the OR gate OR2 as a clock signal from an 8-circuit D flip-flop 34 serving as a bus width storage unit and an output signal from the 8-circuit D flip-flop 34 in units of two. Four decoders 36, 38, 40 as width reading means,
And 42. And this bus width search circuit 1
8 and the above-described weight number search circuit 14 are different only in that 8-bit data D8 to D15 on the data bus 6 are input to the respective input terminals 1D to 8D of the 8-circuit D flip-flop 34.

The bus width search circuit 18 thus configured
In the above, when the write protect signal WP and the register control signal RC from the CPU 2 are both at the high level at power-on and reset start,
The 8-circuit D flip-flop 34 is then operated by the peripheral circuit A.
Each data D8 output from the (ROM) to the data bus 6
~ D15 is latched and each data is output terminal 1
Output from Q to 8Q. That is, at this time, the 8-bit data representing the bus width stored in the peripheral circuit A (ROM) is stored in the 8-circuit D flip-flop 34.

In the bus width search circuit 18, too,
8 circuits D only when both the write protect signal WP and the register control signal RC are at high level
Data is stored in the flip-flop 34 so that the stored contents of the 8-circuit D flip-flop 34 are not changed when appropriate data is not output on the data bus 6.

When any of the peripheral circuits A to D is accessed by the CPU 2 and any one of the detection signals EXA to EXD from the access detecting section 10 becomes low level, the decoder 36 to which the detection signal is input is input. 42
Each 2-bit data from the 8-circuit D flip-flop 34 is decoded exactly as in the case of the weight number search circuit 14, and the decoded output signal is used as the search signal ABS0,
It is output to the bus width setting circuit 20 as ABS1, ABS2 to DBS0, DBS1 and DBS2.

For example, "00010010" indicating that the bus widths of the peripheral circuits A to D are 32 bits, 8 bits, 16 bits, and 8 bits in the order of 8Q to 1Q from the output terminal of the 8-circuit D flip-flop 34, respectively. When the peripheral circuit B is accessed by the CPU 2 and the detection signal EXB becomes low level while "" is output, the search signal ABS
0, ABS1, ABS2-DBS0, DBS1, DBS
Of B2, only BBS0 becomes low level, and when the peripheral circuit C is accessed and the detection signal EXC becomes low level, only CBS1 becomes low level.

That is, the search signals ABS0, ABS1, A
The first alphabet and the last numeral of BS2 to DBS0, DBS1, and DBS2 correspond to the peripheral circuit and the data value that indirectly indicates the bus width, respectively.
When any peripheral circuit is accessed by 2, only the search signal indicating the bus width of the accessed peripheral circuit is returned.
It is output at Low level.

The bus width setting circuit 20 is composed of five AND gates AND4 to AND8 as shown in FIG. 7, and the AND gates AND4 to AND6 are provided with the search output from the bus width search circuit 18. Signal ABS0, ABS
1, ABS2 to DBS0, DBS1, and DBS2 are input for each signal corresponding to each bus width. Then, the output signals of the NAND gates NAND4 and NAND6 become NAND gate N.
AND7, each output signal of NAND gate NAND5,6 is input into NAND gate NAND8,
The output signals of the NAND gates NAND7 and NAND8 are output to the ACK signal generation circuit 22 as 2-bit signals BS0 and BS1, respectively.

Therefore, the search signals ABS0, ABS1, ABS2 to DBS0, DBS from the bus width search circuit 18 are obtained.
1 or DBS2, a 2-bit signal BS is output when a search signal whose number at the end is "0", which indicates that the bus width of the accessed peripheral circuit is 8 bits, is low level.
Of BS0 and BS1, only BS0 goes low, and when the search signal with the last digit "1" indicating that the bus width is 16 bits is low, only BS1 goes low.
When the search signal having the w level and the number at the end indicating that the bus width is 32 bits is "2" is at the Low level, both BS0 and BS1 are at the Low level. In other words, these two 2-bit signals BS0 and BS1 correspond to the 2-bit signal representing the bus width described in the "Prior Art" section.

Then, the ACK signal generating circuit 22 has the same structure as that shown in FIG.
As shown in FIG. 3, an AND gate AND9 that takes the logical product of the detection signals EXA to EXD, and the D flip-flops DFF1, DFF2, DFF3 that inputs the output signal of the AND gate AND9 as data and the system clock CLK as the clock signal Shift register 44 consisting of the following, and a setting signal WT from the weight number setting circuit 16
0 and the output signal of the D flip-flop DFF1 are input to the OR gate OR3, the setting signal WT1 and the output signal of the D flip-flop DFF2 are input to the OR gate OR4, the setting signal WT2 and the D flip-flop DFF
The OR gate OR5 to which the output signal of 3 is input, the AND gate AND10 that takes the logical product of the output signals of the OR gates OR3 to 5, and the 2-bit signals BS0 and BS1 from the bus width setting circuit 20 are input, respectively. It is composed of OR gates OR6 and 7 to which the output signal of the AND gate AND10 is commonly input.

In the ACK signal generating circuit 22 thus constructed, when all the peripheral circuits A to D are not accessed and the detection signals EXA to EXD are all at the high level, the output signal of the AND gate AND9 is output. Since it becomes the High level, all the output signals of the D flip-flops DFF1 to 3 become the High level, and each OR gate OR
Ac signal A of high level from 6, 7 to CPU 2
CK0 and ACK1 are output.

When any of the peripheral circuits is accessed and any one of the detection signals EXA to EXD becomes low level, the output signal of the AND gate AND9 becomes low level and the shift register 44 receives low level data. Is input, a Low level signal is output from any of the OR gates OR3 to OR5 after a predetermined period of the system clock CLK corresponding to the setting signals WT0, WT1, and WT2 that are at Low level at that time. Then, since the output signal of the AND gate AND10 becomes Low level,
2-bit signals BS0 and BS1 representing the bus width from the bus width setting circuit 20 from the OR gates OR6 and 7 to the CPU2.
Will be output as ACK signals ACK0 and ACK1.

For example, one of the peripheral circuits is accessed and the setting signals WT0 and W from the weight number setting circuit 16 are accessed.
Of the T1 and WT2, when the setting signal WT1 indicating that the number of weights is 1, becomes low level, the OR gate OR
If only the OR gate OR4 of 3 to 5 is allowed to change its output and then the rising edge of the system clock CLK is input to the ACK signal generating circuit 22 twice, the D flip-flop DFF forming the shift register 44 is formed.
The output signal of 2 becomes low level, and OR gate OR4
Output signal changes to Low level and OR gate OR6
2-bit signals BS0 and BS1 are output from the CPU 7 to the CPU 2 as ACK signals ACK0 and ACK1. Further, when the setting signal WT2 indicating that the number of weights is 2 becomes Low level, only the OR gate OR5 is allowed to change its output, and thereafter, the ACK signal generating circuit 22
When three rising edges of the system clock CLK are input to the CPU 2, the OR gates OR6 and 7 send the 2-bit signals BS0 and BS1 to the CPU 2 to acknowledge the signals ACK0 and ACK.
It will be output as 1.

That is, in the ACK signal generating circuit 22, by changing the number of stages of the shift register 44 in accordance with the setting signals WT0, WT1, WT2 output from the weight number setting circuit 16 at the Low level, either 2-bit signals BS0 and BS after the peripheral circuits are accessed
The time until 1 is output as the ACK signals ACK0 and ACK1 is switched.

Here, regarding a series of data transfer operations performed by the microcomputer of this embodiment having such a cycle control unit 8, a case of data transfer from the peripheral circuit B to the CPU 2 (read cycle) is taken as an example. The description will be made with reference to FIG.

In the following description, the ACK signal ACK shown in FIG. 9B is the 2-bit ACK signal ACK0, ACK1 output from the cycle controller 8 of this embodiment.
It represents the logical product of In addition, the eight-circuit D flip-flop 24 in the weight number search circuit 14
The weight numbers of the peripheral circuits A to D are 2, 1, 2, respectively.
8-bit data "0010011" indicating that it is 0
0 ”is stored, and the bus widths of the peripheral circuits A to D are 32 bits, 8 bits, 16 bits, and 8 bits in the 8-circuit D flip-flop 34 in the bus width search circuit 18, respectively. 8-bit data "000100"
10 ”is stored.

First, as shown in FIG. 9B, the CPU 2
Outputs the address of the peripheral circuit B in the state S1 and outputs the address strobe signal AS in the state S2.
Also, the data strobe signal DS is output at a low level. Further, at this time, the CPU 2 causes the read / write signal R
/ W is output at a high level indicating a read cycle.

Then, peripheral circuit B recognizes that it has been accessed by the address on address bus 4 and starts preparing to output data on data bus 6. At the same time, in the cycle control unit 8, only the detection signal EXB from the access detection unit 10 becomes Lo.
It is output at w level, and only the search signal BWT1 is output at low level from the weight number search circuit 14, and
Only the search signal BBS0 is low from the bus width search circuit 18.
Output at the level. Then, of the 2-bit signals BS0 and BS1 output from the bus width setting circuit 20, only BS0 becomes low level and the wait number setting circuit 16
Of the setting signals WT0, WT1, WT2 output from, only the setting signal WT1 indicating that the number of weights is 1
When it becomes Low level, only the OR gate OR4 of the OR gates OR3 to 5 in the ACK signal generation circuit 22 is allowed to change the output. However, after that, the system clock CL
2-bit signals BS0, BS until K rises twice
Ac signal ACK output to CPU2 regardless of 1
Both 0 and ACK1 remain at High level.

Therefore, as shown in FIG. 9 (B), the CPU 2 has both the ACK signals ACK0 and ACK1 at the high level at the end of the operations of the first states S3 and S4, so that the state S3 is executed again. , S4 is repeated. Immediately after the CPU 2 finishes the second state S3, that is, when the system clock CLK rises for the second time after the state S2 is finished, the ACK signal generation circuit 22 sends the CPU 2 to the CPU 2.
Bit signals BS0 and BS1 are ACK signals ACK0 and AC
It is output as K1, and almost simultaneously with this, the peripheral circuit B finally outputs the data onto the data bus 6.

Then, the CPU 2 causes the second state S
Immediately after 4, it is detected that at least one of the ACK signals ACK0 and ACK1 is at Low level, and since ACK0 = Low and ACK1 = High, the bus width of the peripheral circuit B is 8 bits. Recognize and starts the operation of states S5 and S6,
After reading the bit data, the address strobe signal AS and the data strobe signal DS are returned to the high level, and one read cycle is completed.

As described above, in the microcomputer of this embodiment, the cycle control unit 8 sends the ACK signals ACK0 and ACK1 representing the bus width of the peripheral circuit to the CPU.
2 to control each peripheral circuit A to D
The data transfer between the CPU 2 and the CPU 2 is ensured.

As described above, in the microcomputer of this embodiment, the CPU 2 uses any of the peripheral circuits A to D.
Of the peripheral circuit accessed by the CPU 2 from the 8-circuit D flip-flop 34, the decoders 36 to 42 in the bus width search circuit 18 read the bus width of the peripheral circuit in the cycle control unit 8, and the bus width setting circuit 20 2-bit signals BS0 and BS1 representing the bus width are output. At the same time, each of the decoders 26 to 32 and the weight number setting circuit 16 in the weight number search circuit 14
The 8-circuit D flip-flop 24 reads the number of waits of the peripheral circuit accessed by the CPU 2, the ACK signal generation circuit 22 measures the wait time according to the read number of waits, and after the wait time elapses, The 2-bit signals BS0 and BS1 output from the bus width setting circuit 20 are output to the CPU 2 as acknowledge signals ACK0 and ACK1.

Therefore, according to the cycle control unit 8 of the present embodiment, the bus width setting circuit 20 commonly outputs the 2-bit signals BS0 and BS1 representing the bus widths of the peripheral circuits A to D, and the peripheral circuits. Since the ACK signal generation circuit 22 commonly measures the wait times A to D, a timer circuit such as a shift register and a logic circuit for outputting data representing the bus width are provided for each peripheral circuit as in the conventional device. Even if many peripheral circuits are connected to the CPU 2 without needing,
The circuit scale of the microcomputer can be minimized.

Further, in the cycle controller 8 of the present embodiment, the 2-bit signal BS0, which represents the bus width of the peripheral circuit,
BS1 is separately generated by the bus width search circuit 18 and the bus width setting circuit 20, and the wait time corresponding to the peripheral circuits is generated in the shift register 4 in the ACK signal generation circuit 22.
After counting by 4, the 2-bit signals BS0, BS1
Is output to the CPU2 as ACK signals ACK0 and ACK1, and a circuit portion for generating the 2-bit signals BS0 and BS1 and the 2-bit signals BS0 and BS1 are C
A circuit portion that determines the timing of output to PU2,
Since they are provided separately, the individual circuit configuration can be simplified, and the propagation delay of the signal in each circuit can be minimized, so that the CPU with a higher system clock frequency can be used. Also, it can be applied to a microcomputer provided with a peripheral circuit having a shorter access time.

Furthermore, according to the cycle control unit 8 of the present embodiment, the data stored in the peripheral circuit A (ROM) is rewritten and the stored data in the 8-circuit D flip-flops 24 and 34 are changed. Since the number of weights of each peripheral circuit A to D and the bus width can be changed, the CPU 2
This makes it very easy to replace the peripheral circuit connected to the one with a different access time or bus width.

Although the microcomputer of the above-described embodiment is one in which four peripheral circuits A to D are connected to the CPU 2, the present invention can of course be applied regardless of the number of peripheral circuits. For example, in the above embodiment, CP
When eight peripheral circuits are connected to U2, four NAND gates in the access detector 10 shown in FIG. 2 are added according to the number of peripheral circuits, and the weight number search circuit 14 shown in FIG. 8 circuit D flip-flop 24 and another 8 circuit D flip-flop 34 in the bus width search circuit 18 shown in FIG. 6 are added respectively, and accordingly, the weight number search circuit 14 and the bus width search circuit 18 are added. Just add a decoder.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer according to an embodiment.

FIG. 2 is a circuit diagram showing a circuit configuration of an access detection unit.

FIG. 3 is a block diagram showing a configuration of an ACK signal generation unit.

FIG. 4 is a circuit diagram showing a circuit configuration of a weight number search circuit.

FIG. 5 is a circuit diagram showing a circuit configuration of a weight number setting circuit.

FIG. 6 is a circuit diagram showing a circuit configuration of a bus width search circuit.

FIG. 7 is a circuit diagram showing a circuit configuration of a bus width setting circuit.

FIG. 8 is a circuit diagram showing a circuit configuration of an ACK signal generation circuit.

FIG. 9 is an explanatory diagram illustrating an outline of asynchronous data transfer.

[Explanation of symbols]

2 ... CPU A, B, C, D ... Peripheral circuit 4
... address bus 6 ... data bus 8 ... cycle control unit 10
... access detection unit 12 ... ACK signal generation unit 14
… Weight number search circuit 16… Weight number setting circuit 18
… Bus width search circuit 20… Bus width setting circuit 22
ACK signal generation circuit 24, 34 ... Eight circuit D flip-flop 26, 28, 30, 32, 36, 38, 40, 42 ... Decoder DFF1 to DFF3 ... D flip-flop 44
… Shift registers

Claims (1)

[Claims] 1. A bus which is connected to a plurality of peripheral circuits and which is used between the peripheral circuits input from the outside when accessing any peripheral circuit and transferring data to and from the peripheral circuit. It is used for a CPU that detects the end of the data transfer operation on the peripheral circuit side by a response signal indicating the width and starts the end operation of the data transfer, detects that the CPU has accessed any peripheral circuit, C for generating the response signal according to the access time of the accessed peripheral circuit
A response signal generation device for a PU, comprising wait time storage means for storing wait times respectively corresponding to access times of the peripheral circuits, and bus width storage means for storing bus widths respectively corresponding to the peripheral circuits. Detecting means for detecting that each of the peripheral circuits has been accessed by the CPU; and, when detecting that one of the peripheral circuits has been accessed by the detecting means, a bus corresponding to the accessed peripheral circuit. A bus width reading means for reading a width from the bus width storage means and outputting a response signal representing the bus width; and when a predetermined wait time is set, the wait time is clocked and after the wait time elapses, the bus The response signal generating means for outputting the response signal outputted by the width reading means to the CPU, and the one of the cycles by the detecting means. When it is detected that the circuit is accessed, the wait time corresponding to the accessed peripheral circuit is read from the wait time storage means, and the wait time setting means for setting the wait time in the response signal generating means, A response signal generation device for a CPU, comprising: