JPH0748857B2 - Orthogonal transformation device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal transform device used for high efficiency coding of images and sounds.

2. Description of the Related Art High-efficiency coding technology has become important with the digitization of images and sounds. Orthogonal transform coding is an effective means of high efficiency coding. This is to collect adjacent data, perform orthogonal transformation once, and then encode each orthogonal component. Generally, in image information and the like, adjacent data has a large correlation, and therefore, the orthogonal component representing most of alternating currents has a very small value. Therefore, by using Huffman coding or the like, the data amount can be compressed by coding the orthogonal component having a small value with a small number of bits.

Problems to be Solved by the Invention However, with such a method, the number of bits becomes very large when a large orthogonal component appears. As a result, the amount of data after compression varies greatly, making it difficult to transmit at a constant speed. On the contrary, if you try to assign a code with a code length that is not too large to the orthogonal component that takes a large value,
The overall compression rate will decrease. In view of such a point, an object of the present invention is to provide an orthogonal transformer in which the fluctuation of the data amount is small and the compression efficiency is high.

Means for Solving the Problems The present invention is directed to orthogonal transform means for dividing an image signal into blocks of a certain size and performing orthogonal transform, and orthogonal components for each block obtained by the orthogonal transform means. A weighting means for multiplying each component by a specific constant and weighting it, and a maximum absolute value of the orthogonal component representing alternating current for each block with respect to the weighted orthogonal component obtained by the weighting means, A (0) <A (1) <, ..., <A (n), (A (0), where A (0) <A (1) <, ..., <A (0)
= 0, A (i) is an arbitrary number), and when A (i−1) ≦ MAX <A (i), the divisor is A (i) /
A divisor generating means for B (B is an arbitrary number), a dividing means for dividing an orthogonal component representing all alternating currents in the block by a divisor obtained by the divisor generating means, and a divisor for encoding the divisor. An orthogonal transformer having an encoding means and outputting a codeword of a divisor obtained by the divisor encoding means, and an orthogonal component representing an alternating current and an orthogonal component representing a direct current obtained by the dividing means. Is.

Effect The present invention has the above-described configuration, and gives a large weight to an orthogonal component representing a low-order alternating current and a small weight to an orthogonal component representing a high-order alternating current, thereby visually recognizing deterioration. It is possible to compress the difficult high-order orthogonal component more greatly. Particularly, in orthogonal transform such as discrete cosine transform, the information of the boundary portion of the block is concentrated on the low-order orthogonal component, so that the block distortion can be improved by weighting the low-order orthogonal component largely.

Further, since the maximum value of the absolute value of the orthogonal component representing each alternating current becomes 0 or more and less than B by the dividing means, the fluctuation of the data amount becomes small. At the same time, if there is even one large orthogonal component, the divisor becomes large, so that each orthogonal component becomes small and the compression rate becomes high. Especially in encoding so that orthogonal components whose magnitude is 0 are not transmitted, the compression rate becomes higher because the number of orthogonal components that become 0 increases when the divisor is large.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, 1 is an orthogonal transformer, 2 is a weighting device, 3 is an absolute value converter, 4 is a maximum value detector, 5 is a divisor generator, 6 is a divisor encoder, 7 is a delay device, and 8 is a delay device. It is a divider.

The orthogonal transformer 1 shown in FIG. 1 divides the input data into blocks of a certain size and orthogonally transforms each block. Among the quadrature components obtained by the quadrature converter 1, the quadrature component representing direct current is output as it is, and the quadrature component representing alternating current is input to the weighter 2. The orthogonal component representing the alternating current weighted for each orthogonal component by the weighting unit 2 is input to the absolutizer 3 and separated into an absolute value and a sign indicating positive or negative. The quadrature component converted into the absolute value is input to the delay unit 7 and the maximum value detector 4 at the same time. The maximum value detector 4 obtains the maximum absolute value of the orthogonal component representing the alternating current for each block. Then, the maximum value is input to the divisor generator 5 to obtain the divisor. This divisor is encoded by the divisor encoder 6 and output. The absolute value of the quadrature component output from the absolute value converter 3 is delayed by the delay unit 7 until a divisor is generated, and then divided by the divisor generated by the divisor 5 by the divider 8 and output. It

Here, Table 1 shows an example of the multiplier multiplied by the weighter 2. Table 1 shows two-dimensional orthogonal components when the image information is two-dimensional 16th-order orthogonal transformation. Represents a multiplier for. That is, the upper left of Table 1 represents the multiplier for the low-order orthogonal component. Further, as it goes to the right, it represents a multiplier for a higher-order orthogonal component in the horizontal direction, and as it goes down, it represents a multiplier for a higher-order orthogonal component in the vertical direction. The weighter 2 sequentially multiplies each input orthogonal component by the multiplier shown in Table 1, and outputs the result to the absolute value digitizer 3. In Table 1, large multipliers are assigned to low-order orthogonal components, and small multipliers are assigned to high-order orthogonal components. This coarsely quantizes high-order orthogonal components whose visual deterioration is difficult to see, so that the compression rate can be improved without degrading the image quality. Furthermore, all the multipliers in Table 1 are 2
It is a power of, and all the actual multiplications can be realized by bit shifting, so that the device can be easily implemented.

Next, the divisor generator 5 will be described. A for the divisor generator
(0) (= 0) and A (0) <A (1) <, ..., A
The constant A (i) and the constant B of (n) are prepared in advance. Then, the maximum value of the orthogonal component input from the maximum value detector 4 is compared with A (0), ..., A (n), and when A (i−1) ≦ maximum value <A (i) Let the divisor be A (i) / B. By defining the divisor in this way, the sizes of the orthogonal components in the block are all B or less. Further, when the maximum value is large, the divisor becomes large, so the quantization error due to this processing also becomes large.
However, in general, the quantization error is not noticeable visually in a block having a large value of the orthogonal component. As described above, the absolute value of the quadrature component representing all alternating currents can be set to B or less without causing significant visual deterioration. This makes it possible to significantly reduce the amount of data and at the same time reduce the fluctuation in the amount of transmission.

FIG. 2 shows a more specific embodiment. In FIG. 2, 9 is a two-dimensional 16th order discrete cosine transform (DCT) converter, 10 is a switch, 11 is a shifter, 12 is an absolute value converter, 13 is a maximum detector, 14 is a shift number generator, and 15 is A delay device, 16 is a shift device, and 17 is a rounding device.

The DCT device 9 shown in FIG. 2 divides the input data into blocks of a certain size and performs DCT for each block. However, it is assumed that all orthogonal components representing the DCTed alternating current are 9 bits.
Of the orthogonal components obtained by the DCT device 9, the orthogonal component representing direct current is output as it is, and the orthogonal component representing alternating current is right-shifted (1/2 times) by 1 bit in the shifter 11. DCT device 9 and shifter
The output of 11 is adaptively switched by the switch 10 and input to the absolute value converter 12, and is separated into an absolute value (8 bits) and a sign indicating positive or negative. The maximum digit detector 13 obtains the maximum number of digits of the orthogonal component for each block from the absolute value of the orthogonal component input from the absolute value converter 12. Then, the maximum number of digits is input to the shift generator 14, where it is converted into a shift number (divisor). The absolute value of the orthogonal component output from the absolute value converter 12 is delayed by the delay unit 15 until the shift number is generated, and then the shift unit 16 shifts the right number by the shift number generated by the shift number generator 14. It is shifted (divided). Shifter 16
The absolute value of the orthogonal component shifted by is rounded to 4 bits by the rounder 17 and output. At the same time, the orthogonal component representing the direct current, the code representing the positive and negative, and the shift number are also encoded and output.

Table 2 shows an example of the weighting multiplier of this embodiment. In this embodiment, since the multipliers are only 1 and 1/2, when the switch 10 multiplies the output of DCT9,
When halving, the output of the shifter 11 is controlled to be input to the absolute value converter 12. Thus, the weighting of this embodiment is non- It is always easy to implement. Further, in the DCT, since information at the boundary of blocks is concentrated in low-order orthogonal components, block distortion is unlikely to occur even if high-order components are roughly quantized. Therefore, the compression ratio can be improved by the weighting as shown in Table 2 without degrading the image quality.

In the shift number generator 14, with respect to the maximum digit MAX input, when MAX = 8, shift number = 3 MAX = 7, shift number = 2 MAX = 6, shift number = 1 MAX ≦ When the number is 5, the shift number = 0 is output. As a result, the absolute value of the orthogonal component shifted by the shifter 16 is always 5 bits or less, and the least significant bit is rounded by the rounder 17 to be 4 bits.

In this embodiment, the absolute value of the orthogonal component representing all alternating currents is 4
Converted to less than or equal to bits. Further, since this processing consists only of detection of the number of digits and bit shift, it can be realized very easily. At this time, B = 16 and A (i) = 16 × 2 ⁱ⁻¹ . However, the method of selecting the number of shifts and the number of shifts can be set arbitrarily other than this.

As described above, two embodiments are used, but the present invention can be applied to all orthogonal transforms other than DCT.
The number of dimensions and the order can be arbitrarily selected. Further, various methods can be applied to the divisor generation and the configuration of the divider. In the embodiment, the weighting multipliers are all represented by powers of 2, but any real number can be assigned to the multiplier.
Furthermore, it is possible to compress the quantized value of the orthogonal component obtained by the present invention by various methods.

EFFECTS OF THE INVENTION The present invention can significantly compress the data amount after orthogonal transformation by the simple method as described above. In particular, since only high-order orthogonal components can be roughly quantized by weighting, the compression rate can be improved without visual deterioration. Further, since the quadrature component representing all alternating currents can be compressed to a certain constant or less, the fluctuation of the transmission amount is small. Further, the division of the present invention can be executed by bit shift, which is very simple to implement and has a great practical effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a block diagram of a second embodiment of the present invention. 1 ... Orthogonal converter, 2 ... Weighting device, 3 ... Absolute value converter, 4 ... Maximum value detector, 5 ... Divisor generator, 6 ... Divisor encoder, 8 ... Divider , 9 ... DCT device, 11,16 ... shift device.

Claims (9)

[Claims] 1. An orthogonal transform means for dividing an image signal into blocks of a certain size to perform orthogonal transform, and an orthogonal component for each block obtained by the orthogonal transform means, for each orthogonal component or for a specific orthogonal component. And a weighting means for multiplying and weighting each set by a specific constant (however, not multiplying when the multiplier is 1), and a weighted orthogonal component obtained by the weighting means. On the other hand, A (0) <A (1) where A (0) <A (1), where maximum value detecting means for obtaining the maximum value of absolute values of orthogonal components representing alternating current for each block and maximum value obtained by the maximum value detecting means are MAX <, …… <A (n), (A (0) =
0, A (i) is an arbitrary number, and when A (i-1) ≤MAX <A (i), the divisor is A (i) /
A divisor generating means for B (B is an arbitrary number), a dividing means for dividing an orthogonal component representing all alternating currents in the block by a divisor obtained by the divisor generating means, and a divisor code for encoding the divisor. And an orthogonal transform device which outputs a codeword of a divisor obtained by the divisor encoding means, an orthogonal component representing alternating current and an orthogonal component representing direct current, obtained by the dividing means. 2. The weighting means weights an orthogonal component representing a low-order AC with a large constant, and weights an orthogonal component representing a high-order AC with a small constant. The orthogonal transform device according to item 1. 3. The weighting means has a multiplication constant of 2 ⁱ (i
Is an integer), The orthogonal transform apparatus according to claim 1 or 2. 4. The orthogonal transforming device according to claim 1 or 3, wherein the weighting means multiplies only an orthogonal component representing a high-order alternating current by 1/2. 5. The orthogonal transform apparatus according to claim 1 or 3, wherein the weighting means executes multiplication by bit shift. 6. A divisor generating means is A (0) = 0, A (i) =
The orthogonal transform apparatus according to claim 1, wherein B × 2 ^i-1 (i = 1, ..., N). 7. The orthogonal transform apparatus according to claim 1 or 6, wherein the divisor generating means is B = 2 ^j . 8. The orthogonal transform apparatus according to claim 1 or 6, wherein the dividing means executes the division by bit shifting. 9. The orthogonal transform device according to claim 1, wherein the orthogonal transform means is a discrete cosine transform.