JP2506724B2 - Orthogonal transformer - Google Patents

Abstract

PURPOSE:To simply compress the quantity of data after orthogonal conversion by outputting a code work being a divisor obtained by a divisor coding means, an orthogonal component representing AC and an orthogonal component representing DC obtained by a divider means. CONSTITUTION:A divisor generator 4 forming a divisor as Ai/B (B is an optional number) in case of AO<A1<-An (AO=O and Ai is an optional number) and in the case of A(i-1)<=MAX<Ai, where MAX is a maximum value obtained by a maximum value detector 3, a divider 7 using a divisor obtained by the divisor generator 4 to divide the orthogonal component representing all AC components in the block, and a divisor coder 5 coding the divisor, are provided. Then the orthogonal component representing the AC component and the orthogonal component representing the DC component obtained by the divisor 7 and the code work of the divisor obtained by the divisor coder 5 are outputted. Thus, since the maximum value of the absolute value of the orthogonal component representing each AC is >=O and <B, the fluctuation of data quantity is decreased and the compression rate is improved.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal transformer used for high efficiency coding of images and sounds.

2. Description of the Related Art With the digitization of images and sounds, high-efficiency coding techniques have become important. Orthogonal transform coding is an effective means of high efficiency coding. This is to collect adjacent data, perform orthogonal transformation once, and then encode each orthogonal component. Generally, in image information and the like, adjacent data has a large correlation, and therefore, the orthogonal component representing most of alternating currents has a very small value. Therefore, by using Huffman coding or the like, the data amount can be compressed by coding the orthogonal component having a small value with a small number of bits.

Problems to be Solved by the Invention However, with such a method, the number of bits becomes very large when a large orthogonal component appears. As a result, the amount of data after compression varies greatly, making it difficult to transmit at a constant speed. On the contrary, if an attempt is made to allocate a code having a code length that is not too large to the orthogonal component that takes a large value, the overall compression rate will decrease. Considering this point,
SUMMARY OF THE INVENTION It is an object of the present invention to provide an orthogonal transformer having a small variation in data amount and a high compression efficiency.

Means for Solving the Problems The present invention relates to an orthogonal transforming unit that divides an image signal into blocks of a certain size and orthogonally transforms it, and an orthogonal component that represents an alternating current for each block among the orthogonal components obtained by the orthogonal transforming unit. The maximum value detecting means for obtaining the maximum value of the absolute value of the component and the maximum value obtained by the maximum value detecting means are set to MAX.
, A (0) <A (1) <, ..., <A
(N), (A (0) = 0, A (i) is an arbitrary number), and A
When (i-1) ≤ MAX <A (i), the divisor is A (i) / B
A divisor generating means (B is an arbitrary number), a divisor obtained by the divisor generating means for dividing an orthogonal component representing all alternating currents in the block, and a divisor code for encoding the divisor. An orthogonal transformer characterized in that it has an encoding means and outputs a codeword of a divisor obtained by the divisor encoding means, and an orthogonal component representing an alternating current and an orthogonal component representing a direct current obtained by the dividing means. is there.

Effect According to the present invention, the maximum value of the absolute value of the orthogonal component representing each alternating current is 0 or more and less than B due to the above-described configuration, so that the variation in the data amount is reduced. At the same time, if there is even one large orthogonal component, the divisor becomes large, so that each orthogonal component becomes small and the compression rate becomes high. In particular, in the encoding in which the orthogonal component whose magnitude is 0 is not transmitted, when the divisor is large, the orthogonal component which becomes 0 increases, so that the compression rate becomes higher.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention.
In FIG. 1, 1 is an orthogonal transformer, 2 is an absolute value converter, 3 is a maximum value detector, 4 is a divisor generator, 5 is a divisor encoder, 6 is a delay device, and 7 is a divider.

The orthogonal transformer 1 shown in FIG. 1 divides the input data into blocks of a certain size and orthogonally transforms each block.
Of the quadrature components obtained by the quadrature converter 1, the quadrature component representing a direct current is output as it is, and the quadrature component representing an alternating current is input to the absolute value converter 2 and separated into an absolute value and a sign representing positive / negative. . The quadrature component converted into the absolute value is input to the delay unit 6 and the maximum value detector 3 at the same time. The maximum value detector 3 obtains the maximum absolute value of the orthogonal component representing the alternating current for each block. Then, the maximum value is input to the divisor generator 4 to obtain the divisor. This divisor is encoded by the divisor encoder 5 and output. The absolute value of the quadrature component output from the absolute value converter 2 is delayed until the divisor is generated by the delay unit 6, and then divided by the divisor generated by the divisor 4 by the divider 7 and output. It

Here, the divisor generator 4 will be described. In the divisor generator, A (0) = 0 and A (0) <A (1) <, ..., <
A constant A (i) and a constant B of A (n) are prepared in advance. Then, the maximum value of the orthogonal component input from the maximum value detector 3 is compared with A (0), ..., A (n), and when A (i−1) ≦ maximum value <A (i) Let the divisor be A (i) / B. By defining the divisor in this way, the sizes of the orthogonal components in the block are all B or less. Further, when the maximum value is large, the divisor becomes large, so the quantization error due to this processing also becomes large.
However, in general, the quantization error is not noticeable visually in a block having a large value of the orthogonal component. As described above, the absolute value of the quadrature component representing all alternating currents can be set to B or less without causing significant visual deterioration. This makes it possible to significantly reduce the amount of data and at the same time reduce the fluctuation in the amount of transmission.

Next, a more specific embodiment will be described with reference to FIG. 8 in FIG. 2 is a discrete cosine conversion (DC
T) device, 9 is an absolute value converter, 10 is a truncation device, 11 is a maximum value detector, 12 is a shift number generator, 13 is a delay device, 14 is a shift device, and 15 is a rounding device.

The DCT unit 8 in FIG. 2 divides the input data into blocks of a certain size and performs DCT for each block. Of the quadrature components obtained by the DCT device 8, the quadrature component representing direct current is output as it is, and the quadrature component representing alternating current is input to the absolute value converter 9 and divided into an absolute value and a sign representing positive and negative. The quadrature component converted into the absolute value is input to the truncator 10, and the absolute value of the quadrature component representing all alternating currents is truncated to 8 bits. The maximum digit detector 11 obtains the maximum number of digits of the orthogonal component for each block from the absolute value of the orthogonal component input from the truncator 10. Then, the maximum number of digits is input to the shift generator 12, where it is converted into the number of shifts. The absolute value of the quadrature component output from the truncator 10 is delayed until a shift number is generated by the delay unit 13, and then the shift unit
At 14, the shift number is right-shifted by the shift number generated by the shift number generator 12. The absolute value of the orthogonal component shifted by the shifter 14 is rounded to 4 bits by the rounder 15 and output. At the same time, the orthogonal component representing the direct current, the code representing the positive and negative, and the shift number are also encoded and output.

The shift number generator 12 outputs the maximum digit MAX when MAX = 8, shift number = 3 MAX = 7, shift number = 2 MAX = 6, shift number = 1 MAX ≦ When the number is 5, the shift number = 0 is output. As a result, the absolute value of the orthogonal component shifted by the shifter 14 is always 5 bits or less, and the rounding device 15 rounds the least significant bit to 4 bits.

In the present embodiment, the absolute values of the orthogonal components representing all alternating currents are exchanged to 4 bits or less. Further, since this processing consists only of detection of the number of digits and bit shift, it can be realized very easily. At this time, B = 16 and A (i) = 16 * 2 ^i-1 . However, the method of selecting the number of shifts and the number of shifts can be set arbitrarily other than this.

As described above using two embodiments, the present invention can be used for all orthogonal exchanges other than DCT, and various methods can be applied to the divisor generation and the configuration of the divider. Further, it is possible to compress the quadrature component obtained by the present invention by various methods.

EFFECTS OF THE INVENTION The present invention can significantly compress the data amount after orthogonal transformation by the simple method as described above. Further, since the quadrature component representing all alternating currents can be compressed to a certain constant or less, the fluctuation of the transmission amount is small. Further, the division of the present invention can be executed by bit shift, which is very simple to implement and has a great practical effect.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, and FIG. 2 is a block diagram of a second embodiment of the present invention. 1 ... Orthogonal converter, 2 ... Absolute value converter, 3 ... Divisor generator, 7 ... Divider, 8 ... DCT device, 11 ... Maximum digit detector, 14 ... Shifter.

Claims (5)

(57) [Claims] 1. An orthogonal transform means for dividing an image signal into blocks of a certain size and orthogonally transforming it, and a maximum absolute value of the orthogonal component representing an alternating current for each block among the orthogonal components obtained by the orthogonal transform means. And the maximum value obtained by the maximum value detecting means
, A (0) <A (1) <, ..., <A
(N), (A (0) = 0, AA (i) is an arbitrary number), and A
When (i-1) ≤ MAX <A (i), the divisor is A (i) / B
And (B is an arbitrary number), division means for dividing the orthogonal components representing all alternating currents in the block by the divisor obtained by the divisor generation means, and divisor coding for encoding the divisor. Means for outputting the codeword of the divisor obtained by the divisor encoding means, the orthogonal component representing the alternating current and the orthogonal component representing the direct current, obtained by the dividing means. 2. A divisor generating means, A (0) = 0, A (i) =
The orthogonal transformer according to claim 1, wherein B * 2 ^i-1 (i = 1, ..., N). 3. An orthogonal transformer according to claim 1 or 2, wherein B = 2 ^j in the divisor generating means. 4. The orthogonal transformer according to claim 1 or 2, wherein the division is performed by a bit shift in the division means. 5. The orthogonal transformer according to claim 1, wherein the orthogonal transform is a discrete cosine transform in the orthogonal transform means.