JPH0746735B2 - Method for adjusting light emission intensity of light emitting diode and light emitting diode array - Google Patents
Method for adjusting light emission intensity of light emitting diode and light emitting diode arrayInfo
- Publication number
- JPH0746735B2 JPH0746735B2 JP61112970A JP11297086A JPH0746735B2 JP H0746735 B2 JPH0746735 B2 JP H0746735B2 JP 61112970 A JP61112970 A JP 61112970A JP 11297086 A JP11297086 A JP 11297086A JP H0746735 B2 JPH0746735 B2 JP H0746735B2
- Authority
- JP
- Japan
- Prior art keywords
- light emitting
- emitting diode
- electrode
- bonding
- emission intensity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
- Led Devices (AREA)
- Dot-Matrix Printers And Others (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、発光ダイオードの光出力を均一化せしめる発
光強度調整方法ならびにそのために使用される改良され
た発光ダイオードアレイに関するものである。Description: TECHNICAL FIELD The present invention relates to a light emission intensity adjusting method for making the light output of a light emitting diode uniform, and an improved light emitting diode array used therefor.
［従来の技術と問題点］ オフィスオートメーションの普及に伴い、オフィスコン
ピュータや日本語ワードプロセッサあるいは高速ファク
シミリなどのプリンタヘッドに発光ダイオードアレイが
使用されるようになり、その高速性、高印字品質、静寂
性などすぐれた特質を有することから今後ますます普及
される趨勢にある。[Conventional technology and problems] With the spread of office automation, light emitting diode arrays have come to be used in printer heads of office computers, Japanese word processors, high speed facsimiles, etc., and their high speed, high print quality, and quietness Due to its excellent characteristics, it is becoming more and more popular in the future.
しかし、このような情報表示用の発光ダイオードは、こ
れを構成するGa As P等のｐ−ｎ接合における拡散の不
均一、電極と発光面との光遮へいの不完全、あるいは発
光ダイオード特性の不均一等に起因して、発光強度にバ
ラツキの発生することは避けられず、印字ムラなど品質
悪化の大きな原因となっていた。However, such a light emitting diode for displaying information has non-uniform diffusion in the pn junction such as Ga As P, which constitutes the light emitting diode, incomplete light shielding between the electrode and the light emitting surface, or incomplete light emitting diode characteristics. It is inevitable that the emission intensity varies due to the uniformity and the like, which is a major cause of quality deterioration such as uneven printing.
すなわち、通常のモノリシック型発光ダイオードは、1m
mの中に８ドットから最大20ドットの密度を有するもの
で使用されており、これのチップ長は８〜12mm程度が通
常であるから、１チップ中には64〜240もの発光点が形
成されることになる。このような多数の発光点からの発
光強度は上記したようになかなか均一なものが得にく
く、同じ基板から造ったテップであっても第１表に示す
ような大きなバラツキを示すのが普通である。That is, a normal monolithic light emitting diode is 1 m
It is used with a density of 8 dots to a maximum of 20 dots in m, and the chip length of this is usually 8 to 12 mm, so 64 to 240 light emitting points are formed in one chip. Will be. As described above, it is difficult to obtain a uniform emission intensity from such a large number of emission points, and it is usual that even a step made from the same substrate shows a large variation as shown in Table 1. .
そこで、これを改善する目的で、発光ダイオードアレイ
チップの外部に制限抵抗を加え、電圧を下げることによ
り発光ダイオードを流れる電流をほぼ一定なものとした
り、トランジスタを使用して発光素子に所定の電流が流
れるようにする方法（例えば特開昭59−114879）などが
試みられてきた。 Therefore, for the purpose of improving this, a limiting resistor is added to the outside of the light emitting diode array chip to reduce the voltage to make the current flowing through the light emitting diode almost constant, or a transistor is used to set a predetermined current to the light emitting element. Have been attempted (for example, JP-A-59-114879).
しかし、発光ダイオードアレイを用いたプリンタの場
合、上記したようなきわめて高密度の発光点からなるも
のであり、このような発光点のそれぞれに必要とされる
所定値の抵抗を加えたり、それぞれに所定特性のトラン
ジスタを使用するように設計することは、設計を著しく
複雑とし、配線や組立工程もきわめて複雑とならざるを
得ず、結果的にかなり高価なものとなることは避けられ
なかった。However, in the case of a printer using a light emitting diode array, it is composed of extremely high-density light emitting points as described above, and a resistor having a predetermined value required for each of these light emitting points is added to each of them. Designing to use a transistor having a predetermined characteristic inevitably complicates the design, makes the wiring and the assembly process extremely complicated, and consequently becomes considerably expensive.
［発明の目的］ 本発明は、上記のような実情にかんがみてなされたもの
であり、発光ダイオードの製造過程において例えば簡単
な蒸着作業によって配設される抵抗性物質を用いて安価
に発光強度の調整を可能にする発光ダイオードの発光強
度調整方法ならびにその方法を直接実施する発光ダイオ
ードアレイを提供しようとするものである。[Object of the Invention] The present invention has been made in view of the above situation, and uses a resistive material provided by, for example, a simple vapor deposition operation in the manufacturing process of a light emitting diode to inexpensively change the emission intensity. (EN) A method for adjusting the light emission intensity of a light emitting diode that enables adjustment, and a light emitting diode array that directly implements the method.
［発明の概要］ すなわち、本発明の要旨とするところは、発光のための
電極と配線金属端子との間にそれぞれ長く伸びて介在す
る抵抗性物質及び導電体を平行に配設し、前記電極に前
記抵抗性物質を接続すると共に前記配線金属端子に前記
導電体を接続し、前記抵抗性物質上にはボンディングス
ペースが連続的に形成されており、当該抵抗性物質上の
ボンディングスペースへの前記導電体からのボンディン
グ位置を、前記電極と前記ボンディング位置によって決
まる抵抗性物質の長さにより定まる抵抗値によって選び
出し、当該選ばれた抵抗値により発光ダイオードに流れ
る電流を調整し、発光強度を調整する調整方法にあり、
またそのような調整を可能に構成し、かかる調整方法を
直接実施し得るように、発光のための電極と配線金属端
子との間にそれぞれ長く伸びて介在する抵抗性物質及び
導電体を平行に配設し、前記電極に前記抵抗性物質を接
続すると共に前記配線金属端子に前記導電体を接続し、
前記抵抗性物質上にはボンディングスペースの配設位置
が連続的に設けられており、当該抵抗性物質上のボンデ
ィングスペースと前記導電体とがボンディングワイヤに
より接続されてなる発光ダイオードアレイにあり、それ
によって、前記従来例に示した複雑化を回避し、安価に
均一な発光強度を有する発光ダイオードを入手可能とし
たものである。[Summary of the Invention] That is, the gist of the present invention resides in that a resistive material and a conductor, which extend long and are respectively interposed between an electrode for light emission and a wiring metal terminal, are arranged in parallel, and The resistive material is connected to the wiring metal terminal and the conductor is connected, a bonding space is continuously formed on the resistive material, the bonding space on the resistive material to the bonding space. The bonding position from the conductor is selected by the resistance value determined by the length of the resistive material determined by the electrode and the bonding position, and the current flowing through the light emitting diode is adjusted by the selected resistance value to adjust the emission intensity. There is an adjustment method,
Further, in order to make such adjustment possible and to directly carry out such an adjustment method, a resistive substance and a conductor, which extend long and are respectively interposed between the electrode for light emission and the wiring metal terminal, are arranged in parallel. Disposed, connecting the resistive material to the electrode and connecting the conductor to the wiring metal terminal,
A bonding space is continuously provided on the resistive material, and the bonding space on the resistive material and the conductor are connected by a bonding wire in a light emitting diode array. Thus, the light emitting diode having uniform emission intensity can be obtained at low cost while avoiding the complication as shown in the conventional example.
［実施例］ 以下に本発明の実施例を図面に基づいて説明する。Embodiments Embodiments of the present invention will be described below with reference to the drawings.
まず、本発明の比較例を第１図及び第２図により説明す
る。First, a comparative example of the present invention will be described with reference to FIGS. 1 and 2.
第１図は、本発明の比較例としてのメサ型モノリシック
発光ダイオードアレイの断面図を示すものであり、第２
図はその一部平面図を示すものである。FIG. 1 is a sectional view of a mesa type monolithic light emitting diode array as a comparative example of the present invention.
The figure shows a partial plan view thereof.
図において、１はｐ型Ga As基板、２はｐ−Ga Al As,3
はｎ−Ga Al As,4はｎ型オーミック接続層、５は電極に
電圧を印加せしめるための配線金属、６は例えば金線な
どよりなるボンディングワイヤ、７はｐ電極、８はｎ電
極であって、当該ｎ電極８は抵抗性物質（例えばシリコ
ン単体）8aと電気的に接続されている。そしてまた、９
は発光面であり、10は絶縁層である。In the figure, 1 is a p-type Ga As substrate, 2 is p-Ga Al As, 3
Is n-Ga Al As, 4 is an n-type ohmic contact layer, 5 is a wiring metal for applying a voltage to the electrodes, 6 is a bonding wire made of, for example, a gold wire, 7 is a p-electrode, and 8 is an n-electrode. Thus, the n-electrode 8 is electrically connected to the resistive material (for example, silicon simple substance) 8a. And again, 9
Is a light emitting surface, and 10 is an insulating layer.
電極８と抵抗性物質8aは一体物（この場合一体蒸着）と
して構成されているが、電極８と抵抗性物質8aは別の材
料をもってし、両者を電気的に接続状態としたものであ
ってもよい。The electrode 8 and the resistive substance 8a are configured as an integrated body (in this case, integrated vapor deposition), but the electrode 8 and the resistive substance 8a are made of different materials and are electrically connected to each other. Good.
第１および２図に示したような構成よりなり、発光面の
巾1mm,長さ8mm,発光点密度16ドット/mmをもって１チッ
プ中に128個の発光点を有する発光面９からなる発光ダ
イオードアレイを製造した。A light emitting diode having a structure as shown in FIGS. 1 and 2 and having a light emitting surface width of 1 mm, a length of 8 mm, and a light emitting point density of 16 dots / mm and having a light emitting surface 9 having 128 light emitting points in one chip. The array was manufactured.
上記発光ダイオードアレイの各ドットのｐ電極７とｎ電
極８との間に特別な電圧調整を与えることなく2,5Vの電
圧を印加した。A voltage of 2.5 V was applied between the p electrode 7 and the n electrode 8 of each dot of the above light emitting diode array without special voltage adjustment.
第２表中調整前とあるのは、その結果における各発光点
の発光強度分布についてＡ〜Ｆの６段階に区分して示し
たものである。（いずれもその強度を有するドットの数
で示してある。） なんらの電圧調整を行なわない場合、Ａグレードに該当
するものはなく、Ｂ〜Ｆの５段階の大きなバラツキから
なる発光強度分布を有することがわかった。そこで、そ
れぞれ上記５段階のグレードごとに電圧調整をするため
に、前記配線金属５と抵抗性物質8aに設けられたボンデ
ィングスペース11〜15とをそれぞれボンディングワイヤ
６をもってボンディングした。すなわちＢグレードのド
ットはボンディングスペース11に、以下Ｃグレードのド
ットは12に、Ｄグレードは13に、Ｅグレードは14に、Ｆ
グレードは15にというように金線よりなるボンディグワ
イヤ６を用いてボンディングし、そのボンディング位置
から電極８までの長さをもって抵抗調整を行ない、2,5V
の電圧を印加した。In Table 2, “Before adjustment” means that the emission intensity distribution of each emission point in the result is classified into 6 stages of A to F. (Each is shown by the number of dots having that intensity.) It was found that, when no voltage adjustment was performed, none of the grades A corresponded, and the emission intensity distribution consisted of five large variations of B to F. Therefore, in order to adjust the voltage for each of the above five grades, the wiring metal 5 and the bonding spaces 11 to 15 provided in the resistive material 8a are bonded by the bonding wires 6. That is, the dots of B grade are in the bonding space 11, the dots of C grade are 12, the D grade is 13, the E grade is 14, and the F grade is F.
The grade is 15, so that bonding is performed using a bond wire 6 made of gold wire, and the resistance is adjusted by adjusting the length from the bonding position to the electrode 8, which is 2,5V.
Was applied.
第２表において調整後とあるのは上記ボンディング後に
おける発光強度分布を示したものであり、発光強度のバ
ラツキが顕著に低減した様子がよくわかる。すなわち、
調整前の平均強度0.01295、標準偏差0.00183であったの
に対し、調整後は平均強度0.01155、標準偏差0.00030と
発光強度のバラツキの著しい低減を実現させることがで
きた。In Table 2, “after adjustment” shows the emission intensity distribution after the above-mentioned bonding, and it can be clearly seen that the variation in emission intensity is remarkably reduced. That is,
While the average intensity before adjustment was 0.01295 and the standard deviation was 0.00183, the average intensity after adjustment was 0.01155 and the standard deviation was 0.00030, which was a significant reduction in the variation in emission intensity.
しかしながら、第１図及び第２図に示した発光ダイオー
ドアレイでは、抵抗性物質8a上のボンディングスペース
11〜15は断続的にしか設けられないため、微妙な調整が
できないという問題がある。However, in the light emitting diode array shown in FIGS. 1 and 2, a bonding space on the resistive material 8a is used.
Since 11 to 15 are provided only intermittently, there is a problem that fine adjustment cannot be performed.
このような第１図及び第２図に示した発光ダイオードア
レイの問題点を解決できる発光ダイオードアレイの構造
を第３図及び第４図に示す。第３図は本発明の実施例を
示す説明平面図であり、第４図は第３図のＡ−Ａ断面図
である。FIGS. 3 and 4 show a structure of a light emitting diode array which can solve the problems of the light emitting diode array shown in FIGS. 1 and 2. FIG. 3 is an explanatory plan view showing an embodiment of the present invention, and FIG. 4 is a sectional view taken along line AA of FIG.
本実施例においては、発光面９に接続され抵抗性物質21
がボンディングスペースとともに連続的なものとして配
設され、当該抵抗性物質21に平行して電圧印加のための
導電体22が配線金属５より伸長配置されている例が示さ
れている。このように構成されていれば、ボンディング
ワイヤ６の長さはつねに一定なものを使用することが可
能となるし、抵抗値を変化せしめる場合にも、小さな抵
抗値でよい場合には第３図中Ａ側寄りでボンディング
し、大きな抵抗値が必要であれば第３図Ｚ側寄りにおい
てボンディングすればよく、しかも抵抗値は連続的に変
化せしめ得るから必要な抵抗値の微少な調整も容易に実
行できるという長所をも有するものである。In this embodiment, the resistive material 21 connected to the light emitting surface 9
Is provided as a continuous one together with the bonding space, and a conductor 22 for applying a voltage is extended from the wiring metal 5 in parallel with the resistive material 21. With such a configuration, it is possible to always use the bonding wire 6 having a constant length, and in the case of changing the resistance value as well, if a small resistance value is sufficient, FIG. Bonding on the side closer to the middle A side and bonding on the side closer to the Z side in FIG. 3 are possible if a large resistance value is required. Moreover, since the resistance value can be continuously changed, it is easy to make a fine adjustment of the necessary resistance value. It also has the advantage of being practicable.
［発明の効果］ 以上詳記した通り、本発明に係る発光強度調整方法なら
びに発光ダイオードアレイによれば、印加電圧を無段階
で調整できる制限抵抗を同一チップ上に設けることによ
り発光強度のバラツキを著しく低減せしめることが可能
となるものであり、従来例のような制御のためのIC等の
高価な素子を使用する必要がなく、経済性の面からみて
も大きな省力化が果せるものである。しかも、同一チッ
プ上に制限抵抗を設けるという本発明の発想は、従来そ
れらが別の基板上に設けられていたことと比較して、非
常にコンパクト化を可能にするということであり、各種
プリンタ、ファックス等に搭載する際のスペースメリッ
トを大きくし、結果的にそれら装置の小型化をも可能に
するという副次効果をも奏するものであって、本発明が
斯業界にもたらす効用はまことに大きいというきであ
る。[Effects of the Invention] As described in detail above, according to the light emission intensity adjusting method and the light emitting diode array of the present invention, the variation of the light emission intensity is provided by providing the limiting resistor capable of continuously adjusting the applied voltage on the same chip. It is possible to significantly reduce the cost, there is no need to use expensive elements such as ICs for control as in the conventional example, and great labor saving can be achieved from the economical point of view. In addition, the idea of the present invention that the limiting resistors are provided on the same chip is that they can be made extremely compact as compared with the case where they are conventionally provided on different substrates. In addition, it has the side effect of increasing the space advantage when it is mounted in a fax machine and the like, and as a result also enables the miniaturization of those devices, the utility of the present invention to the industry is extremely large. It is.
第１図は本発明の比較例としての発光ダイオードアレイ
を示す断面図、第２図は第１図の部分平面図、第３図は
本発明に係る発光ダイオードアレイの実施例を示す説明
的平面図、第４図は第３図のＡ−Ａ断面図である。 １……ｐ型Ga As基板、 ２……ｐ−Ga Al As、 ３……ｎ−Ga Al As、 ５……配線金属、 ６……ボンディングワイヤ、 ７……ｐ電極、 ８……ｎ電極、 8a……抵抗性物質、 ９……発光面、 10……絶縁層、 11,12,13,14,15……ボンディングスペース、 21……抵抗性物質、 22……導電体。1 is a sectional view showing a light emitting diode array as a comparative example of the present invention, FIG. 2 is a partial plan view of FIG. 1, and FIG. 3 is an explanatory plan view showing an embodiment of a light emitting diode array according to the present invention. FIG. 4 and FIG. 4 are sectional views taken along the line AA of FIG. 1 ... p-type Ga As substrate, 2 ... p-Ga Al As, 3 ... n-Ga Al As, 5 ... wiring metal, 6 ... bonding wire, 7 ... p electrode, 8 ... n electrode , 8a ... Resistive material, 9 ... Light emitting surface, 10 ... Insulating layer, 11,12,13,14,15 ... Bonding space, 21 ... Resistive material, 22 ... Conductor.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 国武 栄一 茨城県日立市日高町５丁目１番１号 日立 電線株式会社電線研究所内 (72)発明者 小石 栄三 茨城県日立市日高町５丁目１番１号 日立 電線株式会社電線研究所内 (72)発明者 倉田 一宏 茨城県日立市日高町５丁目１番１号 日立 電線株式会社電線研究所内 (56)参考文献 特開 昭59−117280（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Eiichi Kunitake 5-1-1 Hidaka-cho, Hitachi City, Hitachi, Ibaraki Prefecture Electric Cable Research Institute, Hitachi Cable, Ltd. (72) Eizo Koishi 5-chome Hidaka-cho, Hitachi City, Ibaraki Prefecture 1-1-1 Hitachi Cable Co., Ltd. Electric Cable Research Laboratory (72) Inventor Kazuhiro Kurata 5-1-1 Hidakacho, Hitachi City, Ibaraki Hitachi Cable Co., Ltd. Electric Cable Research Laboratory (56) Reference JP-A-59-117280 (JP, A)
Claims (2)
それぞれ長く伸びて介在する抵抗性物質及び導電体を平
行に配設し、前記電極に前記抵抗性物質を接続すると共
に前記配線金属端子に前記導電体を接続し、前記抵抗性
物質上にはボンディングスペースが連続的に形成されて
おり、当該抵抗性物質上のボンディングスペースへの前
記導電体からのボンディング位置を、前記電極と前記ボ
ンディング位置によって決まる抵抗性物質の長さにより
定まる抵抗値によって選び出し、当該選ばれた抵抗値に
より発光強度を調整する発光ダイオードの発光強度調整
方法。1. A resistive substance and a conductor, which extend in a long manner, are disposed in parallel between an electrode for emitting light and a wiring metal terminal, and the resistive substance is connected to the electrode and the wiring is provided. The conductor is connected to a metal terminal, and a bonding space is continuously formed on the resistive material, and the bonding position from the conductor to the bonding space on the resistive material is the electrode. A method for adjusting light emission intensity of a light emitting diode, comprising selecting a resistance value determined by the length of a resistive material determined by the bonding position, and adjusting the emission intensity by the selected resistance value.
それぞれ長く伸びて介在する抵抗性物質及び導電体を平
行に配設し、前記電極に前記抵抗性物質を接続すると共
に前記配線金属端子に前記導電体を接続し、前記抵抗性
物質上にはボンディングスペースの配線位置が連続的に
設けられており、当該抵抗性物質上のボンディングスペ
ースと前記導電体とがボンディングワイヤにより接続さ
れてなる発光ダイオードアレイ。2. A resistive substance and a conductor, which extend in a long manner, are disposed in parallel between an electrode for emitting light and a wiring metal terminal, and the resistive substance is connected to the electrode and the wiring is provided. The conductor is connected to a metal terminal, and a wiring position of a bonding space is continuously provided on the resistive material, and the bonding space on the resistive material and the conductor are connected by a bonding wire. Light emitting diode array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112970A JPH0746735B2 (en) | 1986-05-16 | 1986-05-16 | Method for adjusting light emission intensity of light emitting diode and light emitting diode array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61112970A JPH0746735B2 (en) | 1986-05-16 | 1986-05-16 | Method for adjusting light emission intensity of light emitting diode and light emitting diode array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62268170A JPS62268170A (en) | 1987-11-20 |
| JPH0746735B2 true JPH0746735B2 (en) | 1995-05-17 |
Family
ID=14600111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61112970A Expired - Lifetime JPH0746735B2 (en) | 1986-05-16 | 1986-05-16 | Method for adjusting light emission intensity of light emitting diode and light emitting diode array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0746735B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2650236B2 (en) * | 1990-01-11 | 1997-09-03 | ローム 株式会社 | Manufacturing method of LED array light source |
| JP4182727B2 (en) * | 2002-11-15 | 2008-11-19 | 富士ゼロックス株式会社 | Self-scanning light emitting element array, optical printer head, optical printer |
| JP2007080877A (en) * | 2005-09-09 | 2007-03-29 | Matsushita Electric Works Ltd | Color tone correcting method of led light source |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59117280A (en) * | 1982-12-24 | 1984-07-06 | Ricoh Co Ltd | Semiconductor light emitting device |
-
1986
- 1986-05-16 JP JP61112970A patent/JPH0746735B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62268170A (en) | 1987-11-20 |
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