JPH0745716A - Amplification type dram memory cell and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell and to contrive a high degree of integration by a method wherein the word line of the write transistor and the readout transistor, to be used for a breadth type DRAM, is commonly used. CONSTITUTION:The gate electrode of the write transistor 26 and the gate electrode of a readout transistor 30 in an amplification type DRAM memory cell are connected by a single word line 32. When the readout transistor 30 is driven, the threshold voltage of the write transistor 26 is set higher than the threshold voltage of the readout transistor 30 so that the write transistor 26 is not driven. As a result, an excellent read operation can be obtained even by the single word line 32. Accordingly, the area of the memory cell can be reduced, and a high degree of integration can be accomplished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data amplification type DRAM which has been proposed with the high integration of memory cells for DRAM.
The improvement of the memory cell for use in
The present invention relates to a memory cell for DRAM, which can realize higher integration by sharing a word line of a writing transistor and a reading transistor used for a RAM, and a manufacturing method thereof.

[0002]

2. Description of the Related Art As DRAM memory cells shrink,
It is difficult to secure the capacity of the storage capacitor. When the capacitance of the capacitor is reduced, it becomes difficult to stably read the data stored in the storage capacitor.

Therefore, as shown in FIG. 7, an amplification type DRAM memory cell having a storage capacitor 2, a writing transistor 6, an amplifying transistor 8 and a reading transistor 10 has been proposed. This DRAM
In the memory cell for writing, when writing data, the word line 12a is set to the high level, the writing transistor 6 is turned on, and the bit line b to the storage node 4 of the storage capacitor 2 is turned on.
Then, the data is accumulated.

When data is read, the word line 12b is set to a high level, the read transistor 10 is turned on, and the on / off state of the amplification transistor 8 is detected by the bit line b, whereby the storage node of the storage capacitor 2 is detected. The data stored in 4 is read. Because
This is because the amplification transistor 8 is driven on / off according to the data stored in the storage node 4.

[0005]

However, in such a conventionally proposed amplification type DRAM memory cell,
Two independent word lines 12a and 12 per memory cell
b is required, and there is a difficulty in high integration. That is, even if the amplifying transistor 8 and the reading transistor 10 are composed of thin film transistors (TFTs), the memory cell cannot be sufficiently reduced. This task is for word lines 12a, 1
Even if the laminated structure of 2b is used, it is not possible to solve the problem because the layout of the decoder becomes difficult.

The present invention has been made in view of the above circumstances, and by sharing the word lines of the write transistor and the read transistor used in the amplification type DRAM, it is possible to realize higher integration.
It is an object of the present invention to provide a memory cell for a computer and a manufacturing method thereof.

[0007]

In order to achieve the above object, a memory cell for a DRAM according to the present invention comprises:
A storage capacitor, an amplification transistor that is turned on / off in accordance with data stored in the storage node of the storage capacitor, a writing transistor connected between the storage node and a bit line, the amplification transistor, and the bit. And a read transistor connected to the line, and the write transistor and the read transistor are controlled by a single word line.

When the read transistor is driven, the threshold voltage of the write transistor is set higher than the threshold voltage of the read transistor so that the write transistor is not driven. Good read operation is possible even with lines.

Further, at the time of reading data, in order to delay the outflow of data from the storage node to the bit line via the write transistor, between the storage node and the write transistor and / or the write transistor and the bit. By connecting a resistor to the line, a good read operation is possible even with a single word line.

The resistor is a writing transistor,
It is composed of a MOS transistor formed on the surface of a semiconductor substrate, and on both sides of the gate electrode of this MOS transistor,
It is formed by forming sidewalls, performing ion implantation of impurities from above the gate electrode on which the sidewalls are formed, and forming source / drain regions with a predetermined offset amount on the side portions of the gate electrode. .

The readout transistor and / or the amplification transistor may be composed of thin film transistors. The word line comprises a writing transistor which is a MOS transistor having a gate electrode laminated on the surface of a semiconductor substrate via a gate insulating layer, and the reading transistor has a gate insulating layer formed on the gate electrode. The gate electrode can be formed by using a thin film transistor having a channel formed in a semiconductor layer which is stacked through the thin film transistor.

A method of manufacturing a memory cell for DRAM according to the present invention includes a step of forming a storage capacitor, a step of forming a writing transistor for writing data to a storage node of the storage capacitor, and a step of forming the storage capacitor. Depending on the data stored in the storage node,
The method includes a step of forming an amplification transistor that is turned off and a step of forming a reading transistor connected between the amplification transistor and a bit line, and the writing transistor is provided with a gate insulating layer on a surface of a semiconductor substrate. And a thin film transistor having a channel formed in a semiconductor layer stacked on the gate electrode via a gate insulating layer, the read transistor being a MOS transistor having a gate electrode stacked via the gate insulating layer. The gate electrode is used as a common word line for the writing transistor and the reading transistor, an insulating sidewall containing impurities is formed on a side portion of the gate electrode, and the impurities contained in the insulating sidewall are By solid phase diffusion in the semiconductor layer, a thin film transistor The source and drain regions characterized by a self-aligned manner.

In the DRAM memory cell according to the present invention,
Since the word line of the write transistor and the word line of the read transistor can be shared, the area of the memory cell can be further reduced and higher integration can be achieved. Moreover, the memory cell for DRAM of the present invention is
Since it is an amplification type, a large data signal can be obtained regardless of the capacity of the storage capacitor, and it is suitable for low voltage operation and suitable for future miniaturization. Further, according to the method for manufacturing a DRAM memory cell of the present invention, the DRAM memory cell of the present invention can be manufactured relatively easily.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Amplified DRAM memory cells according to the present invention and a method of manufacturing the same will now be described in detail with reference to the embodiments shown in the drawings. FIG. 1 shows a D according to an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of a RAM memory cell, FIG. 2 is a sectional view of an essential part of a DRAM memory cell according to an example for realizing the circuit shown in FIG. 1, and FIG. 3 is a DRAM according to another embodiment of the present invention.
4 is an equivalent circuit diagram of the memory cell for memory, FIG. 4 is a cross-sectional view of an essential part of a memory cell for DRAM according to an example for realizing the circuit shown in FIG. 3, and FIG. 6 is a cross-sectional view of the main part showing the structure of FIG. 6, and FIG. 6 is a cross-sectional view of the main part showing the steps for forming the readout transistor shown in FIG.

[Circuit Configuration of First Embodiment] First, a DRAM memory cell according to the first embodiment shown in FIG. 1 will be described. As shown in FIG. 1, the DRAM memory cell 20 of this embodiment is an amplification type DRAM memory cell having a storage capacitor 22, a writing transistor 26, an amplifying transistor 28, and a reading transistor 30.

In this embodiment, the write transistor 26 is arranged between the bit line b and the storage node 24 of the storage capacitor 22. A gate electrode of an amplification transistor 28 for data amplification is connected to the storage node 24. A bit line b is connected to one of the source / drain regions of the amplification transistor 28 via the read transistor 30. Amplification transistor 2
Terminal 34 connected to the other source / drain region of 8
Is applied with a power supply voltage Vcc. The voltage applied to this terminal 34 is not limited to the power supply voltage Vcc,
It can be ground.

However, it is preferable that the power supply voltage is Vcc. The reason is that the through current is suppressed in the amplification transistor 28, and it is not necessary to invert the signal potential at the time of rewriting after reading the data. In this embodiment, the gate electrode of the writing transistor 26 and the gate electrode of the reading transistor 30 are connected by a single word line 32. Moreover, the threshold voltage Vth of the writing transistor 26 is set higher than the threshold voltage Vth of the reading transistor 30. For example, the threshold voltage Vth of the writing transistor 26 is set to 1.2V, and the threshold voltage Vth of the reading transistor 30 is set to 0.6V. In addition, the threshold voltage Vth of the amplification transistor 28
Is set to 0.6V. Further, the power supply voltage Vcc applied to the terminal 34 is set to 2V.

Data Writing In the amplified DRAM memory cell 20 of this embodiment,
In order to write data, first, the word line 32 is boosted to about 3.5 V to drive the writing transistor 26, and the potential of the bit line b (2.0 at high level).
V, 0 V at low level)
Write to the storage node 24 via. At the same time,
The read transistor 30 is also driven, and a through current temporarily flows through the amplification transistor 28 at the time of writing low level data (0V), but when the storage node becomes low level potential (0V), the amplification transistor 28 is turned off. Therefore, normal writing is possible.

Reading of Data At the time of reading data, the bit line b is equalized to a low level potential. In response to the data read start signal, the word line 32 slowly rises from 0V to 3.5V.

When the data stored in the storage node 24 is high level data, the memory cell 20 operates as follows to read the data. (I) When the potential of the word line 32 reaches 0.6V, the read transistor 30 is driven, and the high level data (Vcc = 2.0V) applied to the terminal 34 via the amplification transistor 28. , Into the bit line b. At this time, since the writing transistor 26 is in the off state, the high level data stored in the storage node 24 hardly flows to the bit line b.

(Ii) Next, the potential of the word line 32 becomes
When the voltage exceeds 1.2 V, the writing transistor 26 is turned on, and the high level data stored in the storage node 24 flows out to the bit line b. The bit line b receives an extra charge as much as it flows into the bit line b in the above step (i), so that a sufficiently large high level data signal can be secured.

(Iii) Next, when the word line 32 completely rises to 3.5V, a sense amplifier (not shown) connected to the bit line operates to amplify the signal and pass it through the write transistor. The high level data is rewritten in the storage node 24.

In the writing process, if the word line 32 is raised in two steps, more stable data reading can be performed. (I ') That is, first, the word line 32 is changed from 0V to 1.
Start up to 0V. As a result, the read transistor 30 is driven, and the high level data (Vcc = 2.0) applied to the terminal 34 via the amplification transistor 28.
V) flows into the bit line b. Here, if this state is maintained for a certain period of time, the bit line b rises to about 0.3 V regardless of its parasitic capacitance, and a sufficient high level signal charge is secured in the bit line b. At this time, since the writing transistor 26 is in the off state, the storage node 2
The high level data stored in 4 hardly flows to the bit line b.

(Ii ') Next, the word line 32 is set to 1.0
When the voltage is raised from V to 3.5V, the writing transistor 26 is turned on, and the high level data stored in the storage node 24 flows out to the bit line b. (Iii ') Next, the sense amplifier is operated to amplify the data signal, and the high level data is rewritten to the storage node 24 via the writing transistor.

On the other hand, when the low level data is written in the storage node 24, the amplification transistor 28 is in the off state, the word line 32 rises to 3.5V,
Even if the writing transistor 26 and the reading transistor 30 are turned on, the potential of the bit line b hardly changes. Therefore, if a dummy bit line is provided in addition to the bit line b and a dummy cell whose current driving capability of the amplification transistor is about 1/2 of that of the normal memory cell 20 is connected to this dummy bit line, high level data and low level data can be obtained. In any case of level data, smooth data reading is possible.

[Specific Structure of First Embodiment] Next, an example of a specific structure of the amplification DRAM memory cell 20 shown in FIG. 1 will be described with reference to the sectional view shown in FIG. The amplification DRAM memory cell 20 shown in FIG. 2 is a so-called SOI.
Trench type D using (Silicon on Insulator) structure
It is a memory cell for RAM.

As shown in FIG. 2, in the SOI structure, the first semiconductor layer 36 made of single crystal silicon or the like is laminated on the insulating layer 34. A method for manufacturing such an SOI structure is not particularly limited, and an ion implantation method, a substrate bonding method (one silicon substrate is polished into a thin film after the silicon substrates are bonded), and the like are exemplified. it can. The insulating layer 34 is made of, for example, silicon oxide.

A gate electrode to be the word line 32 is laminated on the first semiconductor layer 36 with the first gate insulating layer 38 interposed therebetween. The first gate insulating layer 38 is made of silicon oxide or the like. The gate electrode to be the word line 32 and the source / drain region 3 formed in the first semiconductor layer 36.
The write transistor 26 is configured by the channels 9 and 41 and the channel region 37. Writing transistor 26
One source / drain region 41 is connected to the bit line b through a contact hole 56, and the other source / drain region 41 is connected to the bit line b.
The drain region 39 is connected to the storage node 24 via a contact hole formed in the insulating layer 34. These source / drain regions 39 and 41 are formed by, for example, an ion implantation method for the first semiconductor layer 36.

Storage node 24 is made of, for example, polysilicon. The storage node 24, the capacitor insulating film 25, and the plate electrode layer 27 form the storage capacitor 22 for each memory cell. Insulation film for capacitors 2
Reference numeral 5 is composed of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof. The plate electrode layer 27 is composed of, for example, a polysilicon layer.

A second gate insulating layer 40 is formed on the gate electrode forming the word line 32. A second semiconductor layer 42 made of, for example, a polysilicon layer is formed on the second gate insulating layer 40. In the second semiconductor layer 42, the channel region 44 and the source / drain regions 46 and 48 of the read transistor 30, and the channel region 50 and the source / drain regions 46 and 52 of the amplification transistor 28 are formed. The source / drain regions are formed by, for example, an ion implantation method.

One source / drain region 48 of the read transistor 30 is connected to the bit line b through the contact hole 56, and the other source / drain region 46 is one source / drain region of the amplification transistor 28. It is shared with. The other source / drain region 52 of the amplification transistor 28 is the terminal 34 shown in FIG.
Connected to.

An interlayer insulating layer 54 is stacked on the second semiconductor layer 42, and bit lines b are stacked thereon in a predetermined pattern. The interlayer insulating layer 54 is not particularly limited, and may be a silicon oxide layer, a silicon nitride layer, a PSG layer, a BP.
An SG layer, a BSG layer or the like can be used. The bit line b is not particularly limited as long as it is a conductive wiring layer, but a polysilicon layer, an aluminum layer, an aluminum alloy layer, or the like can be used.

In this embodiment, the writing transistor 2 is used.
6, the reading transistor 30 and the amplifying transistor 28 are all composed of thin film transistors (TFTs). The writing transistor 26 is a top gate type TFT, and the reading transistor 30 and the amplification transistor 28 are bottom gate type TFTs. Moreover, the writing transistor 26 and the reading transistor 30 are formed so as to sandwich the gate electrode forming the common word line 32. In addition, the amplification transistor 2
In 8, the source / drain region 39 connected to the upper part of the storage node 24 also serves as the gate electrode.

The gate electrode forming the word line 32 preferably has a polycide structure. That is, by forming the lower layer side of the word line 32 with a polysilicon layer containing impurities such as phosphorus and the upper layer side with a tungsten silicide layer, the work function difference between them is utilized to make the writing transistor 26 The threshold voltage Vth can be easily set higher than the threshold voltage Vth of the read transistor 30.

[Circuit Configuration of Second Embodiment] Next, a memory cell for an amplifying DRAM according to a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 3, the DRAM memory cell 60 of the present embodiment includes a storage capacitor 62.
And a writing transistor 66, an amplifying transistor 68, and a reading transistor 70.

In the present embodiment, the write transistor 66 is arranged between the bit line b and the storage node 64 of the storage capacitor 62. A gate electrode of an amplification transistor 68 for data amplification is connected to the storage node 64. The bit line b is connected to one of the source / drain regions of the amplification transistor 68 via the reading transistor 70. Amplification transistor 6
Terminal 74 connected to the other source / drain region of 8
Is applied with a power supply voltage Vcc. The voltage applied to this terminal 74 is not limited to the power supply voltage Vcc,
It can be ground.

However, the power supply voltage Vcc is preferable. The reason is that the through current is suppressed in the amplification transistor 68, and it is not necessary to invert the signal potential at the time of rewriting after reading the data. In this embodiment, the gate electrode of the writing transistor 66 and the gate electrode of the reading transistor 70 are connected by a single word line 72. Moreover, in this embodiment, the resistor 76 is connected between the storage node 64 and the writing transistor 66. The resistor 76 is for delaying the outflow of data from the storage node 64 to the bit line b via the write transistor 66 when reading data. The resistance value R of the resistor 76 is determined from the viewpoint of the time constant, and for example, the storage capacitor 62.
When the capacitance C is 10 fF, R × C is determined to be on the order of several megabytes, and preferably about 1 to several MΩ.

Considering only the time constant, the resistor 76 is provided between the write transistor 66 and the bit line b, as well as between the storage node 64 and the write transistor 66.
Alternatively, they may be attached to both of them. However, from the viewpoint of shifting the threshold voltage Vth of the writing transistor 66 to the high side and improving the data retention capability, the resistor 76 is provided between the storage node 64 and the writing transistor 66 as shown in FIG. It is preferable to install it between them.

Data Writing In the memory cell 60 for amplification type DRAM of this embodiment,
To write data, first, the word line 72 is boosted to about 3.5 volts to drive the writing transistor 66, and the potential of the bit line b (for example, 2.0 V at high level and 0 V at low level). ) Is written to the storage node 64 via the writing transistor 66. At the same time, the read transistor 70 is also driven, and the amplifying transistor 68 is written at the time of writing low-level data (0 V).
A through current temporarily flows through the memory cell, but when the storage node has a low level potential (0 V), the amplification transistor 68 is turned off, so that normal writing is possible.

Reading of Data At the time of reading data, the bit line b is equalized to the low level potential. If the data stored in the storage node 64 is high level data, the word line 72
Since the resistor 76 exists even when the signal is turned on, the data in the storage node 64 does not immediately flow to the bit line b via the writing transistor 66. Meanwhile, the high-level data applied to the terminal 74 flows into the bit line b via the amplification transistor 68 and the read transistor 70. The bit line b passes through the read transistor 70 and the amplification transistor 68.
Since an extra charge is received by the amount of flowing into, it is possible to secure a sufficiently large high level data signal.

Next, a sense amplifier (not shown) connected to the bit line is operated to amplify the signal and rewrite high level data to the storage node 64 via the write transistor. After the data reading is started, the high-level data stored in the storage node 64 is stored in the resistor 76.
Based on the time constant determined by, the current gradually flows out to the bit line b through the write transistor 66, but at that time, high-level data is rewritten,
There is no problem in read operation.

On the other hand, when low level data is written in the storage node 64, the amplification transistor 68 is in the off state, the word line 72 rises, and the writing transistor 66 and the reading transistor 70 are in the on state. However, the potential of the bit line b hardly changes. Therefore, if a dummy bit line is provided in addition to the bit line b and a dummy cell whose current driving capability of the amplification transistor is about 1/2 of that of the normal memory cell 60 is connected to this dummy bit line, high level data and low level data can be obtained. In any case of level data, smooth data reading is possible.

[Specific Structure of Second Embodiment] Next, an example of a specific structure of the amplification DRAM memory cell 60 shown in FIG. 3 will be described with reference to the sectional view of FIG. The amplification type DRAM memory cell 60 shown in FIG. 4 is a trench type DRAM memory cell formed on a normal semiconductor substrate 78.

As shown in FIG. 4, the amplification type DR of this embodiment
In the AM memory cell 60, on the surface of the semiconductor substrate 78,
A trench type storage capacitor 62 is formed. The storage capacitor 62 includes a storage node 64 embedded in a trench formed in a surface of a semiconductor substrate 78 in a predetermined pattern, a capacitor insulating film 63, and a plate electrode layer 6.
5 and.

As the semiconductor substrate 78, for example, a P-type single crystal silicon wafer is used, and a P ⁺ impurity diffusion layer is formed by an ion implantation method or the like in the plate electrode layer 65 portion which becomes one electrode of the capacitor. . The capacitor insulating film 63 is made of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof.

A first gate insulating layer 80 is laminated on the surface of the semiconductor substrate 78, and a gate electrode to be the word line 72 is laminated thereon. Gate electrode 72 is formed of, for example, a polysilicon layer. Gate insulating layer 80
Is made of, for example, silicon oxide.

A gate electrode to be the word line 72 and a source electrode formed in a predetermined pattern on the surface of the semiconductor substrate 78.
A write transistor 666 is formed by the drain regions 86a and 86b. Writing transistor 66
One source / drain region 86b is connected to the bit line b through the contact hole 104, and the other source / drain region 86a is connected to the storage node 64. These source / drain regions 86a and 86b are formed in a self-aligned manner by, for example, an ion implantation method on the surface of the semiconductor substrate 78 on which the word line 72 and the sidewalls 84 and 84 are formed.

A second gate insulating layer 88 is formed on the gate electrode forming the word line 72. A semiconductor layer 90 made of, for example, a polysilicon layer is formed on the second gate insulating layer 88. This semiconductor layer 90
A channel region 92 and source / drain regions 94 and 96 of the read transistor 70, and a channel region 98 and source / drain regions 96 and 100 of the amplification transistor 68 are formed therein.

One source / drain region 94 of the read transistor 70 is connected to the bit line b through the contact hole 104, and the other source / drain region 96 is one source / drain region of the amplification transistor 68. It is shared with. The other source / drain region 100 of the amplification transistor 68 is connected to the terminal 74 shown in FIG.

The interlayer insulating layer 10 is formed on the semiconductor layer 90.
2 are stacked, and the bit line b is stacked thereon in a predetermined pattern. The interlayer insulating layer 102 is not particularly limited, and is a silicon oxide layer, a silicon nitride layer, a PSG layer, a BP.
An SG layer, a BSG layer or the like can be used. The bit line b is not particularly limited as long as it is a conductive wiring layer, but a polysilicon layer, an aluminum layer, an aluminum alloy layer, or the like can be used.

In the embodiment shown in FIG. 4, the writing transistor 66 is formed by a normal MOS transistor, and the reading transistor 70 and the amplification transistor 68 are formed by bottom gate thin film transistors (TFTs). In the amplification transistor 68, the upper part of the storage node 64 serves as a gate electrode.

In this embodiment, the writing transistor 6 is used.
6 and the reading transistor 70 are formed so as to sandwich the gate electrode forming the common word line 72.
Word line 72 is formed of, for example, a polysilicon layer. In this embodiment, between the storage node 64 and the writing transistor 66, and between the writing transistor 66.
In order to form the resistors 76a and 76b between the bit line and the bit line b, the structure shown in FIG. 5 is adopted. That is, as shown in FIG. 5, insulating sidewalls 84, 84 are formed on both sides of the gate electrode (word line 72) of the writing transistor 66, and these sidewalls 8 are formed.
Ion implantation of impurities is performed from above the gate electrodes on which 4, 84 are formed to form source / drain regions 86a, 86b on the surface of the semiconductor substrate 78 with a predetermined offset amount with respect to the side portions of the gate electrodes. As a result, the resistors 76a and 76b are formed in the offset portion.

According to this structure, the resistors 76a and 76b can be easily formed by using the method of manufacturing the LDD structure transistor.
Can be formed. FIG. 6 shows a method of manufacturing the read transistor 70 in the memory cell 60 shown in FIG.

As shown in FIG. 6A, the writing transistor 66 is formed on the surface of the semiconductor substrate 78. At that time, the insulating sidewall 84 is formed of a diffusion impurity-containing thin film. For example, the insulating sidewall 84 is formed of a PSG film (phosphorus-containing SiO ₂ glass film). The sidewall can be formed by an etch back process using RIE or the like. Incidentally, the source / drain region 86 of the writing transistor 66.
The a and 86b are formed by ion implantation of impurities from above the gate electrode on which the side wall 84 is formed.

After that, as shown in FIG. 6B, a second gate insulating layer 88 is formed, a polysilicon thin film is deposited thereon, and a semiconductor layer 90 is formed by patterning. The second gate insulating layer 88 is composed of, for example, a silicon oxide thin film formed by a thermal oxidation method. After that, an annealing heat treatment is performed to diffuse impurities such as phosphorus contained in the sidewalls 84 into the semiconductor layer 90 to form the source / drain regions 94 and 96 in a self-aligned manner as shown in FIG. 6C. Can be formed.

In this embodiment, the source / drain region 9
4, 96 compared with the case of forming by ion implantation method,
Since it is not necessary to secure a mask alignment margin for the word line 72, it is possible to further reduce the size of the memory cell. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways within the scope of the present invention.

For example, in the above-described embodiments, the transistors used for the memory cells are N-type MOS transistors, but these transistors may be P-type MOS transistors. In the case of the embodiment, the ground potential is applied to the terminals 34 and 74 of the amplification transistors 28 and 68, and the potential of the bit line at the time of reading is equalized to the power supply voltage Vcc (about 2 V or less).

The specific structure for realizing the memory cell 20 shown in FIG. 1 is not limited to the embodiment shown in FIG. 2, and the memory cell transistor and the memory cell transistor are formed on a normal semiconductor substrate not utilizing the SOI structure. A storage capacitor can also be built in. Further, the type of the storage capacitor 22 is not particularly limited, and it is not limited to the trench type and may be the stack type.

Further, the specific structure for realizing the memory cell 60 shown in FIG. 2 is not limited to the embodiment shown in FIG. 4, and a memory cell transistor and a storage capacitor are formed on a semiconductor substrate having an SOI structure. It can be crowded.
Further, the type of the storage capacitor 22 is not particularly limited, and it is not limited to the trench type and may be the stack type.

Furthermore, since the capacity of the storage capacitor used in the memory cell according to the present invention may be extremely small,
A structure in which the parasitic capacitance with respect to the gate electrodes of the amplification transistors 28 and 68 is used as a storage capacitor and no special storage capacitor is formed is also conceivable.

[0061]

As described above, the DR of the present invention
According to the AM memory cell, the word line of the write transistor and the read transistor can be shared, so that the area of the memory cell can be further reduced and higher integration can be achieved. Moreover, since the DRAM memory cell of the present invention is an amplification type, it can obtain a large data signal regardless of the capacity of the storage capacitor, and is suitable for low voltage operation and suitable for future miniaturization.

Further, according to the method of manufacturing a DRAM memory cell of the present invention, the DRAM memory cell of the present invention can be manufactured relatively easily.

[Brief description of drawings]

FIG. 1 is an amplification type DRAM according to an embodiment of the present invention.
Is an equivalent circuit diagram of a memory cell for use.

FIG. 2 is a cross-sectional view of essential parts of a memory cell for amplification type DRAM according to an example for realizing the circuit shown in FIG.

FIG. 3 is an amplified DRA according to another embodiment of the present invention.
It is an equivalent circuit diagram of the memory cell for M.

FIG. 4 is a cross-sectional view of essential parts of a memory cell for amplifying DRAM according to an example for realizing the circuit shown in FIG.

5 is a cross-sectional view of essential parts showing a structure for forming a writing transistor and a resistor shown in FIG.

6A to 6C are cross-sectional views of essential parts showing steps for forming the read transistor shown in FIG.

FIG. 7 is an equivalent circuit diagram of a memory cell for amplification type DRAM according to a conventional example.

[Explanation of symbols]

 20, 60 ... Amplified DRAM memory cell 22, 62 ... Storage capacitor 24, 64 ... Storage node 26, 66 ... Write transistor 28, 68 ... Amplification transistor 30, 70 ... Amplification transistor 32, 72 ... Word line b ... Bit line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M H01L 29/78 311 C

Claims (7)

[Claims] 1. A storage capacitor, an amplification transistor that is turned on / off according to data stored in a storage node of the storage capacitor, a writing transistor connected between the storage node and a bit line, An amplification type DRAM memory cell having a read transistor connected between the amplification transistor and the bit line, wherein the write transistor and the read transistor are controlled by a single word line. 2. The amplification type DRAM memory cell according to claim 1, wherein the threshold voltage of the write transistor is set higher than the threshold voltage of the read transistor. 3. A resistor for delaying the outflow of data from the storage node to the bit line via the write transistor between the storage node and the write transistor and / or between the write transistor and the bit line. The memory cell for an amplified DRAM according to claim 1, wherein the memory cells are connected to each other. 4. The writing transistor is composed of a MOS transistor formed on the surface of a semiconductor substrate, and on both sides of a gate electrode of the MOS transistor,
Sidewalls are formed, and ion implantation of impurities is performed from above the gate electrode on which the sidewalls are formed,
4. The amplification DRAM memory cell according to claim 3, wherein the resistance is formed by forming a source / drain region with a predetermined offset amount on a side portion of the gate electrode. 5. The memory cell for DRAM according to claim 1, wherein the reading transistor and / or the amplifying transistor is composed of a thin film transistor. 6. The writing transistor is a MOS transistor having a gate electrode laminated on the surface of a semiconductor substrate via a gate insulating layer, and the reading transistor has a gate insulating layer on the gate electrode. It is a thin film transistor which has a channel formed in the semiconductor layer laminated | stacked through, Comprising: The said gate electrode corresponds to the said single word line, The memory cell for amplification type DRAMs in any one of Claims 1-5. 7. A step of forming a storage capacitor, a step of forming a writing transistor for writing data to a storage node of the storage capacitor, and, according to data stored in the storage node of the storage capacitor, The method includes a step of forming an amplifying transistor that turns on and off, and a step of forming a reading transistor connected between the amplifying transistor and a bit line. The writing transistor is gate-insulated on a surface of a semiconductor substrate. MO having a gate electrode laminated through layers
The read transistor is formed of an S-transistor, and the read transistor is formed of a thin film transistor having a channel formed in a semiconductor layer stacked over the gate electrode with a gate insulating layer interposed therebetween. And forming an insulating sidewall containing an impurity on the side of the gate electrode, which is used as a common word line for the read transistor, and solid-phase diffusing the impurity contained in the insulating sidewall into the semiconductor layer. According to the method, a source / drain region of a thin film transistor is formed in a self-aligned manner.