JPH0745643A - Semiconductor element packaging method - Google Patents

Semiconductor element packaging method

Info

Publication number
JPH0745643A
JPH0745643A JP18971393A JP18971393A JPH0745643A JP H0745643 A JPH0745643 A JP H0745643A JP 18971393 A JP18971393 A JP 18971393A JP 18971393 A JP18971393 A JP 18971393A JP H0745643 A JPH0745643 A JP H0745643A
Authority
JP
Japan
Prior art keywords
semiconductor element
substrate
projections
electrodes
jig
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18971393A
Other languages
Japanese (ja)
Other versions
JP3193198B2 (en
Inventor
Mitsuo Miyazaki
美津雄 宮崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP18971393A priority Critical patent/JP3193198B2/en
Publication of JPH0745643A publication Critical patent/JPH0745643A/en
Application granted granted Critical
Publication of JP3193198B2 publication Critical patent/JP3193198B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To simplify the manufacturing process of a semiconductor element and, at the same time, to eliminate the need for gold bumps, etc., on electrodes by forming projections on a substrate by pressing the heated projections of a jig against the substrate and forming a semiconductor element mounting area by forming electrodes on the projections. CONSTITUTION:One main surface 1a of a substrate 1 is used for mounting a semiconductor element and a jig 3 with projections 2 are brought into contact with the other main surface of the substrate 1. The jig 3 is incorporated with a heater 4 which heats the projections 3. By pressing the heated projections 2 of the jig 3 against the main surface 1a of the substrate 1, projections are formed on the surface 1a. Then molded plastic film substrate for mounting semiconductor elements is obtained by forming a semiconductor element mounting area by forming electrodes at least on the projections of the molded plastic film substrate. Thereafter, an adhesive resin is applied to the semiconductor element mounting area. After applying the resin, a semiconductor element is mounted on the film substrate by aligning the electrodes of the semiconductor element with the electrodes on the projections.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はプラスチック基板上に接
着用樹脂を介して半導体素子を搭載する半導体素子の実
装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting method in which a semiconductor element is mounted on a plastic substrate via an adhesive resin.

【0002】[0002]

【従来の技術】近年、半導体素子を搭載したデバイスが
種々開発されている。例えば、液晶モジュール、ELパ
ネル等があり、この液晶モジュールには、ガラス基板の
上に半導体素子を搭載したCOG方式として提案されて
いる。
2. Description of the Related Art In recent years, various devices equipped with semiconductor elements have been developed. For example, there are a liquid crystal module, an EL panel, and the like, and this liquid crystal module is proposed as a COG method in which a semiconductor element is mounted on a glass substrate.

【0003】また、最近、液晶モジュールに対しては軽
薄短小が要求され、これに伴ってガラス基板に代えてプ
ラスチックフィルム基板の採用も提案されている。
In recent years, light, thin, short and small liquid crystal modules have been required, and accordingly, it has been proposed to use a plastic film substrate instead of a glass substrate.

【0004】このような基板の上に半導体素子を搭載し
た構成においては、これらの基板の上の配線部と半導体
素子とをワイヤーボンディングする技術が確立されてい
るが、近年、半導体素子の電極と基板の上の配線部とを
直接接続するフェイスダウン方式も提案されている。こ
の接続には異方性導電膜、導電性ペースト、ゴムコネク
タを用いたり、更に光硬化樹脂を用いることも提案され
ている(特公平2 7180号参照)。
In the structure in which the semiconductor element is mounted on such a substrate, a technique for wire-bonding the wiring portion on the substrate and the semiconductor element has been established. A face-down method has also been proposed in which the wiring portion on the substrate is directly connected. For this connection, it has been proposed to use an anisotropic conductive film, a conductive paste, a rubber connector, or a photocurable resin (see Japanese Patent Publication No. 27180).

【0005】[0005]

【発明が解決しようとする問題点】しかしながら、プラ
スチックフィルム基板を採用したCOG方式の液晶モジ
ュールにおいては、半導体素子と基板のそれぞれの電極
を直接に接続するので、製造工程が簡略化されるが、そ
の反面、その電極に金から成るバンプ等を形成しなけれ
ばならず、これにより、その材料コストの上昇により製
造コストが高くなるという問題点があった。
However, in the COG type liquid crystal module adopting the plastic film substrate, since the respective electrodes of the semiconductor element and the substrate are directly connected, the manufacturing process is simplified. On the other hand, bumps made of gold or the like have to be formed on the electrodes, which causes a problem that the manufacturing cost increases due to the increase in the material cost.

【0006】[0006]

【問題点を解決するための手段】本発明の半導体素子の
実装方法は、下記(イ)乃至(ヘ)の工程によりプラス
チック基板の一主面上の半導体素子搭載領域に半導体素
子を固定せしめることを特徴とする。 (イ)プラスチック基板の他主面上に突起部を備えた治
具を当接する。 (ロ)その基板に対して治具を押圧しながら加熱した突
起部により基板上に突出部を成形する。 (ハ)その突出部上に電極を形成して半導体素子搭載領
域とする。 (ニ)その半導体素子搭載領域上に接着用樹脂を塗布す
る。 (ホ)突出部上の電極と半導体素子の電極とが対向する
ように位置合わせしながら接着用樹脂を介して半導体素
子を搭載する。 (ヘ)接着用樹脂を固化させることにより半導体素子を
基板上に固定せしめる。
According to the method of mounting a semiconductor element of the present invention, the semiconductor element is fixed to the semiconductor element mounting region on one main surface of the plastic substrate by the following steps (a) to (f). Is characterized by. (A) A jig having a protrusion is brought into contact with the other main surface of the plastic substrate. (B) The protrusion is formed on the substrate by the protrusion heated while pressing the jig against the substrate. (C) An electrode is formed on the protruding portion to form a semiconductor element mounting region. (D) Adhesive resin is applied to the semiconductor element mounting region. (E) The semiconductor element is mounted through the adhesive resin while aligning the electrodes on the protrusion and the electrodes of the semiconductor element so as to face each other. (F) The semiconductor element is fixed on the substrate by solidifying the adhesive resin.

【0007】[0007]

【作用】上記構成の半導体素子の実装方法によれば、プ
ラスチック基板の他主面上に突起部を備えた治具を当接
し、その基板に対して治具を押圧しながら加熱した突起
部により基板上に突出部を成形し、その突出部上に電極
を形成して半導体素子搭載領域ができ、これにより、半
導体素子と基板の電極を直接に接続するので、製造工程
が簡略化され、しかも、その電極に金から成るバンプ等
を形成する必要がなく、その結果、その材料コストの低
減や、製造工程の簡略化により製造コストが低下し、製
造歩留りが向上する。
According to the method of mounting a semiconductor element having the above structure, a jig having a protrusion is brought into contact with the other main surface of the plastic substrate, and the protrusion is heated by pressing the jig against the substrate. By forming a protrusion on the substrate and forming an electrode on the protrusion to form a semiconductor element mounting region, which directly connects the semiconductor element and the electrode of the substrate, the manufacturing process is simplified, and moreover, It is not necessary to form a bump or the like made of gold on the electrode, and as a result, the material cost is reduced and the manufacturing cost is reduced due to the simplification of the manufacturing process, and the manufacturing yield is improved.

【0008】[0008]

【実施例】以下、図1〜図7により順次本発明の半導体
素子の実装方法を詳述する。図1において、1は例えば
透明なプラスチックフィルム基板であり、COG方式の
液晶モジュールであれば、その厚みを0.1〜0.3m
mの範囲にするとよく、また、プラスチックフィルム基
板1は一般的に水分の透過率が大きいので、その表面を
エポキシ系樹脂等によりコートして、その水分の透過を
防止するのが望ましい。尚、この基板1はフィルム状で
あるが、その他にシート状、板状であってもよい。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for mounting a semiconductor device according to the present invention will be described in detail below with reference to FIGS. In FIG. 1, reference numeral 1 is, for example, a transparent plastic film substrate, and a COG type liquid crystal module has a thickness of 0.1 to 0.3 m.
The range is preferably m, and since the plastic film substrate 1 generally has a high moisture permeability, it is desirable to coat the surface thereof with an epoxy resin or the like to prevent the moisture permeation. The substrate 1 has a film shape, but may have a sheet shape or a plate shape.

【0009】この基板1の一方主面1aが半導体素子搭
載用であり、その他方主面1bに突起部2を備えた治具
3を当接した。この治具3には加熱ヒータ4が設けられ
ており、このヒータ4でもって突起部2が加熱され、そ
のような治具3の押圧により基板1の一方主面1aに突
出部5が成形された(図2参照)。この突出部5の高さ
は7〜15μmの範囲にすると電気的接続不良を減少も
しくは無くせるという点でよい。
One main surface 1a of this substrate 1 is for mounting semiconductor elements, and the other main surface 1b is in contact with a jig 3 having a projection 2. The jig 3 is provided with a heater 4, and the heater 4 heats the protrusion 2 to form a protrusion 5 on the one main surface 1 a of the substrate 1 by pressing the jig 3. (See FIG. 2). It is preferable that the height of the protruding portion 5 is in the range of 7 to 15 μm in order to reduce or eliminate poor electrical connection.

【0010】本例においては、その突出部5を最も効率
的かつ精度よく成形するために、一方主面1aの側にも
突起部2と対応する凹部を有するとともに加熱ヒータ4
aを具備する治具6を配置した。但し、治具6を用いな
いで治具3だけでも成形できる。
In this example, in order to form the protruding portion 5 most efficiently and accurately, a recess corresponding to the protruding portion 2 is provided on the one main surface 1a side as well as the heater 4.
The jig 6 provided with a was arranged. However, the jig 6 can be used for molding without using the jig 6.

【0011】次いで、その成形プラスチックフィルム基
板の少なくとも突出部5上に電極7を形成して半導体素
子搭載領域とし、半導体素子搭載用成形プラスチックフ
ィルム基板8(図3参照)とした。
Next, an electrode 7 was formed on at least the projecting portion 5 of the molded plastic film substrate to form a semiconductor element mounting region, which was used as a semiconductor element mounting molded plastic film substrate 8 (see FIG. 3).

【0012】その後に図4に示すように半導体素子搭載
領域に接着用樹脂9を塗布した(図4参照)。この樹脂
9にはエポキシ系、アクリル系、変性アクリル等からな
る光硬化性樹脂があり、その塗布方法はディスペンス
法、印刷法等を用いる。
Thereafter, as shown in FIG. 4, an adhesive resin 9 was applied to the semiconductor element mounting region (see FIG. 4). The resin 9 is a photocurable resin made of epoxy, acrylic, modified acrylic or the like, and the coating method is a dispensing method, a printing method or the like.

【0013】然る後に図5に示すように突出部5上の電
極と半導体素子10の電極とが対向するように位置合わ
せ(アライメント)しながら、接着用樹脂9を介して半
導体素子10を搭載した。
Thereafter, as shown in FIG. 5, the semiconductor element 10 is mounted via the adhesive resin 9 while aligning the electrodes on the protrusion 5 and the electrodes of the semiconductor element 10 so as to face each other. did.

【0014】次の工程においては、半導体素子10の上
面から加圧治具11でもって押圧しながら、他方主面1
bより紫外線照射し、これにより、突出部5が潰されな
がらも突出部5上の電極と半導体素子10の電極とが電
気的に導通するとともに、樹脂9の硬化により半導体素
子10が基板8上に固定された(図7参照)。
In the next step, while pressing the upper surface of the semiconductor element 10 with the pressing jig 11, the other main surface 1 is pressed.
Ultraviolet rays are irradiated from b, so that the electrodes on the protrusions 5 and the electrodes of the semiconductor element 10 are electrically connected to each other while the protrusions 5 are crushed. (See FIG. 7).

【0015】かくして、従来のワイヤーボンディングで
あれば、個別に電極接続するのに対して、上記実施例の
半導体素子の実装方法によれば、半導体素子10と基板
8の電極7を直接に接続するので、同時に電極接続して
製造工程が簡略化された。しかも、その電極に金から成
るバンプ等を形成する必要がなく、これにより、その材
料コストの低減や、製造工程の簡略化により製造コスト
が低下した。
Thus, in the case of the conventional wire bonding, the electrodes are individually connected, whereas according to the semiconductor element mounting method of the above embodiment, the semiconductor element 10 and the electrode 7 of the substrate 8 are directly connected. Therefore, the electrodes are simultaneously connected to simplify the manufacturing process. Moreover, it is not necessary to form a bump or the like made of gold on the electrode, which reduces the material cost and simplifies the manufacturing process, thereby reducing the manufacturing cost.

【0016】次に本発明の半導体素子の実装方法を図8
によりCOG方式の液晶モジュールについて説明する。
同図の液晶パネル12は、プラスチックフィルム基板1
3に半導体素子10を搭載したCOG方式液晶モジュー
ルであり、14は表示領域、15はその表示領域を駆動
するための配線領域である。この液晶パネル12を作製
するには、2枚のプラスチックフィルム基板13、16
の各一主面にITOを形成し、この表示領域14に複数
の透明電極17をライン状に配列し、これにより、この
透明電極を配線領域15にまで延在させ、その延在した
透明電極の上にNi層とAu層とを順次積層してなる配
線部18を形成した。したがって、突出部5上の電極7
は、この配線部18に相当する。
Next, a method of mounting a semiconductor device of the present invention will be described with reference to FIG.
The COG type liquid crystal module will be described below.
The liquid crystal panel 12 in the figure is a plastic film substrate 1.
3 is a COG type liquid crystal module in which the semiconductor element 10 is mounted on 3, a display area 14 and a wiring area 15 for driving the display area. To manufacture this liquid crystal panel 12, two plastic film substrates 13 and 16 are used.
ITO is formed on each one of the main surfaces, and a plurality of transparent electrodes 17 are arranged in a line in the display area 14, whereby the transparent electrodes extend to the wiring area 15 and the extended transparent electrodes A wiring portion 18 was formed by sequentially stacking a Ni layer and an Au layer on the above. Therefore, the electrode 7 on the protrusion 5 is
Corresponds to the wiring section 18.

【0017】その後、表示領域14の透明電極の上に配
向膜19を形成し、更にこの配向膜19の表面をラビン
グ処理して液晶分子の向きを所定の方向に設定するよう
にしている。このような2枚の被膜基板13、16を、
各透明電極ライン17が交差するように且つ対向するよ
うに配置して、その間に液晶20を注入して表示領域1
4と成すとともに、更にこの表示領域14の周囲をシー
ル部21でもって封止する。
After that, an alignment film 19 is formed on the transparent electrodes in the display area 14, and the surface of the alignment film 19 is rubbed to set the orientation of the liquid crystal molecules in a predetermined direction. These two coated substrates 13 and 16 are
The transparent electrode lines 17 are arranged so as to intersect and face each other, and the liquid crystal 20 is injected between them to display the display area 1.
4 and the periphery of the display area 14 is further sealed by the seal portion 21.

【0018】上記構成の液晶パネル12に半導体素子を
搭載するには、次のように行う。先ず、この液晶パネル
12を超音波洗浄し、その後に液晶配向検査を行う。こ
の液晶配向検査は偏光板を介して光を透過させることに
より行う。次に液晶パネル12の半導体素子搭載領域に
対して紫外線照射し、この領域の面に付着した有機物等
を分解除去する。これには水銀キセノンランプの主たる
発光波長のうち184nm、254nm付近の短波長が
有効である。この工程により半導体素子搭載領域のガラ
ス面の接触角が大きくなり、基板13に対する紫外線硬
化樹脂の密着性が著しく向上する。しかる後に、液晶パ
ネル12に対して、本発明に従うフェイスダウン方式の
半導体素子の実装方法を行う。
The semiconductor element is mounted on the liquid crystal panel 12 having the above structure as follows. First, the liquid crystal panel 12 is ultrasonically cleaned, and then a liquid crystal orientation inspection is performed. This liquid crystal alignment inspection is performed by transmitting light through a polarizing plate. Next, the semiconductor element mounting region of the liquid crystal panel 12 is irradiated with ultraviolet rays to decompose and remove organic substances and the like adhering to the surface of this region. For this, a short wavelength around 184 nm and 254 nm is effective among the main emission wavelengths of a mercury xenon lamp. By this step, the contact angle of the glass surface of the semiconductor element mounting region is increased, and the adhesion of the ultraviolet curable resin to the substrate 13 is significantly improved. Thereafter, the face-down type semiconductor element mounting method according to the present invention is performed on the liquid crystal panel 12.

【0019】以上の通り、本発明の半導体素子の実装方
法を採用することにより軽薄短小の要求が満たされた液
晶モジュールが低コスト且つ高い製造歩留りにより安定
して製造できた。
As described above, by adopting the semiconductor element mounting method of the present invention, a liquid crystal module satisfying the requirements of lightness, thinness, shortness and size can be stably manufactured at a low cost and a high manufacturing yield.

【0020】尚、本発明は上記実施例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲内で種々の変
更、改良等は何ら差し支えない。例えば、接着用樹脂と
して光硬化性樹脂を用いる以外に、硬化性樹脂や瞬間接
着剤等を採用してもよく、その場合には透明なプラスチ
ック基板を用いる必要がない。
The present invention is not limited to the above embodiments, and various modifications and improvements can be made without departing from the scope of the present invention. For example, instead of using a photo-curable resin as an adhesive resin, a curable resin, an instant adhesive agent, or the like may be adopted, and in that case, it is not necessary to use a transparent plastic substrate.

【0021】[0021]

【発明の効果】以上のように、本発明の半導体素子の実
装方法によれば、プラスチック基板に突起部を備えた治
具を当接し、その基板に対して治具を押圧しながら加熱
した突起部により基板上に突出部を成形し、その突出部
上に電極を形成して半導体素子搭載領域を構成してお
り、これにより、半導体素子と基板の電極を直接に接続
するので、製造工程が簡略化され、しかも、その電極に
金から成るバンプ等を形成する必要がなく、その結果、
その材料コストの低減や、製造工程の簡略化により製造
コストが低下し、製造歩留りが向上した。
As described above, according to the semiconductor element mounting method of the present invention, a jig provided with a protrusion is brought into contact with a plastic substrate, and the protrusion is heated while pressing the jig against the substrate. The protrusions are formed on the substrate by the parts, and the electrodes are formed on the protrusions to form the semiconductor element mounting region, which directly connects the electrodes of the semiconductor element and the substrate, which makes the manufacturing process easier. It is simplified, and there is no need to form bumps or the like made of gold on the electrodes, and as a result,
Due to the reduction of the material cost and the simplification of the manufacturing process, the manufacturing cost is lowered and the manufacturing yield is improved.

【0022】また、本発明の半導体素子の実装方法を液
晶モデュールに採用することにより、軽く、薄い液晶モ
ジュールが低コスト且つ高い製造歩留りにより安定して
製造できた。
By adopting the method for mounting a semiconductor element of the present invention in a liquid crystal module, a light and thin liquid crystal module can be stably manufactured at a low cost and a high manufacturing yield.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 1 is a schematic sectional view showing a step of a method for mounting a semiconductor element in an example.

【図2】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 2 is a schematic cross-sectional view showing a step in a method for mounting a semiconductor element in an example.

【図3】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 3 is a schematic cross-sectional view showing a step in the semiconductor element mounting method of the example.

【図4】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 4 is a schematic cross-sectional view showing a step in a method for mounting a semiconductor element in an example.

【図5】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 5 is a schematic sectional view showing a step of a method for mounting a semiconductor element in an example.

【図6】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 6 is a schematic cross-sectional view showing a step in a method for mounting a semiconductor element in an example.

【図7】実施例における半導体素子の実装方法の一工程
を示す断面概略図である。
FIG. 7 is a schematic cross-sectional view showing a step in a method of mounting a semiconductor element in an example.

【図8】実施例における液晶モデュール半導体素子の断
面概略図である。
FIG. 8 is a schematic cross-sectional view of a liquid crystal module semiconductor device in an example.

【符号の説明】[Explanation of symbols]

1 プラスチックフィルム基板 2 突起部 3、6 治具 5 突出部 7 電極 9 接着用樹脂 10 半導体素子 1 Plastic Film Substrate 2 Projections 3, 6 Jig 5 Projection 7 Electrode 9 Adhesive Resin 10 Semiconductor Element

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 下記(イ)乃至(ヘ)の工程によりプラ
スチック基板の一主面上の半導体素子搭載領域に半導体
素子を固定せしめることを特徴とする半導体素子の実装
方法。 (イ)プラスチック基板の他主面上に突起部を備えた治
具を当接する。 (ロ)その基板に対して治具を押圧しながら加熱した突
起部により基板の一主面上に突出部を成形する。 (ハ)その突出部上に電極を形成して半導体素子搭載領
域とする。 (ニ)その半導体素子搭載領域上に接着用樹脂を塗布す
る。 (ホ)突出部上の電極と半導体素子の電極とが対向する
ように位置合わせしながら接着用樹脂を介して半導体素
子を搭載する。 (ヘ)接着用樹脂を固化させることにより半導体素子を
基板上に固定せしめる。
1. A method for mounting a semiconductor element, comprising fixing the semiconductor element to a semiconductor element mounting region on one main surface of a plastic substrate by the following steps (a) to (f). (A) A jig having a protrusion is brought into contact with the other main surface of the plastic substrate. (B) The protrusion is formed on one main surface of the substrate by the protrusion heated while pressing the jig against the substrate. (C) An electrode is formed on the protruding portion to form a semiconductor element mounting region. (D) Adhesive resin is applied to the semiconductor element mounting region. (E) The semiconductor element is mounted through the adhesive resin while aligning the electrodes on the protrusion and the electrodes of the semiconductor element so as to face each other. (F) The semiconductor element is fixed on the substrate by solidifying the adhesive resin.
JP18971393A 1993-07-30 1993-07-30 Semiconductor element mounting method Expired - Fee Related JP3193198B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18971393A JP3193198B2 (en) 1993-07-30 1993-07-30 Semiconductor element mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18971393A JP3193198B2 (en) 1993-07-30 1993-07-30 Semiconductor element mounting method

Publications (2)

Publication Number Publication Date
JPH0745643A true JPH0745643A (en) 1995-02-14
JP3193198B2 JP3193198B2 (en) 2001-07-30

Family

ID=16245955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18971393A Expired - Fee Related JP3193198B2 (en) 1993-07-30 1993-07-30 Semiconductor element mounting method

Country Status (1)

Country Link
JP (1) JP3193198B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002011202A2 (en) * 2000-07-31 2002-02-07 Siemens Dematic Ag Method and device for producing connection substrates for electronic components
JP2004327873A (en) * 2003-04-28 2004-11-18 Asahi Glass Co Ltd Connection structure of reed electrode and flexible wiring board
JP2006013479A (en) * 2004-05-28 2006-01-12 Matsushita Electric Ind Co Ltd Bonding equipment and method
US8240539B2 (en) 2004-05-28 2012-08-14 Panasonic Corporation Joining apparatus with UV cleaning
CN108780760A (en) * 2016-03-17 2018-11-09 东京毅力科创株式会社 Using liquid carry out chip part relative to substrate calibration method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002011202A2 (en) * 2000-07-31 2002-02-07 Siemens Dematic Ag Method and device for producing connection substrates for electronic components
WO2002011202A3 (en) * 2000-07-31 2003-01-23 Siemens Dematic Ag Method and device for producing connection substrates for electronic components
JP2004327873A (en) * 2003-04-28 2004-11-18 Asahi Glass Co Ltd Connection structure of reed electrode and flexible wiring board
JP2006013479A (en) * 2004-05-28 2006-01-12 Matsushita Electric Ind Co Ltd Bonding equipment and method
JP4575839B2 (en) * 2004-05-28 2010-11-04 パナソニック株式会社 Joining apparatus and joining method
US8240539B2 (en) 2004-05-28 2012-08-14 Panasonic Corporation Joining apparatus with UV cleaning
CN108780760A (en) * 2016-03-17 2018-11-09 东京毅力科创株式会社 Using liquid carry out chip part relative to substrate calibration method

Also Published As

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