JPH0745111Y2 - Display device drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a display device, particularly a pulse memory type discharge display panel, and an AC type discharge display pulse drive circuit.

(Prior Art) The driving method described in the specification of Japanese Patent Application Laid-Open No. 57-86886 “Driving Method of Gas Discharge Display Panel” previously filed by the applicant gives a display panel having a relatively simple structure a memory function. This is a very advantageous method for obtaining a flat display with high brightness.

2 and 3 show an example of a display anode driving circuit conventionally used in a pulse memory driving method and an anode driving pulse generated by this circuit. The pulse shown in FIG. 3 is composed of two rectangular wave pulses of potential V _S and potential V _W , the former being the sustain pulse SP and the latter being the write pulse WP. The write pulse WP is necessary to selectively discharge each discharge cell corresponding to the pixel, and there are cases where the potential V _W is taken and when the potential is zero due to selection (writing) and non-selection (non-writing). .

The operation of the circuit shown in FIG. 2 will be described with reference to the time chart shown in FIG. The switch SW _S operates at the timing of the operation of the top row SW _S in FIG. 4, and the diodes D _S (D _S1 , D _S2 , ..., D
_sn ) sustain pulse SP through each display anode DA (DA
1, DA2, ... DA _n ). Switch SW _W (SW _W1 , SW _W2 ,
, SW _Wn ) operates at the timing of the operation of SW _{W in} the second line in FIG. 4, and the write pulse WP is applied to each display anode via each diode D _W (D _W1 , D _W2 , ..., D _Wn ). Apply.

The switch SW _D has two purposes. One is the sustain pulse SP due to the anode-cathode capacitance C _O of the discharge display panel.
The other is to prevent the trailing edge from blunting, and the other is to prevent the write pulse potential V _W from being fogged (clouded) on the non-write anode by the capacitance C _m between the anode and the anode. Therefore, as shown in the operation timing of SW _{D in} the 3rd row of FIG. 4, the write pulse starts immediately after the end of the sustain pulse SP.
It operates so that it overlaps WP a little, and this overlapping time τ
_O is, for example, 0.3 to 0.6 μsec. By operating in this way, after the sustain pulse SP ends,
Charge accumulated in C _O is transferred to diode D _D (D _D1 , D _D2 , ...,
D _Dn ) and each of the resistors R _D (R _D1 , R _D2 , ..., R _Dn ) are discharged quickly, and the impedance of each anode circuit is lowered at the rise of the write pulse WP (almost R _D ). This causes write pulse turbidity (crosstalk)
Is being prevented.

Further, as another method of preventing the turbidity, there is a method of lowering the output impedance of the circuit at the time of writing by setting the drive circuit of the write pulse WP to be push-pull.

(Problems to be solved by the device) According to the conventional method of the time chart shown in FIG. 4, V _{W is applied} to the drive circuit of the display anode in which writing is performed during the period τ _O.
The power consumption is ² / _RD , and the invalid power consumption becomes a non-negligible value in view of the writing frequency of the panel, and the second method complicates the configuration circuit, which makes it difficult to form an integrated circuit.

(Means for Solving the Problems) An object of the present invention is to eliminate the above-mentioned drawbacks and to make a comparatively simple improvement to the driving circuit of the conventional example, thereby reducing the ineffective power loss in an integrated circuit. It is intended to provide a drive circuit of a display device which is suitable for the realization.

That is, the drive circuit of the present invention is composed of a plurality of capacitive elements, and in a gas discharge display device having a display anode, a turbidity preventing capacitive element is connected to the display anode, and the other end of the capacitive element is connected. Applies a cloudiness prevention pulse at a timing overlapping with the leading edge of the write pulse, and a switch connected in series with a diode is attached to the display anode, and the switch is turned on at the rising edge of the cloudiness prevention pulse. It is characterized in that the opacity phenomenon due to the coupling capacitance between the plurality of elements of the write pulse does not appear in the display anode.

Embodiments The present invention will be described in detail below with reference to the accompanying drawings.

FIGS. 1 (a) and 1 (b) respectively show a circuit configuration and a drive waveform when the drive circuit according to the present invention is applied to a display anode drive circuit of a pulse memory type discharge display panel. In the circuit configuration shown in FIG. 1 (a), the same parts as those of the conventional example shown in FIG. 2 are designated by the same reference numerals, except for the turbidity prevention capacitive element C _C and the turbidity prevention pulse power supply V _CP. Is the same as that of the conventional example. The on period by the switch SW _D is not temporally superposed on the write pulse WP as shown in FIG. 1 (b). The pulse generated by the Hals power supply V _CP is the write pulse WP
Is applied to form sandwich the rising time t ₂ between time t ₁ ~t _3.

When the presence or absence of the write pulse WP is displayed in states 1 and 0, the switch SW _W2 is on in state 1 and is not affected by the pulse generated by the pulse power supply V _CP (state in FIG. 1 (b)). Part 1). In the state 0, the switch SW _W2 is off, and at this time, turbidity (crosstalk) occurs via the adjacent display anode capacitance C _m (including the capacitance of cables and the like) (Fig. 1 (b). ) State 0 part). For example, when the adjacent display anode DA1 is in state 1, the potential of the display anode DA2 rises to a certain potential V _C via the inter-display anode capacitance C _m . The display anode DA2 is charged toward the potential V _P via the turbidity-preventing capacitor C _C2 by the pulse power supply V _{CP at} time t ₁ , but the display anode DA2 is pulled back toward potential 0 at time t _3. Therefore, it is theoretically and experimentally possible that the potential on the display anode side is pulled back to a certain value determined by the capacitance C _m between the display anodes and other capacitances, resulting in the waveform DA2 as shown in FIG. 1 (b). Was also confirmed.

An equivalent circuit diagram and waveforms for this theoretical explanation are shown in FIG. The equivalent circuit diagram excludes the display anode-grounding capacitance for simplification. In FIG. 5, a waveform V _W is applied as a voltage waveform to the adjacent display anode DA1 and a voltage waveform V _CP is applied as a turbidity-preventing voltage pulse, so that the display anode capacitance C _m and the turbidity prevention capacitance C _C2 are With the display anode DA2 targeted for the middle point,
Let the voltage waveform be waveform V _DA . Then the potential V _DA after turbidity of the flat portion of the waveform V _DA from simple calculations, It turns out that If C _m = C _C , V _DA = 0.5 (V _W −V _CP ) (2) and V _W = V _CP , V _DA = 0, and the turbidity is completely removed. In this case, a whisker-like transient voltage waveform of V _W / 2 appears on the voltage waveform V _DA , but the probability of erroneous discharge occurring with such a thin voltage pulse of several 100 nsec or less is close to zero.

Fig. 1 shows an external capacitor as the turbidity prevention capacitance C _C , but when the auxiliary discharge anode SA and the display anode DA are adjacent to each other and form a capacitance between them, that capacitance is used. Therefore, the voltage waveform V _CP may be applied to the auxiliary discharge anode SA. Since the auxiliary discharge is used for priming, the discharge must be generated before the write pulse WP, and therefore the timing substantially matches the timing of the voltage waveform V _CP . Auxiliary discharge anode S
Normally, a limiting resistor is inserted in series with A, but when the voltage waveform is rounded by this, it is also necessary to insert a capacitor in parallel with the limiting resistor.

In addition, the voltage waveform V _CP is also applied to the cathode K within the range that does not cause erroneous discharge.
Can be applied, and the same effect can be obtained through the capacity between the cathode and the display anode.

FIG. 6 shows the drive circuit configuration (a) of another embodiment and the timing chart (b) thereof, but the diode D _S can be used as the turbidity prevention capacitance C _C. Switch SW
_If the timing of turning on _E is immediately after the writing pulse WP is turned on, the same effect can be produced by the charges accumulated in the diode D _S.

It is also possible to use the above-mentioned two or three methods together, and in the case of an external turbidity prevention capacitor, this capacitor C _C can be formed in the discharge panel or in the connection lead, the circuit board or the like.

Furthermore, it is also possible to use together with the method of superimposing the pulse generated by on / off of the switch SW _D on the write pulse WP in the conventional example, and in this case, the superposed portion is very small.

In the case of the present embodiment as well, since the voltage is charged and discharged in the turbidity prevention capacitor C _C , it is necessary to reduce the ineffective power loss. At this time, a pulse can be supplied through the inductance L described in the specification of "Driving Circuit of Display Device" filed by the applicant on February 20, 1986, and the power loss can be made almost zero.

(Effect of the device) By using the drive circuit of the present invention, the reactive power loss caused by superimposing the pulse generated by the on and off of the switch SW _D of the conventional example on the write pulse WP in a timing manner.
V _W ² / R _D can be made almost zero, and it is possible to effectively reduce the power consumption.

In detail, the difference between the conventional method of driving power per column and the method according to the present invention is as follows.

Here, C is the capacity of the anticathode per column of the display anode, which is 15 pF, τ _O.
＝ 0.3μ sec, T ＝ 4μ sec, C _C ＝ C _m ＝ C, V _CP ＝ V _W ＝ 70V, V _S
= 100V, R _D = 2KΩ.

Therefore, in comparison with the conventional method, it is 240 mw as a whole,
With this method, the power consumption is 90 mw, which is 1/2 to 1/3 of the power consumption not only for removing turbidity but also for the whole. Furthermore, if the circuit that supplies the pulse through the inductance is used as described above, the power in this portion can be reduced to about 1/5 of that, so that it can be reduced to 1/10 or less as a whole.

[Brief description of drawings]

FIG. 1 shows a circuit configuration (a) and waveforms (b) of each part of the drive circuit of the present invention, and FIGS. 2, 3, and 4 are a circuit configuration of a conventional drive circuit and an anode drive, respectively. Waveforms and waveforms of each part are shown. FIG. 5 shows an equivalent circuit for theoretically explaining the history of this embodiment and voltage waveforms of each part. FIG. 6 is a configuration of a drive circuit of another embodiment. 7A and 7B are timing charts of respective parts. WP ... write pulse, SP ... sustain pulse SW _S , SW _W (SW _W1 , SW _W2 , ..., SW _Wn ), SW _D ... each switch D _S (D _S1 , D _S2 , ..., D _Sn ), D _W (D _W1 , D _W2 , ..., D _Wn ),
D _D (D _D1 , D _D2 , ..., D _Dn ) ... Each diode DA (DA1, DA2, ..., DA _n ) ... Each display anode R _D (R _D1 , R _D2 , ..., R _Dn ) …… Each resistance C _C …… Opacity prevention capacitance V _CP …… Opacity prevention pulse power supply C _m …… Display Anode capacitance

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Yuho Kitada 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Technology Research Laboratories (56) Reference JP-A-60-1007094 (JP, A)

Claims (1)

[Scope of utility model registration request] 1. A gas discharge type display device comprising a plurality of capacitive elements and having a display anode, wherein a turbidity preventing capacitive element (C _C ) is connected to the display anode, and at the end, by applying a leading edge and superimposed timing turbid preventing pulses of the write pulse (v _CP), wherein the display anode diode (D _S) and the series-connected switches (SW _E) is attached, the The switch is configured to be turned on at the rising edge of the turbidity prevention pulse so that the turbidity phenomenon based on the coupling capacitance between the plurality of elements of the write pulse does not appear on the display anode. And a drive circuit of the display device.