JPH0744487A - Multi-processor system - Google Patents

Abstract

PURPOSE:To provide a multi-processor system in which plural processors are arbitrated to share a resource in common efficiently by a simple configuration additional circuit with respect to the multi-processor system using plural independent processors to make high speed processing. CONSTITUTION:The system is configured by using plural independent processor CPUi (i=1, 2), a common resource 4 shared in common by the plural processors CPUi, and an arbitration means 3 applying allocation control so as to allow one CPUi in the plural processors to access the common resource 4, and the arbitration means 3 outputs an interrupt signal 9 commanding the interruption of the access of the processor CPUi to the common resource 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system for performing high-speed processing by using a plurality of independent processors, and more particularly, to enable a plurality of processors to efficiently share resources by using an additional circuit having a simple structure. The present invention relates to a multiprocessor system capable of arbitration.

In recent years, the operating frequency of a processor such as a central processing unit (CPU) has been increased year by year. on the other hand,
Although the access speed of peripheral devices has improved, the current situation is that they have not caught up with the speed of the central processing unit.

As described above, the speed ratio between the processing speed inside the central processing unit and the access speed to the external peripheral devices tends to increase, and in a multiprocessor system having a shared resource, the shared resource of a processor having a low priority is shared. It is expected that the waiting time of a high-priority processor until the access is completed has a great influence on the throughput of the entire system, and a resource allocation control method that does not reduce the throughput of the entire system is desired.

[0004]

2. Description of the Related Art FIG. 6 shows a configuration diagram of a conventional multiprocessor system.

The multiprocessor system shown in FIG.
Two independent processors CPU1 and CPU2
Composed of two processors CPU1 and CP
U2 shares the memory 4. Further, in the configuration of the conventional example, the processor CPU 2 has a higher priority of access to the memory 4.

The arbitration circuit 3 includes a processor CPU1.
When the CPU 2 and the CPU 2 try to access the shared resource (memory 4) at the same time, the access request from the processor CPU 2 is selected and the processor CPU 1 is controlled to stand by. Regarding the processor CPU 1, the address bus 5 is connected to the memory 4 via the arbitration circuit 3, the one-way bus driver 10 and the shared address bus 14, and the data bus 6 is connected to the memory 4 via the bidirectional bus driver 11 and the shared data bus 15. , Each connected.

Similarly, regarding the processor CPU2, the address bus 7 is connected to the memory 4 via the arbitration circuit 3, the one-way bus driver 12, and the shared address bus 14, and the data bus 8 is shared by the bidirectional bus driver 13 and the shared bus. It is connected to the memory 4 via the data bus 15.

While the processor CPU1 is accessing the memory 4 which is a shared resource, the processor CPU2 having a high priority
7 shows a timing chart when there is an access request to the memory 4 of FIG.

In this conventional example, the processor CPU1 receives the access right to the memory 4 and sets the bus cycle to T1.
When the processor CPU2 having a higher priority tries to access the memory 4 from the timing of T2 during execution from the timing of T3, the timing of T3 at which the processor CPU1 with lower priority ends the bus cycle being executed It was supposed to accept the next access request only because.

Further, when the bus cycle is interrupted, the data in the interrupted bus cycle is lost. Therefore, when the bus cycle is restarted, it is necessary to re-execute the interrupted bus cycle. However, if the function for re-execution is added, the amount of hardware such as the arbitration circuit 3 becomes large, and therefore the interruption is not performed during the execution of the bus cycle. It should be noted that a processor having an input for performing a retry operation for re-executing the same bus cycle when correct data cannot be obtained due to a parity error or the like has been developed in the related art.

[0011]

As described above, in the conventional multiprocessor system, since the system configuration in which the bus cycle being executed cannot be interrupted, the overhead time for acquiring the access right becomes large, and the system There was a problem that the processing efficiency as a whole fell.

The present invention solves the above problems,
It is an object of the present invention to provide a multiprocessor system in which a plurality of processors can arbitrate so as to efficiently share resources by using an additional circuit having a simple structure.

[0013]

In order to solve the above problems, the first feature of the multiprocessor system of the present invention is that a plurality of independent processor CPUs i (i = 1, 2) are provided as shown in FIG. And the plurality of processors CP
A shared resource 4 shared by Ui, and an arbitration unit 3 for performing allocation control so that one CPUi of the plurality of processors can be accessed to the shared resource 4, the arbitration unit 3 includes at least the arbitration unit 3. One processor CPUi
To output the interrupt signal 9 instructing to interrupt the access of the processor CPUi to the shared resource 4.

A second feature of the present invention is that in the multiprocessor system according to the first aspect, the arbitration means 3 performs the allocation control according to the priority order of the processor CPUi.

The third feature of the present invention is that in the multiprocessor system according to claim 1 or 2, the processor CPUi suspends the access to the shared resource 4 suspended by the suspend signal 9. It is possible to re-execute from the state where it was put.

Further, the fourth feature of the present invention is as follows.
2 or 3, the processor CPUi is a central processing unit (CP).
U) or a bus master.

[0017]

In the multiprocessor system of the first, second, third, and fourth features of the present invention, as shown in FIG. 1, a plurality of independent processor CPUs i (i = 1, 2) have specific resources. In a resource allocation control of a multiprocessor system sharing 4
When there is a bus access request from a processor CPUj (j ≠ i) having a higher priority than the bus cycle being executed, the processor CPUi having a lower priority currently being executed.
Interrupts the bus cycle of the processor CP with a high priority
An arbitration method that preferentially performs the Uj bus cycle is adopted.

The resource allocation control performed by the arbitration means 3 outputs an interruption signal 9 for instructing at least one processor CPUi to interrupt the bus access to the shared resource 4 of the processor CPUi, and the processor CPi.
Even if the bus cycle of Ui is being executed, it is forcibly interrupted.

As described above, the additional circuit having a simple structure can reduce the overhead time of the access wait of the high-priority processor, suppress the decrease in the throughput of the multiprocessor system, and allow the plurality of processors to operate. It is possible to realize a multiprocessor system that can arbitrate so as to efficiently share resources.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a system configuration diagram of a multiprocessor system according to a first embodiment of the present invention.

The multiprocessor system of this embodiment is
Two independent processors CPU1 and CPU2
Share the memory 4. Processor CPU
1 has an input (hereinafter, referred to as “interruption input”) terminal as an input terminal for forcibly interrupting a bus cycle during execution, for continuing to repeatedly execute the same bus cycle due to a parity error or the like.

Further, in the present embodiment, the priority order of access to the memory 4 is higher in the processor CPU2 than in the processor CPU1. Processor CPU1
As for the address bus 5, the address bus 5 is connected to the memory 4 via the arbitration circuit 3 and the one-way bus driver 10 and the shared address bus 14, and the data bus 6 is connected to the memory 4 via the bidirectional bus driver 11 and the shared data bus 15. Each is connected.

Similarly, regarding the processor CPU2, the address bus 7 is connected to the memory 4 via the arbitration circuit 3 and the one-way bus driver 12 and the shared address bus 14, and the data bus 8 is shared with the bidirectional bus driver 13. It is connected to the memory 4 via the data bus 15. Further, the interruption signal 9 from the arbitration circuit 3 is connected to the interruption input of the processor CPU1.

FIG. 2 shows a circuit example of the arbitration circuit 3 of this embodiment. The address signals of the processors CPU1 and CPU2 are decoded by the decoders 105 and 107, respectively. The decoders 105 and 107 are so-called address decoders, and output signals 1 from the decoders 105 and 107 when the processors CPU1 and CPU2 try to access the memory 4, which is a shared resource, respectively.
01 and 17 are enabled.

The logic gate 109 is the processor CPU1.
Is accessing the memory 4 and the processor CP
The signal line 16 is enabled when U2 is not accessing the memory 4. The logic gate 103 is an interruption signal output circuit that enables the interruption signal 9 while the processors CPU1 and CPU2 are simultaneously accessing the memory 4.

A case where the processor CPU2 starts to access the memory 4 while the processor CPU1 is accessing the memory 4 will be described with reference to a timing chart shown in FIG.

First, only the processor CPU1 outputs the address A to the address bus with respect to the memory 4, which is a shared resource, from the timing T1 and starts the execution of the bus cycle. At this time, the one-way bus driver 10 becomes active and the address A is output to the shared address bus 14.
Next, at the timing of T2 in this bus cycle, the processor CPU2 outputs the address B to the address bus 7 to access the memory 4. In response to this, arbitration circuit 3
Outputs the interrupt signal 9 to the processor CP
U1 suspends the bus cycle being executed.

Therefore, the one-way bus driver 10 becomes inactive, the one-way bus driver 12 becomes active, and the address B is output to the shared address bus 14. That is, the processor CPU2 obtains the access right to the memory 4 and starts the access at the timing of T2.

While the processor CPU2 is accessing the memory 4, the arbitration device 3 sends a suspend signal 9 to the processor CPU1.
Continues to be output. In this embodiment, the processor CPU2
Starts data transfer from the timing of T2 '. When the processor CPU2 finishes accessing the memory 4 at the timing of T3, the arbitration circuit 3 disables the interruption signal 9.

When the suspend signal 9 is disabled, the processor CPU1 sets the suspended bus cycle to T3.
Start again from the timing of. In the example of FIG. 3, the processor CPU1 starts data transfer from the timing of T3 ′. Further, in the present embodiment, the processor CPU1 enters a stopped waiting state while suspending the bus cycle, but while suspending the bus cycle, for example, an instruction to a local memory (not shown) is given. You may make it wait while fetching or the like. The processors CPU1 and CPU2 referred to here are processors in a broad sense that include a cache memory and the like.

Next, as a second embodiment, FIG. 4 shows a system configuration diagram of a multiprocessor system when it is configured by using n processors CPU1 to CPUn. A circuit diagram of the arbitration circuit according to the second embodiment is shown in FIG.

Referring to FIG. 4, the multiprocessor system of this embodiment has a plurality of independent processor CPUs.
i (i = 1 to n), a memory 4 shared by a plurality of processors CPUi, and an address bus 5 of the processors CPUi.
-I and the one-way bus driver 10-i for controlling the direction of the address between the shared address bus 14 and the processor CP
A bidirectional bus driver 11-i for controlling the direction of data between the Ui data bus 6-i and the shared data bus 15;
In order that one of the plurality of processors, CPUi, can access the memory 4, the processor CPUj (j = 1
To n-1), and an arbitration circuit 3n for controlling allocation by issuing an interruption signal 9-j and an enable / disable signal 16-i to the one-way bus driver 10-i and the bidirectional bus driver 11-i, respectively. It is configured.

The configuration of the arbitration circuit 3n is, as shown in FIG. 5, a decoder 105-i for the processor CPUi.
And the enable / disable signal 16-i by the logical operation of the output signal line 101-i from the decoder 105-i.
To generate a logic gate 109-i and a decoder 105-
logic gates 103-i and 104- that generate the interruption signal 9-j by the logical operation of the output signal line 101-i from i.
i and.

The multiprocessor system of this embodiment is
The first embodiment including two processors CPU1 and CPU2 is expanded to include n processors CPU1 to CPUn, and the operation of each individual processor CPUi is the same as that of the first embodiment. Is the same as.

In the first and second embodiments, the terminal prepared for performing the retry operation for parity error is used as the input of the interruption signal 9, but for the purpose of the present invention, this terminal is particularly It does not have to be for retry operation.

As described above, according to the multiprocessor systems of the first and second embodiments, a plurality of processors C are provided.
When an attempt is made to access the memory 4 related to sharing of PUi (i = 1 to n), even if a certain processor CPUi is already accessing the bus, by issuing an interruption signal 9-i to the processor CPUi. , The bus cycle can be forcibly interrupted.

As a result, comparing the timing of the conventional example (FIG. 7) and the timing of the first embodiment of the present invention (FIG. 3), the first embodiment has a higher priority than the conventional example. The high processor CPU2 access can be started 3 system clocks earlier. For the above reasons, the above-described embodiment can reduce the access waiting overhead time of the high-priority processor and does not reduce the efficiency of the entire multiprocessor system.

[0039]

As described above, according to the present invention, in the resource allocation control of a multiprocessor system in which a plurality of independent processors share a specific resource, a processor with a lower priority than a bus cycle under execution. When there is a bus access request from a high-priority processor, the arbitration means issues a suspend signal to forcibly suspend the bus cycle of the currently-running low-priority processor,
Since the arbitration method that gives priority to the bus cycle of the high-priority processor is adopted, the overhead time of the access wait of the high-priority processor is reduced by the additional circuit with a simple structure, and the throughput of the entire multiprocessor system is reduced. It is possible to provide a multiprocessor system capable of suppressing the degradation of the power consumption and arbitrating so that a plurality of processors can share resources efficiently.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a multiprocessor system according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing an internal configuration example of an arbitration circuit according to the first embodiment.

FIG. 3 is a timing chart illustrating the operation of the first embodiment.

FIG. 4 is a system configuration diagram of a multiprocessor system according to a second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of an arbitration circuit according to a second embodiment.

FIG. 6 is a system configuration diagram of a conventional multiprocessor system.

FIG. 7 is a timing chart illustrating the operation of a conventional example.

[Explanation of symbols]

CPU1, CPU2 Processor 3 Arbitration circuit 4 Shared memory 5 CPU1 address bus 6 CPU1 data bus 7 CPU2 address bus 8 CPU2 data bus 9 Interrupt signal (line) 10 1-way bus driver 11 Bidirectional bus driver 12 1-way bus Driver 13 Bidirectional bus driver 14 Shared address bus 15 Shared data bus 16 CPU driver side enable / disable signal line 17 CPU2 side bus driver enable / disable signal line 105, 107 Decoder 101 Decoder 105 output Signal line 103,109 Logic gate CPU1 to CPUn processor 3n Arbitration circuit 5-i (i = 1 to n) CPUi address bus 6-i (i = 1 to n) CPUi data bus 9-i (i = 1 to 1) n-1) Suspension signal (line) 10-i (i = 1 to n) One-way bus driver for CPUi 11-i (i = 1 to n) Bidirectional bus driver for CPUi 16-i (i = 1 to n) i-th bus Driver enable / disable signal line 105-i (i = 1 to n) Decoder for CPUi 101-i (i = 1 to n) Output signal line from decoder 105-i 103-i (i = 1 to n-) 1), 104-i (i = 1 to 1
n-2) Logic gate 109-i (i = 1 to n-1) Logic gate

Claims (4)

[Claims] 1. A plurality of independent processors, a shared resource shared by the plurality of processors, and an arbitration unit that controls allocation of one of the plurality of processors so that the shared resource can be accessed. The multi-processor system, wherein the arbitration means outputs, to the at least one processor, an interruption signal instructing to interrupt access to the shared resource by the processor. 2. The multiprocessor system according to claim 1, wherein the arbitration unit performs the allocation control according to a priority order of the processors. 3. The multiprocessor system according to claim 1, wherein the processor can re-execute access to the shared resource interrupted by the interrupt signal from an interrupted state. 4. The processor is a central processing unit (CP).
U), or a bus master, The multiprocessor system according to claim 1, 2 or 3.