JPH0744398A - Information processor - Google Patents

Abstract

PURPOSE:To compretely prevent the processing amount of a normal processing program from being affected by the presence/absence of exception processing by previously coding both the executing state of the normal processing program and exception condition, preparing them at every exception processing handler, coupling them with each exception processing handler and adding it as information in a program code. CONSTITUTION:A CD-ROM drive 106 reads data from a medium (CD-ROM disk 111) of a mounted software package. In this case, the executing state of the normal processing program, for which it is necessary to select and execute each exception handler, and the exception condition are previously coded, prepared at every exception processing handler, coupled with each exception processing handler and added to data stored in this disk 111 as the information in the program code together with the normal processing program and the program of the plural exception processing handlers. Thus, processing overhead for exception processing addition in normal processing can be turned to zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programming language compiler or interpreter for realizing an exception handling mechanism, and a C program.
The present invention relates to an information processing device having a PU (Central Processing Unit).

[0002]

2. Description of the Related Art Conventionally, a processing program when an exceptional situation is detected in a computer program is separated as a program different from a normal processing program, that is, an exception handler, and means for controlling this handler. It is well known that the language and the CPU provide the program with robustness, generality, correctness, and complexity.

Among them, there are some control modes in which an exception handler is dynamically defined along with the execution of a normal processing program and the exception handler is dynamically selected and executed when the program encounters an exceptional situation. Has been proposed and implemented for the language.

As an example, the ANSI X3J16 C ++ language standardization committee has proposed try, catch and throw, and the ANSI X3J13 Common Lisp language standardization committee has also proposed a condition system as a specification.

As the implementation, C / C ++ Vers of Microsoft
ion 7.0 implements the ANSI C ++ specification as a macro using the setjmp / longjmp functions in the conventional C language library, and unlike the C ++ and Lisp languages, ParcPlace Syst
In Smalltalk Release 4 of ems, there is an example of implementing a similar exception handling mechanism by linking a block closure to the context with a handler definition method.

[0006]

However, the conventional mounting method as described above has the following drawbacks.
In other words, the method to call setjmp or a function that defines an exception handler to save the location where control is transferred at the time of exception, and to restore the control transfer location saved when the exception is detected and the exception handler is executed The execution state and the exception handler must be combined and separated, and the normal process needs to perform extra processing in preparation for exception processing that may not be executed. This extra process is not preferable as an overhead incurred in the normal process in consideration of the property that the probability that the exception process is performed is much lower than that in the normal process.

Therefore, the present invention is to solve the above-mentioned problem of overhead, and makes it possible to reduce the overhead required for a normal processing program for adding an exception processing program to zero, that is, An object of the present invention is to provide an information processing apparatus having an exception handling mechanism in which the presence or absence of exception handling does not affect the throughput of a normal processing program at all.

[0008]

In order to achieve the above object, the information processing apparatus of the present invention separates a computer program into a normal processing program and a plurality of exception handling handlers, codes them, and defines the exception handling handlers. Is performed dynamically by the execution of the normal processing program, and when the exception is detected, the exception processing handler is dynamically selected and executed based on the execution state of the normal processing program. Transfer of control from the first exception handling handler to the second exception handling handler (that is, from the first exception handling handler to the second exception handling handler more general than the first exception handling handler) Control transfer), and the process of deleting the execution control state of the exception handling handler and recovering the execution environment in which the exception handling handler is defined, The process of returning control from the external processing handler to the exception starting point, the process of exchanging parameters between the exception processing handler and the exception starting point, and the process of executing the exception processing handler in the execution environment in which the exception processing handler is defined. ,
The present invention is characterized in that it has control means for performing a process of multiple exceptions for multiplexing exception processing, and the presence or absence of an exception processing handler does not affect the processing amount of the normal processing program.

Here, in the information processing apparatus of the present invention, in order to select the exception handling handler, execution state information of the normal processing program to be selected for each exception handling handler is added to the coded program. The information is included in advance. When the exception is detected, the exception processing handler is selected and execution control is performed by comparing the execution state of the normal program when the exception is detected with the execution state information of the normal processing program added to each exception handler. To do so. Further, the control means is controlled by one stack.

In other words, in the information processing apparatus of the present invention, in order to realize the exception handling mechanism, the normal handling program and the programs of the plurality of exception handling handlers as well as the normal handling that each exception handler needs to be selected and executed. The program execution state and exception status are coded in advance and prepared for each exception handler, and combined with each exception handler to be added as information in the program code.

More specifically, the exception handling mechanism according to the present invention comprises an execution control means for holding and executing the execution state of a processing program or an exception handler, a detection means for detecting an exceptional situation, and an exception detection. By the search means that compares the execution status and exception status of the normal processing program at that time with the execution status and exception status coded and added to the exception handler and searches for and selects the exception handler to be executed from among multiple exception handlers. It will be realized.

That is, the exception handling mechanism according to the present invention is
For the exception handling form described above, which has a dynamic scope in which multiple prepared and dynamically defined exception handling handlers are dynamically selected based on the execution state of the normal processing program, The exception condition is coded as an exception code, and the exception handler corresponding to the exception code is selected and executed according to the execution state of the normal processing program when the exception is detected.

The execution state of the program represents, for example, in C language, which expression or statement of which function is being executed by which function or statement at that time, and the CPU level. From the viewpoint of the above, the contents of the stack and the contents of the program counter (PC) at that time are shown.
The exception handler programmed according to the above-described form becomes valid or invalid as the normal processing program is executed.

[0014]

According to the present invention, along with the normal processing program and the programs of a plurality of exception processing handlers, the execution states and exception statuses of the normal processing programs that need to be selected and executed by each exception processing handler are coded in advance. It is prepared for each exception handling handler and is combined with each exception handling handler and added as information in the program code. When an exception is detected, the normal program execution state at the time of exception detection and each exception handling handler are added. By selecting the exception processing handler by comparing it with the added execution state information of the normal processing program and controlling the execution, the presence or absence of the exception processing handler does not affect the processing amount of the normal processing program.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a schematic configuration of the information processing apparatus of the present invention.

The information processing apparatus according to the embodiment of the present invention separates a computer program into a normal processing program and a plurality of exception processing handlers, codes them, and dynamically defines the exception processing handler by executing the normal processing program. When an exception is detected, the CPU 100, which is control means shown in FIG. 1, performs a control to dynamically select and execute the exception handler based on the execution state of the normal processing program. Transfer of control from the first exception handling handler to the second exception handling handler according to the rule (ie, for example, from the first exception handling handler to the second exception handling handler more general than the first exception handling handler) Process), deletion of the execution control state of the exception handler and restoration of the execution environment that defines the exception handler. Process, process of returning control from exception handler to exception start point, process of exchanging parameters between exception handler and exception start point, execution of the exception handler in the execution environment in which the exception handler is defined And the process of multiple exceptions for multiplexing exception processing, and the presence or absence of an exception processing handler does not affect the processing amount of the normal processing program.

First, prior to a detailed description of the configuration of FIG. 1, a method of implementing an exception handling mechanism in the information processing apparatus of this embodiment will be described. The exception handling mechanism in the apparatus of the embodiment of the present invention is realized as a virtual CPU instruction and an exception sequence for exception handling in the architecture of the virtual CPU, and its details will be described. In the following description, for the purpose of understanding only the present invention, in order to avoid unnecessary complexity, the functions of the CPU that are considered to be necessarily possessed by an ordinary general-purpose CPU and the method of implementing function calls, etc. Is not described in detail.

2 and 3 show registers in the virtual CPU (corresponding to the virtual CPU memory storage area 103 of the RAM 130 in FIG. 1) and show a programming model.

The word size of this virtual CPU is 32 bits. As shown in FIGS. 2 and 3, the virtual CPU is 1
Has a stack 7 and a stack pointer (SP) 1,
It has a program counter (PC) 2 that points to the instructions of the program being executed. Also, this virtual CPU
Supports function definition and call, and has a frame pointer (FP) 4 on the stack to indicate the call state of the function and the storage location of the local variable. It also has a function word frame pointer (WP) 3 that points to the address of the function currently being executed. The exception state frame pointer (ES) 5 and the exception argument frame pointer (EP) 6 respectively point to the storage location of the exception state and the exception argument when a stack frame for exception processing is placed on the stack.

Next, the data structure of the function will be described with reference to FIGS. The function word frame 8 is shown in FIG.
5, a function instruction frame 9 (for example, having N execution blocks with handlers) is shown, and FIG. 6 shows an exception handler table 12. Extbl of the extble field 19 of the function word frame 8 of FIG. 4 is the word offset value [I] of the field where the exception handler table address is stored, locals is the total number of function arguments and local variables, and lvars is The number of local variables in the function.

The defined function is placed in the memory in the structure as shown in FIGS. 4 to 6, and when the function is referred to, it is referred to by the address of the function word frame 8 in FIG. In the word frame 8 of the function shown in FIG. 4, constants in units of words referred to by the function are arranged side by side, and in the function instruction frame 9 of FIG. 5, a virtual CP coded in byte units.
The instruction sequence (instruction) of the function by the U instruction is arranged.

The function word frame 8 of the function being executed is
The WP register (function word frame pointer) 3 in FIG. 2 is always pointed to, and the instruction being executed is pointed to in the PC register (program counter) 2 in FIG.

The part that performs exception processing is composed of two instruction blocks, that is, an execution block 10 and an exception handler block 11 shown in FIG. Instructions in the execution block are placed at consecutive addresses. When an exception is detected while executing the instruction of the execution block, the corresponding exception handler block is activated. The exception handler block and execution block are always in the same function.

One execution block always corresponds to 1
Since it has one exception handler block, the two are collectively called a block with exception handler. A function can have multiple blocks with exception handlers. A function having a block with an exception handler always has one exception handler table 12 shown in FIG. The entry 13 of the exception handler table includes the address ranges 14 and 15 in which the instructions of the execution block are placed, the corresponding start address 17 of the exception handler block, and the exception code of the exception to be processed (exception code that can be processed) 16. Composed of. When one function has a plurality of blocks with exception handlers, a plurality of handler table entries 13 are arranged.

The address of the exception handler table is set to a word at an arbitrary offset [I] 18 in the function word frame 8, and the 16th to 23rd bits from the bottom of the 0th word of the function word frame 8 are set. The offset value [I] of the word in which the table address is set is set in the bit (extbl field) 19. Also, in a function that does not have a block with an exception handler,
The extble field 19 is set to zero.

Blocks with exception handlers can be nested. It is possible to nest within a single function, or by executing a call to another function while executing a block with an exception handler and executing the block with an exception handler in the called function. 1
Even when nesting within one function, multiple handler entries are retained in the exception handler table, and the entries are arranged in order from the inner nest to the outer nest.

The structure of the stack frame 20 when a function is called is as shown in FIG.
er WP, Caller PC, Caller FP, etc.

As shown in FIG. 8, the structure of the stack frame 21 created when an exception is detected and an exception sequence is activated is composed of an exception argument frame and an exception status frame. Is an exception argument.Initiator ES, Init
iator EP, Initiator WP, Initiator PC, Initiator F
It consists of P, Catcher WP, Catcher PC, Catcher FP, reserved (unused), handler entry index, and exception code.

Further, the following four instructions are prepared as instructions for exception processing in the virtual CPU.

1) Raise Exception 2) Continue Exception 3) Return Exception 4) Unwind Stack

The exception sequence may be activated by the Raise Exception instruction, or may be activated by the virtual CPU detecting the exception inside the CPU during normal instruction execution. In both cases, the operation of the exception processing part is performed. Since they are the same, the startup with RaiseException is explained here as an example.

Of the four instructions shown above, 1) is excluded
Instructions 2), 3), and 4) are instructions that can be executed only within the exception handler, and 1) are instructions that can be executed by both the normal processing program and the exception handler.

9 and 14 show examples of stack snapshots at some points in the exception sequence. In addition, regarding FIG. 9, in order to make the figure easy to see, this FIG. 9 is divided into four by dashed lines in the figure, and each is enlarged and shown in FIGS. In addition, similarly, in FIG. 14 as well, in order to make the drawing easy to see, FIG. 14 is divided into four by dashed lines in the drawing, and each is enlarged and shown in FIGS.

The detailed operation of each exception handling instruction and exception sequence will be described below with reference to the stack snapshot examples of FIGS. 9 and 14 and the flowcharts of FIGS.

FIG. 19 shows a sequence flow of a program for starting an exception. First, in step S17, an exception argument that is a parameter to the exception handler is pushed onto the stack, and in step S18, an exception code for identifying the type and reason of the exception is pushed onto the stack. And
In step S19, the Raise Exception instruction is executed. The state of the stack and the point position of the register at this point are shown by P1 in FIGS. 9 and 14.

FIG. 20 shows a flowchart of the operation of the virtual CPU when the Raise Exception instruction is executed. In FIG. 20, when the execution of the Raise Exception instruction is started, first, in step S1, the virtual CPU
Pushes the exception stack frame onto the stack and returns E
The S register (exception state frame pointer 5) is set to point to the exception state frame and the EP register (exception argument frame pointer 6) is set to point to the exception argument frame. At this stage, Initiator ES, Initiator EP, Initiator FP, Initiator in the frame
Raise Excepti in the field of ator PC, Initiator WP
The contents of the register at the time of execution of on are saved and the settings are made.
The contents are not set in Catcher FP, Catcher PC, and Catcher WP, and only that area is secured in the frame. Further, the WP, PC, and FP registers (function word frame pointer 3, program counter 2, frame pointer 4) at this time point show the execution state of the function at the time point when the Raise Exception instruction is executed.

After that, the virtual CPU proceeds to step S2. In step S2A of this step S2, WP
When the function pointed by (function word frame pointer 3) has an exception handler table (Ye
In step s), the process proceeds to step S2B. In this step S2B, whether the contents of the PC register (program counter 2) are within the address range of the execution block, and the exception code is an exception code that can be processed,
Alternatively, the entry of an exception handler having an exception code that can accept the processing of zero is searched in order from the top of the exception handler table. Then, it progresses to step S2C.

In step S2A, the function pointed by WP (function word frame pointer 3) does not have an exception handler table (No).
Alternatively, if no entry is found even after searching the table in step S2C after step S2B (No), the process proceeds to step S3. Virtual CPU
In this step S3, the execution state of the virtual CPU stored in the stack for the function that called the currently executing function to return from the function is accessed from the function stack frame based on the FP register (frame pointer 4). Then, after the WP, PC, and FP registers (function word frame pointer 3, program counter 2, frame pointer 4) are restored, the process returns to step S2 to repeat the handler search. Although the flow does not show the operation when there is no caller as a result of repeating the search by tracing the call chain of the function, the virtual CPU in that case is in a fatal error state.

If a handler entry satisfying the conditions is found by searching the exception handler table in step S2C (Yes), the process proceeds to step S4. The virtual CPU determines WP, P at the time when the function having the handler is executed in step S4.
Save the C and FP registers (function word frame pointer 3, program counter 2 and frame pointer 4) in the fields of Catcher WP, Catcher PC and Catcher FP of the exception status frame and set the index of the found entry on the table. Similarly, it is set to the handler entry index of the exception status frame.

Then, in step S5, the handler block start address of the handler entry is referenced and set in the PC register (program counter 2) in step S5, and the execution of the Raise Exception instruction ends. The state of the stack and the point position of the register at this point are shown by P2 in FIGS. 9 and 14. After that, sequential execution is started from the virtual CPU instruction at the head of the handler block pointed to by the PC (program counter 2).

Note that ^* XX in the flowchart of FIG.
Represents the contents of the memory pointed to by XX, X
X. YY represents the contents of the field YY of the memory XX.

FIG. 21 shows a processing sequence flow in the exception handler block. In FIG. 21, step S21 is the main body of processing in the exception handler.
Here, the exception handler block is executed in the same context as the function, so the arguments and local variables of that function can be accessed while retaining the contents at the time of exception activation, and other EP and ES registers (exception argument frame pointer 6 It is also possible to refer to the exception argument and exception state frame based on the exception state frame pointer 5). After that, to finish the processing in the exception handler block, although not shown in the flowchart, after judging the processing result in the exception handler and the condition depending on the type of exception, 3
Two choices are possible.

If step S22 is selected in this exception handling sequence, Continue Excep
Execute the instruction command.

FIG. 22 shows an operational flowchart of the virtual CPU when the Continue Exception instruction is executed. In the flowchart of FIG. 22, Continue E
When the xception command starts to be executed, first, step S6
In the virtual CPU, the virtual CPU sets the contents of the Catcher FP, Catcher PC, and Catcher WP fields from the exception state frame pointed to by the ES register (exception state frame pointer 5) to the FP, PC, and WP registers (function word frame pointer 3, The program index is returned to the program counter 2 and the frame pointer 4), and the table index for continuing the search of the handler table is extracted from the handler entry index field.

After that, in step S7A in step S7, the virtual CPU of the function pointed to by WP (number of times word frame pointer 3) of the handler entry that matches the same condition as the handler search condition step S2B in the RaiseException instruction. Search from the position indicated by the table index of the exception handler table.

In the next step S7B, if the search is not found (No), the process proceeds to step S8.
In this step S8, the table index for the handler table search is set to zero to prepare for the next search.

Then, the process proceeds to step S9. In step S9A of this step S9, the execution state of the virtual CPU stored in the stack in order for the function calling the currently executing function to return from the function is based on the FP register (frame pointer) as a function stack frame. Access to the WP, PC, FP registers (function word frame pointer 3, program counter 2, frame pointer 4), and in the next step S9B, the function pointed to by WP (function word frame pointer 3) is an exception. The search is performed on the function call chain until the function has the handler table. If the exception handler table is found in this step S9B (Yes), the process returns to step S7 and the search for the handler entry is repeated.

If a handler entry satisfying the conditions is found by searching the exception handler table in step S7 (Yes in step S7B), the virtual CPU proceeds to step S10. In this step S10, the WP, PC, and FP registers (function word frame pointer 3, program counter 2, frame pointer 4) at the time when the function having the handler is being executed are set in the exception state frame Catcher WP, Catche.
r Save in each field of PC and Catcher FP, and set the index of the found entry in the table to the handler entry index of the exception status frame in the same way.

Thereafter, in step SS11, the handler block start address of the handler entry is referred to and set in the PC register (program counter 2), and the execution of the Continue Exception instruction is completed. Figure 9 shows the stack status and register point positions at this point.
And P3 in FIG. After that, sequential execution is started as a new exception handler sequence from the virtual CPU instruction at the head of the exception handler block pointed to by the PC8 program counter 2).

If Step S23 is selected in the exception handling sequence of FIG. 21, Unwind Sta
Execute ck instruction.

FIG. 23 shows an operational flowchart of the virtual CPU when the Unwind Stack instruction is executed.

In this flowchart, Unwind Sta
When the ck instruction starts to be executed, in step S12A of step S12, the ES and EP registers (exception state frame pointer 5 and exception argument frame pointer 6) are set to the Initia of the exception state frame pointed to by the ES register.
It recovers from the tor ES, Initiator EP field, and in the next step S12B, it judges whether or not all the exception frames generated during the execution of the function currently being executed have been removed from the stack, and if they have not been removed, Remove all from stack.

Then, in step S13, the local stack state of the function currently being executed is emptied. That is, here, the stack returns to the state in which this function was originally called, and the execution of the Unwind Stack instruction ends. The state of the stack and the point position of the register at this point are shown by P4 in the drawing of FIG.

After that, returning to the processing sequence of the exception handler block shown in FIG. 21, the virtual CPU instruction next to the Unwind Stack instruction is sequentially executed. However, as in step S24, the normal processing is performed somewhere in the function. It is common to branch into a program. in this way,
When step S23 is selected in the exception handling sequence, all the information for returning to step S20 of the exception starting sequence in FIG. 19 is erased, so the exception starting sequence is never recovered and ended.

In the mechanism example of the Unwind Stack instruction described above, only the stack contents are popped and deleted, but after the function continuation of control disappears by popping the function stack frame, a problem occurs after the function. In order to perform processing, the Unwind protection handler that is started when the Unwind Stack is executed is defined in that function, and it is
Raise Ex can be started when the Unwind Stack instruction is executed.
Unwin the same mechanism as the handler search in the ception command
It can be applied and added in the same way to the d Stack instruction.

When step S25 is selected in the exception handling sequence of FIG. 21, the return value of the handler is pushed onto the stack, and in step S26.
Execute the Return Exception instruction.

FIG. 24 shows an operation flowchart of the virtual CPU when the Return Exception instruction is executed. The state of the stack and the point position of the register immediately before the execution of the Return Exception instruction are shown in P5 of FIG.

In the flowchart of FIG. 24, Return
When the Exception instruction is executed, the virtual CPU saves the return value of the exception handler at the top of the stack in step S14. Then, in step S15, Initiator WP, Initiato of the exceptional state frame pointed to by ES (exceptional state frame pointer 5)
r PC, Initiator FP, Initiator EP, Initiator ES field contents WP, PC, FP, EP, ES respectively
The registers (function word frame pointer 3, program counter 2, frame pointer 4, exception argument frame pointer 6, exception state frame pointer 5) are restored, and the exception state frame and the exception argument frame are popped and removed from the stack.

In the next step S16, step S
The return value of the exception handler saved in 14 is placed on the top of the stack, and the execution of the Return Exception instruction ends. The state of the stack and the point position of the register at this point are indicated by P6 in FIG. After that, since the process returns to the exception activation sequence in the execution state of the function that executed the Raise Exception instruction that started the exception handler, the sequential execution from the virtual CPU instruction next to the Raise Exception instruction is resumed in step S20 of FIG. The exception handler return value is popped and received, and the exception startup sequence ends.

Even when multiple exceptions occur in the above-described embodiment, the exception processing state is stacked as a stack frame, so that it is possible to return to the exception starting point without contradiction.
The Unwind Stack instruction can also erase multiple exception stack frames at once.

Returning to FIG. 1, the CD-RO of the apparatus of this embodiment.
The M drive 106 reads data from the loaded software package medium (the CD-ROM disc 111). Here, in the data recorded on the disk 111, the normal processing program and the programs of the plurality of exception processing handlers are included in the data, and the execution states and exceptions of the normal processing programs which are required to be executed by each exception handler are selected. The situation is coded in advance and prepared for each exception handling handler, combined with each exception handling handler and added as information in the program code. The normal processing program and the exception processing handler program, and the information added to the exception processing handler are recorded as virtual CPU instructions (virtual CPU programs), for example, in the virtual CPU program area 112 at the innermost circumference of the disk 111. ing. The virtual CPU
The program is stored in the virtual CPU memory storage area 103 of the RAM 130.

Further, the CPU 100 of the apparatus of this embodiment is connected to the bus 108 such as a key input device 7 such as a keyboard, a CD-ROM drive 106, an MPEG decoder 105 described later, a CRT display controller 109, etc. It mainly controls and sends and receives various data. The CPU 100 interprets the virtual CPU program stored in the virtual CPU memory storage area 103 of the RAM 130 connected to the bus 108 based on the virtual CPU interpreter program stored in the virtual CPU interpreter program storage area 102. By executing it, the exception handling mechanism is realized as described above.

Further, the virtual CPU program controls each device connected to the bus 108 at a high level, and C
The control intended by the D-ROM manufacturer is finally performed.

The apparatus of this embodiment is a so-called MPEG.
It also has a (Moving Picture Expert Group) decoder 105, and the compressed image data recorded on the CD-ROM disk 111 is decoded by the MPEG decoder 105, and this image data is transferred to the CRT via the image buffer memory 104. Display controller 109
It is displayed on the CRT display 110 controlled by. In addition, the display 110
It is possible to use not only a CRT (cathode ray tube) but also another display device (for example, a liquid crystal display device). In this case, the controller 109 performs control according to the display device.

In the embodiment of the present invention described above, the address range of the processing program in which the exception handler is valid and the address of the exception handler corresponding to the range are prepared in advance as a table. Only when the exception is activated, the table and stack frame are searched. Therefore, the CPU instruction content of the normal processing program has nothing to do with the presence or absence of an exception handler, and the processing for validating or invalidating the definition of the exception handler is
It does not need to be performed by a normal processing program. Further, in a language or a CPU that provides an exception handling mechanism having flexible and various control forms as described in this embodiment, it is possible to reduce the processing overhead for adding exception handling in normal processing to zero. It can be realized by the invention.

Further, the above embodiment is only one embodiment of a language and a CPU having a function definition and its calling mechanism, but the execution states and concepts required by the language and the CPU are different. However, if the language or CPU has the concept of the execution state, the present invention can be applied to realize the same exception handling mechanism.

[0068]

According to the information processing apparatus of the present invention, the normal processing program and the programs of a plurality of exception processing handlers as well as the execution state and the exception status of the normal processing program which each exception handler needs to be selected and executed. Necessary for a normal processing program for adding an exception processing program, because it is coded in advance and prepared for each exception processing handler, and combined with each exception processing handler and added as information in the program code. It is possible to reduce the overhead to zero. That is, it is possible to realize an exception processing mechanism in which the presence or absence of exception processing does not affect the processing amount of the normal processing program at all.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a register included in a virtual CPU.

FIG. 3 is a diagram illustrating a stack of virtual CPUs.

FIG. 4 is a diagram showing a structure of a function word frame.

FIG. 5 is a diagram showing a structure of a function instruction frame.

FIG. 6 is a diagram showing a structure of an exception handler table.

FIG. 7 is a diagram showing a structure of a stack frame when a function is called.

FIG. 8 is a diagram showing a structure of a stack frame created when an exception is detected and an exception sequence is activated.

FIG. 9 is a diagram showing an example of a stack snapshot in an exception sequence.

FIG. 10 is an enlarged view showing an upper left portion when FIG. 9 is divided into four.

FIG. 11 is an enlarged view showing a lower left portion in the case where FIG. 9 is divided into four.

FIG. 12 is an enlarged view showing an upper right portion when FIG. 9 is divided into four.

FIG. 13 is an enlarged view showing a lower right portion when FIG. 9 is divided into four.

FIG. 14 is a diagram showing another example of the stack snapshot in the exception sequence.

FIG. 15 is an enlarged view showing an upper left portion in the case where FIG. 14 is divided into four.

FIG. 16 is an enlarged view showing a lower left portion of FIG. 14 divided into four parts.

FIG. 17 is an enlarged view showing an upper right part in the case where FIG. 14 is divided into four.

FIG. 18 is an enlarged view showing a lower right portion when FIG. 14 is divided into four.

FIG. 19 is a flowchart showing the sequence of a program for starting an exception.

FIG. 20 is a flowchart showing the operation of the virtual CPU when a Raise Exception instruction is executed.

FIG. 21 is a flowchart showing a processing sequence for outputting an exception handler block.

FIG. 22 is a flowchart showing the operation of the virtual CPU when a Continue Exception instruction is executed.

FIG. 23: Virtual C when the Unwind Stack instruction is executed
It is a flowchart which shows operation | movement of PU.

FIG. 24 is a flowchart showing the operation of the virtual CPU when a Return Exception instruction is executed.

[Explanation of symbols]

1 Stack pointer 2 Program counter 3 Function word frame pointer 5 ..Exception status frame pointer 6 ... Exception argument frame pointer 7 ... Stack 8 ... Function word frame 9 ...・ ・ ・ ・ ・ ・ ・ ・ Function instruction frame 12 ・ ・ ・ ・ ・ ・ Exception handler table 20 ・ ・ ・ ・ ・ ・ ・ ・ ・ Function stack frame 21 ・ ・ ・ ・ ・ ・ ・ Exception stack frame 100 ... CPU 102 ... Virtual CPU interpreter program storage area 103 ... Virtual CPU memory storage area 104 ... Image buffer Memory 105 ... MPE Decoder 106 ・ ・ ・ ・ ・ ・ CD-ROM drive 107 ・ ・ ・ ・ ・ ・ Key input device 108 ・ ・ ・ ・ ・ ・ Bus 109 ・ ・ ・ ・ ・ ・ CRT display controller 110 ・・ ・ ・ ・ CRT display 111 ・ ・ ・ ・ ・ ・ CD-ROM disk 112 ・ ・ ・ ・ ・ ・ Virtual CPU program area 120 ・ ・ ・ ・ ・ ・ ROM 130 .... RAM

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] July 19, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction content]

2 and 3 show registers in the virtual CPU (corresponding to the virtual CPU memory storage area 103 of the RAM 130 of FIG. 1 and a part of the registers of the CPU 100), and show a programming model.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0043

[Correction method] Change

[Correction content]

FIG. 21 shows a processing sequence flow in the exception handler block. In FIG. 21, step S21 is the main body of processing in the exception handler.
Since the exception handler block is executed in the same context as the function here, the arguments and local variables of the function can be accessed while retaining the contents at the time of exception activation, and other EP and ES registers (exception argument frame pointer 6 It is also possible to refer to the exception argument and exception state frame based on the exception state frame pointer 5). After that, to finish the processing in the exception handler block, although the condition judgment is not shown in the flowchart, three selections are possible after judging the processing result in the exception handler and the condition depending on the type of exception. .

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] Fig. 21

[Correction method] Change

[Correction content]

FIG. 21 is a flowchart showing a processing sequence in an exception handler block.

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

[Procedure correction 6]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

[Procedure Amendment 7]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 8]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 7

[Correction method] Change

[Correction content]

[Figure 7]

[Procedure Amendment 9]

[Document name to be corrected] Drawing

[Correction target item name] Figure 8

[Correction method] Change

[Correction content]

[Figure 8]

[Procedure Amendment 10]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 14

[Correction method] Change

[Correction content]

FIG. 14

[Procedure Amendment 11]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 20

[Correction method] Change

[Correction content]

FIG. 20

Claims (4)

[Claims] 1. A computer program is divided into a normal processing program and a plurality of exception processing handlers and coded, the definition of the exception processing handler is dynamically performed by executing the normal processing program, and the normal processing is performed when an exception is detected. An information processing apparatus for controlling to dynamically select and execute the exception handling handler based on the execution state of a program, from a first exception handling handler according to a predetermined rule to a second exception handling handler Process of transferring the control of the exception handling handler, the process of clearing the execution control state of the exception handling handler and the recovery of the execution environment in which the exception handling handler is defined, the process of returning control from the exception handling handler to the exception starting point, and the exception Process of exchanging parameters between processing handler and exception starting point, and the exception processing handler in the execution environment in which the exception processing handler is defined And execution of the process, the information processing apparatus characterized by comprising a control means for the stroke of multiple exceptions for multiplexing exception handling. 2. In order to select the exception handling handler, execution state information of a normal processing program to be selected is added to each exception handling handler and included in the coded program in advance as information. The information processing device according to claim 1. 3. When the exception is detected, the exception processing handler is selected and executed by comparing the execution state of the normal program when the exception is detected with the execution state information of the normal processing program added to each exception processing handler. The information processing apparatus according to claim 2, which is controlled. 4. The information processing apparatus according to claim 1, wherein the control means is controlled by one stack.