JPH0743954B2 - Semiconductor memory device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention mainly relates to a semiconductor memory device including a channel cut ROM, and more specifically, it has memory cells arranged in a plurality of rows and a plurality of columns. The present invention relates to a semiconductor memory device in which data is stored by preliminarily selecting and setting a threshold value of a memory cell to a first size or a second size in accordance with a column address.

[Prior Art] A semiconductor memory device of this type that has been generally known in the past is, for example, that shown in FIG.

FIG. 6 is an overall view of a semiconductor memory device including a 1-bit × 16-word ROM. In the figure, 1 is a memory cell array composed of a plurality of memory cells 5 arranged in a plurality of rows (4 rows in the drawing) and a plurality of columns (4 columns in the drawing). Reference numeral 22 denotes an X decoder which is an example of row selecting means and outputs a high level signal or a low level signal to each word line driver 20 based on the address input signals Aφ and A1. When a high level signal is input to the word line driver, a low level signal is output to the word line 3 connected to the word line driver 20. That is, the word line driver 20 is composed of an inverter composed of an N-channel MOS transistor and a P-channel MOS transistor, to which a voltage is applied by the power supply 26, and the input is inverted to be output. The X decoder 22 is composed of an inverter 30 and a NAND circuit 34 composed of a P-channel MOS transistor and an N-channel MOS transistor, and has four NANDs.
A low level signal is output from one of the circuits 34 and a high level signal is output from the other three. The NAND circuit 34 that outputs a low-level signal is appropriately selected by four kinds of combinations of low-level and high-level signals of the address input signals Aφ and A1. Then, only the word line 3 connected to the word line driver 20 to which the low level signal output from the NAND circuit 34 is input becomes the high level state, and the high level is applied to the memory cells 5 existing in the row belonging to the word line 3. The signal will be input as a gate signal. That is, the memory cell 5 is composed of an N-channel MOS transistor, and a high-level signal is input to the gate electrode, which is an example of the control electrode of the N-channel MOS transistor. If the threshold value of the channel MOS transistor is lower than the input gate voltage, the N-channel MOS transistor becomes conductive, and if the threshold value is higher than the gate voltage, the N-channel MOS transistor.
The transistor does not become conductive. Data is stored according to the threshold value of each memory cell.

In the figure, 24 is a Y decoder which is an example of a column selecting means,
It consists of an inverter 32 and a NOR circuit 36.
Only one of the NOR circuits 36 outputs a high level signal, and the other NOR circuits 36 output a low level signal. A NOR circuit 36 that outputs a high level signal by combining four types of signals of high level and low level in the address input signals A2 and A3
Is configured to be appropriately selected. The NOR circuit 36
Output from the N channel provided on the bit line 4.
It is input to the gate of the MOS transistor 38.
Then, the N-channel MOS transistor 38 to which the high level signal has been input is in the conductive state, and the N-channel MOS transistor 38 to which the low level signal has been input is in the non-conductive state.

As described above, the X decoder 22 can select a row of the memory cells 5 including a plurality of rows and a plurality of columns, and
The decoder 24 can select a column of the memory cells 5 including a plurality of rows and a plurality of columns, and one memory cell 5 existing in the selected row and column can be selected and specified. Then, the voltage from the power supply 26 is applied to the selected and specified one memory cell 5, and the threshold value of the N-channel MOS transistor of the memory cell is applied to the applied voltage, that is, the gate voltage. N depends on whether the value is high or low
It is determined whether or not the channel MOS transistor is in the conductive state, and whether or not the channel MOS transistor is in the conductive state can be detected by the sense amplifier 28 which is an example of the state determining means. The voltage V from the power source 26
_In addition to the word line driver 20, _DD is also supplied to each inverter 30 and the NAND circuit 34 of the X decoder 22, and also to the inverter 32 and the NOR circuit 36 of the Y decoder 24, and further to the sense amplifier 28. Is also supplied.

[Problems to be Solved by the Invention] In this type of conventional semiconductor memory device, since the word line 3 selected by the X decoder 22 rises to a high voltage corresponding to the voltage V _DD generated by the power supply 26, data is stored. Therefore, it is necessary to set the threshold value of the memory cell 5 having a high threshold value higher than the rising voltage of the word line 3 in advance. However, in order to obtain such a high threshold value, it is necessary to implant high-concentration impurities in the manufacturing stage of the memory cell 5, which is a problem in terms of wafer process, and the electrical breakdown voltage of the memory cell transistor is high. There is a drawback that the semiconductor memory device is deteriorated to have low reliability.
Therefore, it is conceivable to set the voltage V _{DD of the} power supply 26 to a low value from the beginning, but the voltage from the power supply 26 is not limited to the word line driver 20 and the X decoder as described above.
Since it is also applied to various other circuits such as 22 and Y decoder 24, a new drawback is that various inconveniences occur in the other various circuits by lowering the voltage V _{DD of the} power supply 26. Occurs.

In view of such circumstances, an object of the present invention is to provide a semiconductor memory device capable of reducing only the threshold value of a memory cell without reducing the power supply voltage.

[Means for Solving the Problem] The present invention has a memory cell array in which a plurality of memory cells each having a control electrode and having a predetermined threshold value are arranged in a plurality of rows and a plurality of columns. A semiconductor memory device, wherein each of the cells changes between a first logic state and a second logic state depending on a magnitude relationship between a voltage applied to the control electrode and the threshold value. Row selecting means for selecting each row, column selecting means for selecting each column of the plurality of memory cells, and the memory cells by lowering a voltage from a power supply for applying a voltage to a predetermined device. Voltage reducing means for applying the voltage to the control electrode, wherein the plurality of memory cells are in the first logic state in response to a voltage applied to the control electrode by the voltage reducing means. Previous A first memory cell having a threshold value set, and the threshold value is set to be in the second logic state in response to a voltage applied to the control electrode by the voltage lowering means. A memory cell selected by the row selecting means and the column selecting means in response to a voltage applied to its control electrode. It further includes a state discriminating means for discriminating which one of the logical states of the above.

[Operation] According to the present invention, memory cells having control electrodes are arranged in a plurality of rows and a plurality of columns to form a memory cell array. Each of the plurality of memory cells changes between the first logic state and the second logic state depending on the magnitude relation between the voltage applied to the control electrode and a predetermined threshold value. Also, each row of the plurality of memory cells is selected by the row selecting means, each column of the plurality of memory cells is selected by the column selecting means, and a predetermined memory cell is selected and specified by both the selecting means. . Further, the voltage from the power source is applied to the control electrode of the memory cell in a state where the voltage from the power supply is reduced by the voltage reducing means. Further, the plurality of memory cells are
It includes a first memory cell and a second memory cell. The threshold value of the first memory cell is set so as to be in the first logic state by the voltage applied to the control electrode by the voltage lowering means. The threshold value of the second memory cell is set so as to be in the second logic state by the voltage applied to its control electrode by the voltage lowering means. Then, by the operation of the state determining means, the memory cells selected by the row selecting means and the column selecting means are in the first logic state or the second logic state in response to the applied voltage. It is determined which one of them is in.

That is, the memory cells are divided into a memory cell group located at a predetermined address of a plurality of addresses composed of rows and columns and a memory cell group other than that, and one of the memory cell groups is designated as the first memory cell. By configuring the other memory cell group by the second memory cell, data is stored, and the memory cell selected by the row selecting means and the column selecting means serves as its control electrode. By determining whether the memory cell at the predetermined address is in the first logic state or the second logic state in response to the applied voltage, the memory cell located at the predetermined address is the first memory cell or the second memory cell. It is possible to know the number of the two memory cells and read the stored data.

Then, the voltage applied to the control electrode of each memory cell is
Since the voltage lowering means causes the voltage to be lower than the power supply voltage, the threshold value of the memory cell whose size is set with the height of the applied voltage as a reference can be set low accordingly.

Embodiments of the Invention Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a word line drive portion in a semiconductor memory device according to the present invention. In the figure, 20 is a word line driver, which is a P-channel MOS transistor 11
And an N-channel MOS transistor 12.
3 is a word line, which is the P-channel MOS transistor 1
The drain electrodes of 1 and the N-channel MOS transistor 12 are connected. A bit line 4 is connected to the sense amplifier 28 via an N-channel MOS transistor 38 as shown in FIG. Reference numeral 7 denotes an N-channel MOS transistor, and a gate electrode and a drain electrode of the N-channel MOS transistor 7 are connected to each other and connected to a connection portion thereof to a power source from the power source 26 shown in FIG. The voltage V _DD is applied. The source electrode 8 of the N-channel MOS transistor 7 is a P-channel M
It is connected to the source electrode of the OS transistor 11. The gate electrodes of the P-channel MOS transistor 11 and the N-channel MOS transistor 12 are connected to each other and connected to the terminal 6. As shown in FIG. 6, a high level signal or a low level signal from the X decoder 22 is supplied. Is entered. further,
The source of the N-channel MOS transistor 12 is connected to GND. In the figure, 5 is a memory cell, which is an N-channel MOS
It is composed of a transistor and its N channel
The source of the MOS transistor is connected to GND, the gate electrode of an example of the control electrode is connected to the word line 3, and the drain electrode is connected to the bit line 4. There are two types of threshold values of the N-channel MOS transistors forming the memory cell 5, that is, a normal low value and a slightly higher value than normal.

Next, the operation will be described.

When the signal obtained by decoding the address signal from the X decoder 22 (see FIG. 6) is input to the terminal 6 and the decoded signal is at the low level, the P channel MO
The output of the inverter composed of the S-transistor 11 and the N-channel MOS transistor 12 is in the high level state, but the potential of the output in the high level state does not rise above the potential of the source electrode 8. On the other hand, since the gate electrode of the N-channel MOS transistor 7 is connected to the power supply 26 (see FIG. 6) together with the drain electrode, the potential of the source electrode 8 is
If it is lower than the value obtained by subtracting the threshold voltage V _th (hereinafter referred to as V _th7 ) of the N-channel MOS transistor 7 from the power supply voltage V _DD , the N-channel MOS transistor 7 _{turns on} and the potential of the source electrode 8 rises. As a result, the potential of the source electrode 8 is
Biased to V _DD −V _th7 . Therefore, word line 3
Is charged to V _DD −V _th7 when selected. If the threshold value of the predetermined N-channel MOS transistor forming the memory cell 5 connected to the word line 3 is normally low, the N-channel MOS transistor is turned on, while the N-channel MOS transistor in the memory cell 5 is turned on. If the threshold value of the MOS transistor is high near V _DD -V _th7 , the N-channel MOS transistor does not turn on, and the sense amplifier 28 shown in FIG. 6 turns on the memory cell 5 which is maintained at a predetermined address. It is possible to determine whether or not it has been done, and the data of "0" and "1" can be read from the memory cell group. At this time, the word line does not rise to the power supply voltage V _DD as in the conventional case and only rises to V _DD −V _{th7. Therefore} , the N channel of the memory cell that does not turn on even when the voltage is applied.
It is not necessary to raise the threshold value of the MOS transistor to near the power supply voltage V _DD, but it is sufficient to raise it to near V _DD -V _th7 . This N-channel MOS transistor 7
Thus, voltage reduction means for reducing the voltage from the power source and applying it to the memory cell is configured.

In the embodiment shown in FIG. 1, one P-channel MOS transistor of the word line driver 20 for driving the word line 3 has a gate electrode and a drain electrode connected between the source and the power source. Although the N-channel MOS transistor 7 is inserted, a plurality of similar N-channel MOS transistors 7 may be inserted in series as shown in FIG.
Further, as shown in FIG. 3, the sources of the P-channel MOS transistors of the word line driver 20 composed of a plurality of inverters are connected to each other, and the N-channel MOS transistor is connected between the source of the common P-channel MOS transistor and the power supply. 7 may be inserted.

Further, as shown in FIG. 4, as the word line driver 20, a NAND circuit composed of a P-channel MOS transistor and an N-channel MOS transistor may be used instead of the inverter, and as shown in FIG. , P channel
You may use the NOR circuit which consists of a MOS transistor and an N channel MOS transistor. In this case, signals from different decoders may be input to the two input terminals 50a and 50b, respectively, or one input terminal 50a inputs a signal from the decoder and a clock signal is input to the other input terminal. You may enter. In addition, 7 in FIG. 4 and FIG.
Is an N-channel MOS transistor which is an example of the voltage lowering means.

[Advantages of the Invention] In the present invention having the above configuration, since the voltage applied to the control electrode of each memory cell is lower than the power supply voltage due to the function of the voltage lowering means, The threshold value of the memory cell whose size is set on the basis of the height can be set low accordingly, and only the threshold value of the memory cell can be lowered without lowering the power supply voltage. It has become easier to provide a highly reliable semiconductor memory device by improving the electrical breakdown voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of a semiconductor memory device according to the present invention. FIG. 2 is a circuit diagram of a main part showing another embodiment of the present invention. FIG. 3 is a circuit diagram of a main part showing still another embodiment of the present invention. FIG. 4 is a circuit diagram of an essential part showing still another embodiment of the present invention. FIG. 5 is a circuit diagram of an essential part showing still another embodiment of the present invention. FIG. 6 is a general circuit diagram of a semiconductor memory device showing a conventional example. In the figure, 5 is a memory cell, 1 is a memory cell array, 22 is an X decoder which is an example of row selecting means, 24 is a Y decoder which is an example of column selecting means, and 7 is N which is an example of voltage lowering means.
The channel MOS transistor 28 is a sense amplifier which is an example of a state determining means.

Claims (1)

[Claims] 1. A memory cell array in which a plurality of memory cells having control electrodes and having predetermined threshold values are arranged in a plurality of rows and a plurality of columns, each of the plurality of memory cells being the control electrode. A semiconductor memory device that changes between a first logic state and a second logic state depending on a magnitude relationship between a voltage applied to the memory cell and the threshold value, and row selection for selecting each row of the plurality of memory cells. Means, column selecting means for selecting each column of the plurality of memory cells, and lowering a voltage from a power supply for applying a voltage to a predetermined device and applying the voltage to the control electrode of the memory cell. And a threshold value of the plurality of memory cells is set so as to be in the first logic state in response to a voltage applied to the control electrode by the voltage reducing means. Was first No. 1 memory cell and a second memory cell in which the magnitude of the threshold value is set so as to be in the second logic state in response to the voltage applied to the control electrode by the voltage lowering means. , The memory cell selected by the row selecting means and the column selecting means is in one of the first logic state and the second logic state in response to a voltage applied to its control electrode. The semiconductor memory device further including a state determination means for determining whether or not it is present.