JPH0740434B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a MOS type memory cell.

(Prior Art) FIG. 5 is a circuit diagram showing a main part of a conventional semiconductor memory device. This circuit is widely used in high-speed MOS semiconductor memory devices, and employs a CMOS circuit which is said to have the best performance. In the figure, 1 is a memory cell, 2 is a sense amplifier, 3 and 4 are bit lines, and W is a word line. MOS transistor
Reference numerals 5, 6, 7, and 10 constitute a switch for executing precharge, a transfer gate for extracting data, a memory cell, and a constant current source. Further, 8 and 9 are bit line capacitors coupled to the bit lines 3 and 4, respectively.

In such a circuit, in order to speed up the sense amplifier 2, the dimensions of the precharge transistor 5, the transfer gate transistor 6, and the memory cell transistor 7 are optimized, and the potential difference between the bit lines 3 and 4 is set to a high level. It is necessary to make it as small as possible on the “1” side and the low level “0” side.

In this case, generally, the time t required for the potential of the bit line 3 or 4 changes by △ V, the bit line capacitance 8,9 as _{C BL, t = C BL ·} △ V / I ··· ( 1) is represented. Here, I is a current flowing through the bit lines 3 and 4.

According to the equation (1), I is increased by
_It suffices to reduce _BL and ΔV. However, since the size of the memory cell transistor 7, especially the width W, must be made as small as possible, the current I flowing through the bit lines 3 and 4 is
Becomes smaller. When a large number of transfer gate transistors 6 are connected for high integration, the bit line capacitances 8 and 9 increase due to the junction capacitance formed between the drain and the substrate.

Therefore, in order to reduce the time t based on the equation (1), there is no other method than to reduce the change voltage ΔV of the bit lines and the transition time (recovery time) of the bit lines 3 and 4.

[Problems to be Solved by the Invention]

However, in the configuration shown in FIG. 5, since the voltage of the bit lines 3 and 4 is received by the gate of the N-channel MOS type transistor of the sense amplifier 2, it is necessary to take a large transition voltage ΔV. That is, if the transconductance g _m of the MOS type transistor is increased, the size of the transistor becomes large, so that it must be kept low in order to increase the degree of integration, and the transition voltage ΔV is necessarily increased. I have to do it. Therefore, the conventional sense amplifier has a drawback that it is extremely difficult to detect a minute current. Moreover, since the potentials of the bit lines 3 and 4 are configured to change in the vicinity of the power supply voltage V _DD , it is said that the sense amplifier 2 operates largely outside the threshold voltage V _{th in which} the sensitivity is the highest. There was also a problem.

In order to solve such a drawback, measures such as suppressing the conductance of the transistor 10 for the constant current source and adopting a P-channel transistor as the load of the transistor for the sense amplifier have been taken. However, the former measure reduces the drain current of the sense transistor,
On the other hand, the latter measure involves using a P-channel MOS transistor, which is inferior in characteristics, instead of the N-channel MOS transistor, and thus has a problem with respect to high-speed operation.

The present invention has been made to solve such conventional problems, and an object thereof is to provide a high-speed semiconductor device.

[Structure of Invention]

(Means for Solving the Problem) The present invention is directed to a plurality of memory cells formed of MOS transistors and arranged in a matrix, and connected to memory cells provided in each column of these memory cells in the same column. A plurality of complementary bit line pairs, and a sense amplifier that amplifies and outputs a signal read from these bit line pairs, wherein the sense amplifier is provided in each of the bit line pairs. A plurality of detection bipolar transistor pairs to which bases are connected, a constant current source commonly connected to the emitters of the detection bipolar transistor pairs, and a MOS having a saturated drain current larger than the supply current of the constant current source Transistors, one end of each of which is connected to the collector of the detection bipolar transistor pair and Control electrode enters the column decoder signal, and having a plurality of transfer gates pair, and a common load element commonly connected to the other end of the MOS transistors constituting the transfer gates pair.

(Operation) Use a bipolar transistor whose emitter is commonly connected as a transistor used to detect the potential of the bit line, and connect these bit lines to the base so that the signal with the amplified potential difference is taken out. Therefore, even if the voltage difference between the bit lines is minute, the change can be detected at high speed and output with a high amplification degree.

Further, since the transfer gate pair controlled by the column data signal is provided between the common load element and the detection bipolar transistor pair, column selection can be performed by this transfer gate pair. Therefore, it is not necessary to change the potential of the bit line in order to select the column, and the reading speed can be increased.

Further, by forming a transfer gate pair with a MOS transistor having a saturated drain current larger than the supply current of the constant current source and connecting the transfer gate pair to the collector side of the detection bipolar transistor pair, the detection bipolar transistor pair is connected to the non-saturation region. Therefore, the operation of the detection bipolar transistor pair can be speeded up, and this can also speed up the reading.

(Example) Hereinafter, the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram schematically showing the configuration of a semiconductor memory device according to an embodiment of the present invention. In FIG.
The components denoted by the same reference numerals indicate the same components as in FIG.

Also, as shown in the figure, the sense amplifier is
Bipolar NPN transistors 15,15 'whose bases are respectively connected to 3, 4 (which constitutes the "bit line pair" of the present invention)
(Constituting the "detection bipolar transistor pair" of the present invention), a MOS transistor 14 (constituting the "constant current source" of the present invention) commonly connected to the emitters of the bipolar transistors 15 and 15 ', and One end is connected to the collectors of the bipolar transistors 15 and 15 ', and each gate electrode is a MOS transistor 20 or 20' (which constitutes a "transfer gate pair" of the present invention) to which a column decoder signal is input, and one end is a MOS transistor. MOS transistors 13 and 13 '(which constitute the "common load element" of the present invention) which are commonly connected to the other ends of 20, 20' and the other end of which is connected to a power supply line (voltage V _DD ). There is. The one ends of the MOS transistors 20 and 20 'are input to the gate 16, respectively. The gate 16 outputs an output signal according to the input voltage to the output terminal 17.

Although the memory cells are arranged in a matrix in the semiconductor memory device according to this embodiment, only one memory cell is shown in FIG. The same sense amplifier is provided for each column of memory cells arranged in a matrix, but only one is shown in FIG. The transfer gates 20 and 20 'of each sense amplifier are
Commonly connected to one load MOS transistor 13,1
It is connected to 3 '. With such a configuration, only the sense amplifier output of the column selected by the column decoder signal input to the gate electrodes of the transfer gates 20 and 20 'is taken out and input to the gate 16.

Next, the operation of the semiconductor memory device shown in FIG. 1 will be described.

In the semiconductor memory device shown in FIG. 1, the potential difference between the bit lines 3 and 4 is ΔV, the current flowing in the high potential side bit line is I _H , and the current flowing in the low potential side bit line is I _L. Then, the ratio of I _H and I _L is expressed by I _H / I _L = exp {(q / KT) · ΔV} (2) Therefore, for example, KT / q = 25 mV, and ΔV =
With 0.4V, I _H / I _L = 10 ⁷ .

Also, of the output voltage of the sense amplifier (that is, the input voltage of the gate 16), select the one that corresponds to the bit line on the high potential side.
V _OH, a low potential side of the V _OL which corresponds to the bit line, and the resistance of the MOS transistors 13 and 13 'for loading the R, V _OH and V
The difference of _OL is V _OH −V _OL = R (I _H −I _L ) −RI _H −RI (3).

Thus, in this embodiment, the bipolar transistor 1
By converting the current difference of the collector current of 5,15 'into a voltage difference using the load MOS transistors 13, 13',
The level change of the bit lines 3 and 4 is to be detected.
Therefore, the level change detection sensitivity can be improved.

The MOS transistors 13 and 13 'are used as the common load element in order to utilize the advantage that the internal impedance is high in spite of the small occupied area, but a normal resistance element may be used. Of course.

If the bipolar transistors 15 and 15 'are used in the saturation region, the operation speed will be significantly reduced due to the effect of accumulating minority carriers. Therefore, the bipolar transistors 15 and 15 'need to be used in a non-saturated state, and for this purpose, the collector potential needs to be designed to be sufficiently larger than the base potential.

In this embodiment, transfer gates 20, 20 'are provided between the bipolar transistors 15, 15' and the common load elements 13, 13 '.
Is provided, the collector potentials of the bipolar transistors 15 and 15 'can be made sufficiently higher than the base potential for the following reason.

Figure 2 shows the gate-source voltage V _GS of a MOS transistor.
In a case where the constant is a graph showing the relationship between the drain current I _D and the drain-source voltage V _DS. In the figure, ID _max indicates the saturated drain current. The value of this ID _max is _{schematically, ID max = β (V GS} -V th) represented by ^2/2 (4). However, β = μC _G (W / L).

In order to make the collector potential of the bipolar transistors 15 and 15 'sufficiently higher than the base potential, a circuit composed of the transfer gates 20 and 20' and load MOS transistors 13 and 13 '(a MOS transistor equivalent to this circuit) is required. It is necessary to operate in the unsaturated region. To this end, transfer gates 20, 20 'and load MOS transistors 13, 1'
It is necessary to operate both 3'in the unsaturated region.

The conditions for making the collector potentials of the bipolar transistors 15 and 15 'sufficiently higher than the base potential are as follows.
The details will be described.

In the present invention, since the output of the sense amplifier is obtained by the collector output of the bipolar transistors 15 and 15 ', this sense amplifier output is resistance-divided by the bipolar transistors 15 and 15' and the transfer gates 20 and 20 '. . Therefore, in order to increase the gain of the sense amplifier, β (= β _T ) of the transfer gates 20 and 20 '
Should be sufficiently larger than β (= β _L ) of the load MOS transistors 13 and 13 ′.

Therefore, in considering the conditions for making the collector potentials of the bipolar transistors 15 and 15 'sufficiently higher than the base potential, the relationship between the load MOS transistors 13 and 13' and the constant current MOS transistor 14 should be examined. Will be enough.

When the load MOS transistors 13 and 13 'are operated in the non-saturation region, the supply current of the constant current MOS transistor 14 is set to I _C, and the gate-source voltage, threshold value, drain-source voltage of the load MOS transistor are set to V _{GS, L} , V respectively
_{th, L,} V _DS, as _{L, I C = β L {} (V GS, L -V th, L) V DS, L -V DS, L 2/2} ·
.. (5) is established. As can be seen from this equation, when operating the load MOS transistor in the non-saturation region, this load MO transistor
The drain-source voltage V _{DS, L} of the S transistor is uniquely determined with respect to the supply current I _C.

On the other hand, when the load MOS transistors 13 and 13 'are operated in the saturation region, I _C is the gate-source voltage of the constant current source MOS transistor 14 and the threshold value is V, respectively.
_{GS, C,} V _th, as _{C, I C = β C (} V GS, C -V th, C) is expressed by ^2/2 (6). That is, since V _{DS, L} is not included in this equation, when operating the load MOS transistors 13, 13 ′ in the saturation region, the drain-source voltage V _{DS, L} of the load MOS transistors is MOS transistor for constant current 1
The supply current I _{C of} 4 is not uniquely determined and a free value can be obtained.

Since it is necessary to keep V _{DS, L} constant in order to keep the collector potential of the bipolar transistors 15 and 15 'sufficiently higher than the base potential, the load MOS transistors 13 and 13' need to operate in the non-saturation region. It turns out that.

Here, the maximum value of the above equation (5) is the load MOS transistor 1
It is the boundary value between the unsaturated region and the saturated region of 3,13 '. That is, the maximum value of formula (5) _{is, β L (V GS, L} -V th, L) becomes ^2/2 (7). In order for the load MOS transistors 13 and 13 'to operate in the non-saturation region, the right side of (6) must have a value sufficiently larger than that of (7). In other words, the _{β L (V GS, L -V} th, L) 2/2 »β C (V GS, C -V th, C) 2/2 ··· (8).

At this time, if V _{GS, L} = V _{GS, C} = V _DD , V _{th, L} = V _{th, C} , then β _L >> β _C (9). Moreover, since β _T »β _L as described _{above, β T (V GS, T} -V th, T) 2/2 »β L (V GS, L -V th, L) 2/2 »β C ( _{V GS, C -V th, C} ) 2/2 ··· (10) is satisfied, thereby, eventually, a _{β T »β L »β C ··· (} 11).

As described above, in the present invention, it is possible to use a normal resistance element instead of the load MOS transistors 13 and 13 '. However, when such a resistance element is used, the above formula (10) is used. _{instead, β T (V GS, T} -V th, T) 2/2 »V R / R »β C (V GS, C -V th, C) 2/2 ··· (12) is satisfied Therefore, the resistance value R of the resistance element may be determined. Incidentally, V _R is the voltage between the terminals of the resistor element.

According to the above equation (11), the transconductance g _mT of the transfer gates 20 and 20 'must be larger than the transconductance g _mL of the load MOS transistors 13 and 13', and this transconductance g _mL is constant current source. It can be seen that it must be larger than the mutual conductance g _{mC of the} transistor 14 for use.

However, if the mutual conductance g _mc is too small,
Since the amplitude of the output voltage taken out from the collectors of the bipolar transistors 15 and 15 'cannot be made large, it is necessary to select an appropriate value.

The reason why the MOS transistors are used as the transfer gates 20 and 20 'is that if a bipolar transistor is used,
This is because the collector potential of the bipolar transistors 15 and 15 'is lowered by the PN junction, and the effect of raising the collector potential is reduced.

FIG. 3 shows the output voltage when the input voltage (the potential of the bit lines 3 and 4) of the sense amplifier (provided that g _mL / g _mc = 4) related to the semiconductor memory device of this embodiment is changed. It is a characteristic view which asked for change by transient analysis simulation.
5A is a waveform diagram of the output voltage of the sense amplifier according to the semiconductor memory device of the present invention, and FIG. 7B is a waveform diagram of the output voltage of the sense amplifier according to the conventional semiconductor memory device shown in FIG. FIG. 6C is a waveform diagram showing a change in the input voltage. As can be seen from the figure, according to the semiconductor memory device of the present embodiment, it is possible to improve the amplification degree and the reaction speed when reading out the potential difference between the bit lines 3 and 4.

Further, in the semiconductor memory device according to the present embodiment, the MOS transistors 19 and 19 'for level shifting are provided so that the bit lines 3 and 4 operate at a voltage relatively lower than the power supply voltage V _DD . As a result, the output voltage difference of the sense amplifier can be made large, and the number of stages of the gate 16 from the sense amplifier to the output terminal 17 can be reduced, and the speed can be increased accordingly.

FIG. 4 is an element sectional view showing an element configuration in the case where one side of the sense amplifier shown in FIG. 1 is realized by a semiconductor integrated circuit.

As shown in the figure, a load transistor 13, a constant current source transistor 14, and a detection transistor 15 are formed in a P-type silicon substrate 21. That is, the load transistor 13 forms a source S and a drain D by forming a P-type region in the N-type well 22, and the constant current source transistor 14 forms an n-type region directly on the surface of the substrate 21. To form a source S and a drain D, and the detecting transistor 15 uses an N-type well 23 as a collector C, and a P-type region in this well 23 is a base B, and an N-type well in this P-type region is formed.
The mold region is formed so as to serve as the emitter E.

Such a structure can be formed and integrated relatively easily by adopting the well-known CMOS process.

Although the case where the bit line detection transistors 15 and 15 'are configured as NPN transistors has been described in the present embodiment, it goes without saying that they may be PNP transistors. In this case, it is necessary to match the polarities of the constant current source MOS transistor 14 and the load MOS transistors 13, 13 '.

Further, in the present embodiment, the "bipolar transistor pair" of the present invention is composed of the transistors 15 and 15 ', but it may be composed of bipolar transistors connected in Darlington.

〔The invention's effect〕

As described above, according to the present invention, a bipolar transistor whose emitter is commonly connected is used as a transistor for detecting the potential of a bit line, and the potential difference is amplified from the collector by connecting these bit lines to the base. Since the signal is extracted, it is possible to provide a semiconductor memory device capable of detecting the change at high speed even when the potential difference between the bit lines is small and outputting the signal with a high amplification degree.

Further, since a transfer gate pair is provided between the detection bipolar transistor pair and the common load element, and the column selection is performed by controlling the transfer gate pair in accordance with the column decoder signal, the set potential of the bit line is set. By making the change, the time required for column selection can be shortened as compared with a semiconductor memory device that performs column selection, and also in this respect, the operating speed of the semiconductor memory device can be improved.

Further, according to the present invention, the transfer gate pair is constituted by MOS transistors having a saturated drain current larger than the supply current of the constant current source, and the transfer gate pair is provided on the collector side of the detection bipolar transistor pair. Can be operated in the non-saturated region, so that the operation of the detection bipolar transistor pair can be speeded up, and this can also speed up the operation of the semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a circuit diagram schematically showing the structure of a semiconductor memory device according to the present invention, and FIG.
A graph showing the relationship between source voltage and drain current,
FIG. 3 is a characteristic diagram showing changes in input / output voltage, and FIG.
FIG. 5 is a device sectional view showing a case where a part of the embodiment shown in the drawing is realized in a silicon substrate, and FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor memory device. 3,4 …… bit line, 13,13 ′ …… load MOS transistor, 14 …… constant current source MOS transistor, 15,15 ′ …… detection bipolar transistor, 19,19 ′ …… level shift transistor , 20,20 '…… Transfer gate.

Claims (5)

[Claims] 1. A plurality of memory cells which are composed of MOS transistors and are arranged in a matrix, and a plurality of complementary bits which are provided for each column of these memory cells and are respectively connected to the memory cells of the same column. A semiconductor memory device comprising: a line pair; and a sense amplifier that amplifies and outputs a signal read from the bit line pair, wherein the sense amplifier has a plurality of bases connected to the bit line pair. A pair of detecting bipolar transistors, a constant current source commonly connected to the emitter of the pair of detecting bipolar transistors, and a MOS transistor having a saturated drain current larger than the supply current of the constant current source. Are connected to the collectors of the pair of detecting bipolar transistors, and the respective control electrodes receive the column decoder signal. A semiconductor memory device comprising: a plurality of input transfer gate pairs; and a common load element commonly connected to the other ends of the MOS transistors forming the transfer gate pairs. 2. The semiconductor device according to claim 1, wherein the collector of the detection bipolar transistor is a well of opposite conductivity type formed in a semiconductor substrate of one conductivity type. . 3. The semiconductor memory device according to claim 1, wherein the common load element is a MOS transistor. 4. The semiconductor memory device according to claim 1, further comprising a level shift circuit between the base of the detecting bipolar transistor and the bit line. 5. The semiconductor device according to any one of claims 1 to 4, wherein the detection bipolar transistor pair is composed of two sets of bipolar transistor circuits, and each of the bipolar transistor circuits is cascade-connected. A semiconductor device comprising a bipolar transistor.