JPH0740278B2 - Logic circuit drawing generator - Google Patents

Description

The present invention relates to a logic circuit drawing generation device that automatically generates a logic circuit drawing from connection data indicating the connection relationship of logic elements. In particular, the present invention relates to a logic circuit drawing generation device that partitions a drawing into m × n and arranges logical symbols in each partition.

(Prior Art) In recent years, as the performance of graphics equipment has improved and the price of high-performance workstations has become lower, logic circuit diagrams for digital systems can be created and modified as specified by the designer. 2. Description of the Related Art Devices and logic circuit diagram generation devices such as a logic circuit diagram generation device that automatically generates a logic circuit diagram of a digital system from data indicating the connection relationship of logic elements have become widespread. Among them, especially in the automatic logic circuit diagram generation device, a circuit diagram generation method called a partition layout method has been conventionally used because it has advantages of high-speed processing and a small storage capacity.

This partition arrangement method divides the drawing into n × m (n and m are arbitrary natural numbers) partitions and assigns each logical symbol in partition units. For example, a 2-input AND 1 as shown in FIG. In order to automatically design a circuit consisting of a 2-input OR 2 and an inverter 3, first draw a drawing as shown in FIG.
Divide into 6 sections of × 2. Then, it is determined in which section each logical symbol is to be arranged based on the input / output relation information of each logical element, and each logical symbol is arranged in each of the determined sections. Then, when the logical symbol is allocated to a predetermined section, the connection process between the input and output of the logical symbol is performed.

According to this partition arrangement method, the position of the logical symbol in the partition is determined in advance. Therefore, by determining in which partition the logical symbol is to be arranged, the position where the logical symbol is arranged is uniquely determined. That is, the two-dimensional arrangement of one symbol can be determined only by designating the type of the logical symbol of the circuit component and the section in which it is arranged, so that the storage capacity can be reduced.

However, in such a conventional logical layout generating apparatus using the partition layout method, since the symbols in the partition are fixed at the same position, for example, as shown in FIG. There is a problem in that the vertical (y) coordinates of the terminals are different, which makes the wiring very bent and makes it difficult to see the logic circuit diagram.

(Problems to be Solved by the Invention) As described above, in the conventional logic circuit drawing generation device using the partition layout method, the drawing is difficult to see because the wiring between the input and output of the logic symbol is often bent There was a problem that it was not good.

The present invention can reduce the number of bent wirings without any loss of the advantage of the partition arrangement method that can perform the arrangement processing of logical symbols at high speed and with a small storage capacity, and can generate a drawing that is easy to see and looks good. An object is to provide a logic circuit drawing generation device.

[Structure of the Invention] (Means for Solving the Problems) The present invention relates to an input / output relationship between connected logic symbols in a logic circuit drawing generation device by a partition layout method in which a plurality of logic symbols are arranged in partition units. Means for setting the displacement amount of the logical symbol from the in-zone reference position based on the position, means for storing the displacement amount set by this means, and displacing the logical symbol from the reference position by the displacement amount. And a means for arranging them.

(Operation) In the present invention, since the logical symbols are not fixedly arranged at a certain fixed reference position in the partition, but the internal area of the partition can displace the logical symbols beyond the partition,
The logical symbol can be displaced so that the output end position of the input side logical symbol and the input end of the output side logical symbol connected thereto have the same vertical coordinate.
By displacing the logical symbols in this way, it is possible to wire the two logical symbols in a straight line, and therefore it is possible to reduce the number of bent wires.

(Embodiment) An automatic logic circuit generation device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of the device. This apparatus includes an arrangement processing unit 11, a displacement setting unit 12, a wiring processing unit 13, and a display processing unit 14 that perform various data calculations and processing, a connection storage unit 15 that stores various data, an arrangement information storage unit 16, and pins. It is composed of a position information storage unit 17, a displacement storage unit 18, a wiring information storage unit 19, and a symbol shape storage unit 20. When this device is configured with a CPU (central processing unit) and a storage device (not shown), the CPU has four large functional blocks including an arrangement processing unit 11, a displacement setting unit 12, a wiring processing unit 13, and a display processing unit 14. The storage device is composed of six storage units: a connection storage unit 15, an arrangement information storage unit 16, a pin position information storage unit 17, a displacement storage unit 18, a wiring information storage unit 19, and a symbol shape storage unit 20. To be done.

Now, it is assumed that the circuit diagram to be generated is the circuit composed of the 2-input AND 1 and 2-input OR 2 and the inverter 3 shown in FIG. The connection information storage unit 15 stores the connection information such as the type of each component as shown in FIG. 2 and information on the component and pin to which it is connected.

When the drawing generation request signal is input, the arrangement processing unit 11 inputs the connection information from the connection information storage unit 15 and arranges each component in a partition unit based on the connection relation of each component. The placement information at this time is stored in the placement information storage unit 16. As shown in FIG. 3, this arrangement information is composed of the logical symbol type of each component, and the X direction (horizontal direction) number and the Y direction (vertical direction) number of the section in which it is arranged. When the storage in the layout information storage unit 16 is completed, the layout processing unit 11 sends a layout end signal to the displacement setting unit 12.

On the other hand, the pin position information storage unit 17 stores the type of each component and the intra-section coordinates of the input / output pin at the reference position of each logical symbol, as shown in FIG. That is, in this embodiment, the size of one section is 300 × 300, and as shown in FIG. 5, the reference position is when each logical symbol is arranged at the bottom of each section. Therefore, in the case of 2-input AND and 2-input OR, the coordinates of the two input pins are (0,20) and (0,140), respectively, and the coordinates of the output pin are (300,80). The input pin coordinates of the inverter are (0,80) and the output pin coordinates are (300,8).
0).

When the displacement setting unit 12 receives the placement end signal, it reads the connection information for each component number from the connection information storage unit 15, reads the placement information from the placement information storage unit 16, and further reads the pin from the pin position information storage unit 17. Read position information. Upon receiving these pieces of information, the displacement setting unit 12 first sets the initial value of the displacement δ of all logic symbols to “0”, and determines the displacement in order from the output side, that is, the logic symbols arranged on the right side of the logic circuit drawing. The value of the partition Y of the logical symbol to be compared with the value of the partition Y to which the output is connected is compared, and if they match, the logical symbol for which the displacement should be further determined is moved within the range of the partition to determine the displacement. When the coordinate y of the output pin of the symbol and the coordinate y of the connection destination pin can have the same value, the value at that time is set as the displacement y.

The displacement setting unit 12 is configured, for example, as shown in FIG. The register 30 stores the value of the partition Y of the logical symbol of the component whose displacement is to be determined (hereinafter referred to as “target symbol”), and the register 31 stores the logical symbol of the connection destination of the target symbol (hereinafter referred to as “connection”). The value of the section Y of the "previous symbol") is stored. The register 32 stores the vertical size of the partition, and the register 33 stores the vertical size of the target symbol. Also, register 34
Stores a value obtained by adding the displacement δ of the connection destination symbol to the pin position y of the connection destination symbol (hereinafter referred to as “displacement addition pin position”). The register 35 stores the value of the output pin position y of the target symbol. Is stored.

The comparator 36 compares the section Y of the target symbol output from the registers 30 and 31 with the section Y of the connection destination symbol,
If they match, "1" is output, and if they do not match, "0" is output. The subtractor 37 inputs the vertical size of the section Y output from the register 32 and the vertical size of the target symbol output from the register 33, subtracts the latter from the former, and outputs the result. . The subtraction result indicates the maximum value of the displacement of the target symbol (hereinafter, referred to as “displacement maximum value”). The subtractor 38 subtracts the output pin position y of the target symbol output from the register 35 from the displacement addition pin position y output from the register 54, and outputs the result. The result is a candidate value of displacement y (hereinafter,
“Displacement candidate value”). The comparator 39 compares the displacement maximum value output from the two subtractors 37 and 38 with the displacement candidate value, outputs "1" if the displacement candidate value is less than the displacement maximum value, and outputs "1" if less than the same. Output 0 ". Further, the comparator 40 is
The displacement candidate value from the subtractor 38 is compared with "0", and if the displacement candidate value is greater than 0, "1" is output, and if it is less than 0, "0" is output. The outputs of the three comparators 35, 39, 40 are input to the AND circuit 41. AND circuit 41
When the outputs from these comparators 36, 39, 40 are all "1",
That is, the section Y of the target symbol and the section Y of the connection destination symbol
And the displacement candidate value is larger than “0” and smaller than the displacement maximum value, “1” is output to the selection circuit 42, otherwise “0” is output. . Selection circuit
The displacement candidate value from the subtractor 38 and the “0” level signal are input to the 42, and the selection circuit 42 uses the AND circuit 41.
When the output from is "1", the displacement candidate value from the subtractor 38 is selected, and when it is "0", the "0" level signal is selected.
Then, these selected values are set to the displacement δ of the symbol of interest.
Output as.

For example, considering the case where the symbol of interest is the logical symbol of component number 1, "2", "0", "300", "160", "0", "80" are stored in registers 30 to 35, respectively. Therefore, the output of the comparator 36 is “0” and the output of the AND circuit is “0”.
Therefore, since the selection circuit 42 selects “0”, the displacement δ of the component 1 becomes “0”.

On the other hand, in the logical symbol of the component number 2, "2", "2", "300", "160", "14" are stored in the registers 30 to 35, respectively.
Since 0 "and" 80 "are stored and the comparators 36, 39 and 40 all output" 1 ", the output of the AND circuit 41 also becomes" 1 "and the selection circuit
The 42 selects “60” which is the output of the subtractor 38 and outputs it as the displacement amount δ.

The displacement information δ is stored in the displacement storage unit 18 in the form as shown in FIG. 7, for example. When the displacement information is stored, the displacement setting unit 12 outputs a displacement setting end signal to the wiring processing unit 13.

When the displacement setting end signal is input, the wiring processing unit 13 stores the connection information of the logic circuit stored in the connection information storage unit 15, the placement information stored in the placement information storage unit 16, and the pin position information storage. Pin position information stored in section 17,
The displacement information stored in the displacement storage unit 18 is read, and the number of wirings and the coordinates of the start point and the end point of each wiring are obtained.

In this example, the wiring from the output of the 2-input OR arranged in the section (1,2) to the input 1 of the 2-input AND arranged in the section (3,2) and the section arranged in the section (1,1) Inverter 3
It is necessary to have two wires from the output of 2 to the input 2 of 2 input AND arranged in the section (3, 2). Compartment (Xs, Ys)
The starting point coordinates (xs, y) of the wiring that connects the logical symbol placed in the section and the logical symbol placed in the section (Xe, Ye)
s) and the end point coordinates (xe, ye) can be obtained by the following formula, where (xsp, ysp), (xep, y
ep) is the pin position information on the output side and the input side, and δs and δe are the displacements of the logical symbols on the output side and the input side.

xs = 300. (Xs-1) + xsp ... (1) ys = 300. (Ys-1) + ysp + δs ... (2) xe = 300. (Xe-1) + xep ... (3) ye = 300. (Ye-1) ) + Yep + δe (4) Once the start and end points of the wiring have been obtained, the wiring processing unit 13
Determines the wiring route. The wiring information is stored in the wiring information storage unit 19 in the form as shown in FIG. 8, for example. When the wiring information is stored, the wiring processing unit 13 sends a wiring end signal to the display processing unit 14.

When the wiring output signal is input, the display processing unit 14 first
The arrangement information is read from the arrangement information storage unit 16, and the symbol coordinate (x, y) of the logical symbol arranged in the section (X, Y) is calculated by the following formula.

x = 300 · (X−1) (5) y = 300 · (Y−1) + δ (6) When the coordinates of all the logical symbols are obtained, the display processing unit 14
Reads the shape of the type of the logical symbol from the symbol shape storage unit 20 based on the type of the logical symbol in the arrangement information. The symbol shape storage unit 20 stores data of all symbol shapes. When the symbol shape is read, the display processing unit 14 displays the symbol shape with the symbol coordinates calculated by the equations (5) and (6) as the origin. Finally, the display processing unit 14 includes the wiring information storage unit 19
The wiring information is read out and wiring is added to the displayed logic symbol to display it in the form of a connected logic circuit.

The circuit obtained by the above processing is shown in FIG. Since there is no bent portion in the connection between the 2-input OR output and the 2-input AND input 1, a drawing that is easier to see and looks better than the conventional one is generated. Moreover, the stored information is only the displacement information of each logical symbol as compared with the conventional one, and the information amount does not increase significantly.

The present invention is not limited to the above embodiment. For example, in the above-described embodiment, the logical symbol is displaced within the range of one section. However, when there is no other logical symbol or wiring in the adjacent section, the logical symbol is displaced beyond one section. It is also possible. Further, for example, when one output side logical symbol is connected to two input side logical symbols, the output side logical symbol is arranged at an intermediate position in the vertical direction between the two input side logical symbols. It is also possible to displace the logical symbols.

[Effects of the Invention] As described above, according to the present invention, since the logic symbol is displaced from the reference position within the section, it is possible to create a logic circuit drawing that is easy to see and looks good, and only displacement information is redundant. It suffices to store the data in the partition, and the advantages of high-speed processing and low storage capacity, which are the advantages of the intra-partition layout method, are not lost.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a logical drawing automatic generation device according to an embodiment of the present invention, FIG. 2 is a diagram showing connection information stored in an information storage section of the same device, and FIG. 3 is the same device. 4 is a diagram showing the arrangement information stored in the arrangement information storage unit in FIG. 4, FIG. 4 is a diagram showing the pin position information stored in the pin position information storage unit in the same device, and FIG. 5 is the shape and pin position of each logical symbol. FIG. 6 is a diagram showing an example of information, FIG. 6 is a more detailed block diagram of a displacement setting unit in the device, FIG. 7 is a diagram showing displacement information stored in a displacement storage unit in the device, and FIG. 8 is the device. FIG. 9 is a diagram showing wiring information stored in a wiring information storage unit in FIG. 9, FIG. 9 is a diagram showing a logic circuit drawing generated by the device, FIG. 10 is a diagram showing an example of the logic circuit, and FIG. 11 is a drawing. Fig. 12 is a diagram showing a partitioned state, and Fig. 12 is a conventional logic circuit drawing It is a diagram illustrating a logic circuit diagram that is generated by the device. 11 ... Arrangement processing unit, 12 ... Displacement setting unit, 13 ... Wiring processing unit, 14 ... Display processing unit, 15 ... Connection information storage unit, 16 ...
Arrangement information storage unit, 17 ... Pin position information storage unit, 18 ... Displacement storage unit, 19 ... Wiring information storage unit, 20 ... Symbol shape storage unit, 30 to 35 ... Register, 36, 39, 40 ... … Comparator, 3
7,38 ... Subtractor, 41 ... And circuit, 42 ... Selection circuit.

Claims (2)

[Claims] 1. A plurality of logical symbols are arranged in a unit of division on a drawing divided into n × m (n and m are arbitrary natural numbers), and connection processing is performed between the arranged logical symbols. In a logic circuit drawing generation device for generating a logic circuit drawing, a means for setting a displacement amount of the logic symbol from a reference position within a section based on input / output relational positions between connected logic symbols, and a means for setting the displacement amount by this means. And a means for storing the displacement amount and a means for arranging the logic symbol by displacing the logic symbol by the displacement amount from the reference position. 2. The means for setting the displacement amount comprises first comparing means for comparing the vertical partition position of the logical symbol of interest with the vertical partition position of the logical symbol to which it is connected, and the vertical partition position. First subtracting means for subtracting the vertical size of the logical symbol of interest from the vertical size, and the vertical division of the input pin of the logical symbol of the connection destination from the vertical internal coordinates of the output pin of the logical symbol of interest Second subtraction means for subtracting the in-section coordinate of the direction and second comparison means for comparing whether or not the subtraction result by the second subtraction means is greater than 0 and less than or equal to the subtraction result by the first subtraction means And the comparison result by the first comparing means is the same, and the second comparing means
Selection means for selecting the subtraction result by the second subtraction means as the vertical displacement when the comparison result by the comparison means is within the range, and selecting "0" as the vertical displacement otherwise. The logic circuit drawing generation device according to claim 1, further comprising: