JPH0740221B2 - Floating-point representation number sign determination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention (Field of Industrial Application) The present invention relates to a method for determining the sign of a calculation result in a floating-point numerical value calculator of a digital computer.

(Prior Art) Among the numerical representation formats inside a digital computer, the floating-point representation that represents an indefinite digit in a fixed-length area is
Although it cannot be expressed exactly, it is generally called a real number type because it can efficiently handle extremely small real numbers to extremely large real numbers, and it is mainly used in fields such as scientific and technological computing. The real number type numerical value is composed of a 1-bit code, an exponent part of 1 bit or more, and a mantissa part of 1 bit or more.

On the other hand, the fixed-point representation that expresses a fixed-digit number in a fixed-length area gives a range of numbers that can be represented, but it is generally called an integer type because it can be expressed exactly with respect to integers. It is used in the field of business calculation.
The integer type numerical value is composed of a 1-bit code and a 1-bit or more numerical value part.

Normally, the arithmetic unit outputs a state identification signal indicating the sign of the arithmetic result, which is used as a criterion for the subsequent conditional branch instruction. In the conventional arithmetic unit, the zero state identification signal is generated, and as shown in FIG. 2, the logical sum of all bits 22 excluding the sign bit 21 of the output of the arithmetic unit 10 is negated to obtain the total operation result. When the bit has the logical value 0, the logical value 1 of the zero state identification signal is used. This is because both the real number type and the integer type numerical expression forms represent the numerical value 0 with a state in which all bits of the area are logical values 0. In the integer type operation, since a strict numerical expression is possible, the operation result and the zero-state identification signal match in the mathematical sense.
However, even if mathematically zero, a real number type operation result rarely becomes an accurate numerical value 0 due to a rounding error, and in many cases, in the conventional state identification signal generation method, the zero state identification signal is generated. Has a disadvantage that the state identification signal of the calculation result does not always reflect the mathematical meaning.

Since the above calculation result is usually an extremely small numerical value, in actual programming, a certain small constant (estimation error) depending on the calculation is set, and an operation to judge zero for numerical values less than the constant is added. It has become common practice to do so. Specifically, the following procedure is performed in consideration of the sign of the calculation result.

(1) The calculation result is stored in a temporary variable, (2) the absolute value of the numerical value of the variable is obtained using an arithmetic unit, and stored again, (3) the arithmetic unit is again used to compare with the above constant, or Subtraction is performed, and (4) it is determined whether or not it is zero according to the sign of the result.

As described above, in the conventional computer, in order to determine whether or not the arithmetic result of the real number is zero in the mathematical sense, (1) the arithmetic unit must be used three times.

(2) A mathematically unnecessary procedure is required.

There was a drawback.

(Problems to be Solved by the Invention) The present invention has been made in view of the above circumstances, and when the sign of the operation result is determined, an integer type is known at the end of the operation. Regardless, the real type has to solve the problem that it has to be further operated, and for that reason, mathematically unnecessary procedures must be programmed.

An object of the present invention is to provide a code determination method for floating-point representation values that eliminates these drawbacks.

[Structure of Invention]

(Means for Solving Problems) The present invention is basically to perform the above procedure by hardware rather than programming. The present invention is a means for taking an absolute value of a calculation result of a floating point arithmetic unit,
Means for comparing the value of the calculation result and the value of the expected error register (ε register), a logic circuit for generating a state identification signal from the comparison result and the sign bit, and means for making a condition determination based on the state identification signal. And means for giving a value to the ε register.

As a means for taking the absolute value, it is not necessary to use an arithmetic unit, and the sign bit of the floating point representation may be simply removed.

As a means for performing size comparison, a floating point value subtractor is not necessary, and an integer value comparator can be used. This takes advantage of the fact that the floating point representation format used in the IEEE standard and IBM computers uses a biased representation for its exponent part. In other words, the comparison of two real numbers has the property that the magnitude comparison is made by comparing the absolute value representations (MSB to exponent part and mantissa part in this order) excluding the sign bit in the same manner as integers. To use.

As a means for producing a positive / negative zero state identification signal based on the output of the integer comparator and the sign bit, the following logic circuit for performing a simple 1-bit logical operation is used. This circuit
When the output of the integer comparator indicates (computation result) <(ε register), a zero state signal is output. When (computation result) ≥ (ε register), it follows the value of the sign bit, and when it is positive, it indicates the positive state. It outputs a signal and, when negative, a negative state signal.

The state identification signal is taken into the state identification register of the computer and used for the subsequent condition judgment instruction, but the means therefor is known and will not be described in detail.

As a means for setting the prediction error in the ε register, an ε register set instruction and a logic circuit for decoding the instruction and generating a set signal are used as in the case of a normal register.

By using the means as described above, the positive / negative zero state identification signal considering the error can be output at the same time as the output of the floating point arithmetic unit, and the above-mentioned problems are solved.

(Operation) First, prior to the calculation, the user predicts the error that will be included in the calculation result, and sets the predicted error in the ε register. Next, an operation is performed, and the final operation result is immediately taken as an absolute value and compared with the ε register. A state identification signal is generated from the result of the comparison and is stored in the state identification register in preparation for a subsequent condition determination command.

By operating as described above, the positive / negative zero state identification signal in consideration of the error can be output at the same time as the output of the floating point arithmetic unit, and the above problems are solved.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

First, the user predicts an error that may be included in the calculation result and sets the maximum value regarded as zero in the ε register 1 before the calculation. As a means for setting the prediction error in the ε register, the ε register set instruction is executed by a program, as in the case of a normal register.
The control unit 7 decodes the instruction, generates a set signal for the ε register 1, and sets the predicted error value in the ε register 1.

Next, the calculation is performed. Here, similarly to the conventional computer, the control unit 7 fetches necessary data from the storage device 8 according to the instruction of the program and gives it to the floating-point numerical value arithmetic unit 10 together with the operation instruction to perform the operation. The arithmetic operation uses the arithmetic unit 10 once or a plurality of times according to the request of the program. When it is used a plurality of times, the same means as the conventional computer is taken, such as temporarily storing the intermediate result appearing in the output 2 of the arithmetic unit in the storage device 8.

When the final calculation result appears at the calculator output 2, the calculation result is stored in the storage device 8 and the exponent part and the mantissa part excluding the sign, that is, the absolute value 22 of the final calculation result is an integer comparator. The sign bit 21 of the operation result is supplied to the A input of 3 to the state identification signal generator 5. The absolute value 22 is compared with the value of the ε register 1 given to the B input by the integer comparator 3, and the comparison result 4 is supplied to the state identification signal generator 5. By the way, the comparison result 4 is the logical value 1 when A <B.
give.

In the state identification signal generator 5, each state identification signal is generated as follows.

(1) The positive state identification signal 61 is generated as a logical product of the logical NOT of the integer comparator output 4 and the logical NOT of the sign bit 21 of the arithmetic unit output. That is, since the final calculation result 2 is a positive value larger than the value of the ε register 1, it is identified as positive.

(2) The negative state identification signal 62 is generated as the logical product of the logical negation of the integer comparator output 4 and the sign bit 21 of the arithmetic unit output. That is, since the final operation result 2 is a negative value whose absolute value is larger than the value of the ε register 1, it is identified as negative.

(3) The zero state identification signal 63 outputs the integer comparator output 4 as it is. That is, since the absolute value 22 of the final calculation result is smaller than the value of the ε register 1, it is identified as zero.

State identification signal generated in state identification signal generator 5
61, 62 and 63 are stored in the state identification register 9 in preparation for the subsequent condition judgment command.

The time required to determine the state identification signals 61, 62, 63 after obtaining the operation result 2 is the propagation delay inside the integer comparator 3 and the state identification signal generator 5, and the final operation results that proceed at the same time. 2 is shorter than the storage time in the storage device 8. Therefore, the positive / negative zero state identification signals 61, 62, 63 considering the error are stored in the state identification register 9 at the time when the arithmetic processing including the result storage in the storage device 8 is completed.

By the above operation, it is understood that the positive / negative zero state identification signal in consideration of the error can be output at the same time when the floating point arithmetic is completed.

〔The invention's effect〕

Therefore, according to the present invention, the sign such as positive and negative zero of the operation result is found at the end of the operation of the floating point value, and it is possible to practically compare two real number type values by using the operation unit once. In addition, since the mathematical meaning and the operation of the computer match, there is no need to do unnecessary coding from the viewpoint of programming, the probability of making an error is reduced, a good quality program can be created, and the program itself is shortened. The effect is obtained.

In particular, when the present invention is applied to a vector computer having an index set and a vector computer having a mask vector described in Japanese Patent Application No. 57-28905, "Index Limited Continuous Operation Vector Processor", a remarkable effect can be seen. In these computers, in order to vectorize the iterative control including condition determination, a series of data is previously calculated and the result is used for determination. What is important here is not the calculation result but the judgment result.

According to the present invention, since the condition judgment is finished at the same time as the storage of the calculation result, there is no need to judge the calculation result again, and the speed can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention, and FIG. 2 is a logic diagram of a conventional state identification signal generating circuit. 1 …… Prediction error register (ε register) 2 …… Calculator output 21 …… Calculator output sign bit 22 …… Calculator output absolute value (exponent part, mantissa part) 3 …… Integer comparator 4 …… Integer comparison Output 5 …… Positive / negative zero discrimination signal generator considering error 61 …… Positive discrimination signal considering error 62 …… Negative discrimination signal considering error 63 …… Zero discrimination signal considering error 7 …… Control section 8: Storage device 9: State identification register 10: Floating point numerical value calculator

Claims (1)

[Claims] 1. A floating point arithmetic unit, a prediction error register for storing an error value expected to be included in a result of a floating point arithmetic operation, an absolute value of an output of the floating point arithmetic unit and the prediction error. An integer comparator that compares the error value stored in the register, and a zero state as the state identification signal of the operation result when the comparison result by the integer comparator indicates that the absolute value is smaller than the error value. A logic circuit which outputs a signal and outputs a positive state signal or a negative state signal according to the positive or negative of the operation result when the comparison result by the integer comparator indicates that the absolute value is larger than the error value. An apparatus for determining a sign of a floating-point expression value, which is characterized in that