JPH0738890A - Method and circuit for encoding dynamic image - Google Patents

Abstract

PURPOSE:To control the insertion of macroblocks by a simple circuit by selecting a number (n) which is mutually prime with the number of macroblocks in a frame and performing forcible in-frame encoding at intervals of (n) macroblocks. CONSTITUTION:When a macroblock(MB) start signal is inputted, the MB start signal increments the count value of an MB counter 101 by one unless a reset input is active. A 130 detecting circuit 102 inputs the count value of the counter 101 and outputs a forcible in-frame encoding signal which becomes active only when the count value is equal to 130. This request signal is outputted to the outside and also inputted to an AND gate 103. This request signal is inputted to the other input of the gate 103 and only when the MB start signal is active, the gate 103 is turned ON to send the signal to the reset input of the counter 101 through an OR gate 104, thereby resetting the count value output of the counter 101 to 0.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture coding method and a circuit for coding moving picture data, and more particularly to a moving picture code for adaptively switching between intraframe coding and interframe predictive coding. Method and circuit.

[0002]

2. Description of the Related Art CC is used as a moving picture compression coding method.
The video coding standard H.264 of the ITT (International Telegraph and Telephone Advisory Committee) for video conferencing. 261 and ISO (International Organization for Standardization)
MPEG (Mov
ing Picture Expert Group) and the like, a method of adaptively switching between intraframe coding and interframe predictive coding to perform coding is currently the mainstream.

Intra-frame coding
Is an encoding method that encodes only information within the own frame, and inter-frame prediction encoding (inter-frame prediction
coding) is a method of obtaining a prediction value using another frame as a reference frame and encoding a difference between the current frame and the prediction value, that is, a prediction error.

In the coding of such a moving image, as shown in FIGS. 7 and 8, one frame of image data is divided into 16 pixels ×
It is divided into macroblocks each having a size of 16 pixels, coding processing is performed for each macroblock, and intraframe coding and interframe predictive coding are adaptively switched and coded for each macroblock.

FIG. 7 shows the SIF (Source
8 shows the format of the H.264 input format. Two
CIF set as the picture format in 61
This indicates the format of (Common Intermediate Format).

The image size is 35 in MPEG SIF.
2 pixels × 240 pixels, H.264 In the CIF of H.261, the number of pixels is 352 pixels × 288 pixels, and the processing order of macroblocks is H.264 in the order of processing from top left to bottom right of an image in MPEG as shown in FIG. In FIG. 261, as shown in FIG. 8, 11 macroblocks × 3 macroblocks are GOB.
Treated as a higher-level unit called (Group of block), GO
A macroblock is processed for each B. For this reason, H. 26
1 and MPEG are different in the order of processing macroblocks in a frame.

Interframe predictive coding encodes the prediction error between the input current frame and reference frame,
Although the coding efficiency is higher than the intra-frame coding, the difference between the reference frame in the encoding device and the reference frame in the decoding device accumulates due to the difference in calculation accuracy between the encoding device and the decoding device. There is a problem of going.

Therefore, in the moving picture coding system in which intraframe coding and interframe predictive coding are adaptively switched and coded for each macroblock, the interframe predictive code is applied to each macroblock in the frame. It is necessary to forcibly perform intraframe coding so that the coding does not continue for more than a certain number of frames.

H. 261 and MPEG stipulate that control is performed so that interframe predictive coding does not continue for 132 frames or more.

FIG. 6 is a block diagram showing a general structure of a moving picture coding circuit.

In general, the moving picture coding circuit includes a block scanning unit 502, a subtractor 503, and a selector 504.
, Information source coding unit 505, and entropy coding unit 5
06, a multiplexer 507, and a local decoding unit 408.
, Reference frame storage unit 509, and predicted value calculation unit 510
And a coding type determination unit 501.

The coding type determination unit 501 includes a forced intra-frame coding control unit 520 and a determination data generation unit 521.
And an adaptive coding type selection unit 522.

First, the operation of the coding type determining section 501 will be described.

The forced intraframe coding control unit 520 receives timing signals such as a frame start signal and a macroblock start signal and indicates whether the current macroblock should be forcibly intraframe coded. A coding request signal is generated and output to the adaptive coding type selection unit 522.

The determination data generation unit 521 inputs the current macroblock data from the block scan unit 502 and the reference data from the reference frame storage unit 509, and based on these data, the current macroblock is interframe predictively coded. Judgment data for determining the coding type such as the estimated code amount between the case of performing the frame coding and the case of performing the frame coding are generated and output to the adaptive coding type selecting unit 522.

The adaptive coding type selection unit 522 inputs the frame coding type input from the outside. When the frame coding type is intra-frame coding, the coding type is selected for all macroblocks in the frame. Intraframe coding is selected as.

When the input frame coding type is interframe predictive coding, adaptive coding type selecting section 522 activates the forced intraframe coding request signal input from forced intraframe coding control section 520. In the case of, the intraframe coding is selected as the coding type of the current macroblock, and when the compulsory intraframe coding request signal is inactive, based on the determination data input from the determination data generation unit 521, The coding type determined to be the most suitable as the coding type of the current macroblock is selected, and the prediction type selection signal and the intra / interframe selection signal are output.

It should be noted that the determination of intra / inter frame (Intra / Inter
Judgment), ISO standard IS1117-2, Supplement (Appendix)
See the Intra / Inter decision method adopted in P-pictures of CCITT RM, MPEG SM3.

Next, the overall processing flow of the moving picture coding circuit shown in FIG. 6 will be described.

The block scanning unit 502 scan-converts the input image data, and determines the macroblock data according to the processing order.
The data is output to the determination data generation unit 521 in 01, and output to the subtractor 503 and the selector 504 after the encoding type is determined by the encoding type determination unit 501.

The subtractor 503 is a block scan unit 50.
The current macroblock data input from 2 and the prediction value input from the prediction value calculation unit 510 are subtracted, and the subtraction result data is output to the selector 504 as prediction error data.

The selector 504 has a coding type determining unit 5
In accordance with the Intra / Inter selection signal input from 01, either the current macroblock data input from the block scanning unit 502 or the prediction error input from the subtractor 503 is selected to select the source code. Conversion part 5
Output to 05.

The information source coding unit 505 has a selector 504.
The data input from is subjected to processing such as orthogonal transformation and quantization processing, and is output to the entropy coding unit 506 and the local decoding unit 508.

The entropy coding unit 506 performs coding for reducing the statistical redundancy such as zero run coding, Huffman coding or arithmetic coding on the data input from the information source coding unit 505, and pixel coding The data is output to the multiplexer 507.

The multiplexer 507 inputs the prediction type selection signal of the macro block and the intra-frame / inter-frame selection signal from the coding type determination unit 501, and a sub-code before the pixel code data input from the entropy coding unit 506. After outputting these pieces of information as secondary information according to a predetermined rule, pixel code data is output.

The local decoding unit 508 is the information source coding unit 5
The information source encoding unit 505 for the data input from 05.
The macroblock data or the macroblock prediction error data is restored by performing the opposite process to the process performed in the step (3), and the intraframe / interframe selection signal input from the coding type determination unit 501 indicates interframe coding. If it is, the predicted value data input from the predicted value calculation unit 510 is further added to restore the macroblock data and input to the reference frame storage unit 509.

The reference frame storage unit 509 stores the image data of one frame or more by sequentially storing the macroblock data restored by the local decoding unit 508, and stores the image data of one frame or more as the reference data of the current macroblock. The image data of a required portion of the frame encoded before the frame is cut out and first output to the determination data generation unit 521 in the encoding type determination unit 501, and the encoding type determination unit 5
In 01, after the coding type of the current macroblock is determined, it is output to the prediction value calculation unit 510.

Prediction value calculation section 510 follows reference frame storage section 5 according to the prediction type selection signal input from adaptive coding type selection section 522 in coding type determination section 501.
A prediction value is calculated from the reference data input from 09 and output to the subtractor 503 and the local decoding unit 508.

Coding of a moving image is executed according to the flow of processing as described above.

In the forced intraframe coding control unit 520 of the conventional moving picture coding circuit, first, the position of the macroblock to be forcibly intraframe coded is determined for each frame, and then, the current macro for each macroblock is determined. The position of the block is checked, and when the current macroblock position matches the position of the previously set macroblock, the compulsory intra-frame coded signal is generated.

FIG. 9 is a block diagram showing an example of a conventional configuration of the forced intraframe coding control unit of FIG.

This prior art example is a moving picture coding circuit for coding a moving picture of MPEG SIF format, and as shown in FIG.
By forcibly performing the intra-frame encoding on the macro block, all macro blocks in the frame are forcibly intra-frame encoded every 110 frames.

The configuration of a conventional moving picture coding circuit will be described with reference to FIG.

The forced intraframe coding control unit of the conventional example is
SR latch 751, horizontal position counter 701, 21
The detection circuit 711, the OR gate 721, the AND gate 731, the vertical position counter 702, and the 4 detection circuit 71.
2, an OR gate 722, an AND gate 732, and S
R latch 753, horizontal position counter 703, 21 detection circuit 713, OR gate 723, AND gate 7
33, a vertical position counter 704, and a 2 detection circuit 714
, OR gate 724, AND gate 734, vertical position counter 705, 4 detection circuit 715, OR gate 725, AND gate 735, and comparators 741 and 7
42 and an AND gate 743.

The SR latch 751 is an SR latch that is set when a system reset signal is input and is reset when a first frame start signal after the system reset signal is input.

The SR latch 753 is an SR latch that is set when a frame start signal is input and is reset when the first macroblock start signal after the frame start signal is input.

The horizontal position counter 701 and the vertical position counter 702 indicate the positions of macroblocks to be forcibly intraframe coded in the current frame and are updated for each frame.

The horizontal position counter 703, vertical position counter 704, and vertical position counter 705 indicate the position of the current macroblock and are updated for each macroblock.

As shown in FIG. 11, the horizontal position counter 7
Count value 1 which is the output of 01 and the horizontal position counter 70
The count value 3 that is the output of 3 is the horizontal position of the macroblock, and the count value 2 that is the output of the vertical position counter 702 and the count value 5 that is the output of the vertical position counter 705 are in units of 3 macroblocks. The vertical position is shown.

The vertical position counter 704 is used to count up the vertical position counter 705 in units of three macro blocks in the vertical direction.

Next, the operation of the conventional forced intraframe coding control unit will be described.

First, the update timing of the count values of the horizontal position counter 701 and the vertical position counter 702 will be described.

The system reset signal is a signal that is active before starting the moving image coding process and is inactive from beginning to end during the moving image coding process.

The system reset signal is the SR latch 75.
It is connected to the set signal of 1, and the SR latch 751 is set to 1 when the system reset signal is input.

The output of the SR latch 751 is the OR gate 7.
21 is connected to the reset signal of the horizontal position counter 701 via 21 and resets the horizontal position counter 701 to 0, and is also connected to the reset signal of the vertical position counter 702 via the OR gate 722. The position counter 702 is reset to 0.

The frame start signal is connected to the reset signal of the SR latch 751. The latch 751 is reset by the first frame start signal input after being set by the system reset signal.

After the reset, the moving image coding process is executed, and the system reset signal is inactive during this period.

The frame start signal is input before processing the frame.

The frame start signal is input to the count pulse signal of the horizontal position counter 701, and the output of the OR gate 721 is connected to the reset signal of the horizontal position counter 701. One input of the OR gate 721 is connected to the SR latch 751 and the other input is AND
It is connected to the output of the gate 731.

A frame start signal is connected to one input of the AND gate 731, and the other input is connected to the 21 detection circuit 7.
It is connected to the output of 11.

The 21 detection circuit 711 inputs the count value 1 which is the output of the horizontal position counter 701, and the value is 2
It outputs a signal that becomes active only when it is equal to one.

Therefore, the reset signal of the horizontal position counter 701 becomes active only during the period from the input of the system reset signal in which the SR latch 751 outputs 1 to the input of the first frame start signal, and the frame start. This is when the next frame start signal is input after the count value 1 is counted up to 21 by the signal.

When the frame start signal is input while the reset signal of the horizontal position counter 701 is inactive, the count value 1 is incremented by 1.

By the above operation, the count value 1 is as shown in FIG.
It is updated by the frame start signal input as shown in 0 (a). In the timing chart of FIG. 10A, the outputs from 1 to 19 of the count value 1 are omitted.

The count value 1 becomes a cyclic counter that cycles through the values 0 to 21. However, when the first frame start signal is input after the system reset signal, the SR latch is still active, and the horizontal position counter 701 is
Is not counted up, and the count value 1 remains 0.

Vertical position counter 702 and 4 detection circuit 7
12, the OR circuit 722, and the AND circuit 732, the horizontal position counter 701, the 21 detection circuit 711.
The OR gate 721 and the AND gate 731 have exactly the same configuration. Regarding the signal connection, the horizontal position counter 701 and the counting pulse signal are connected to the frame start signal, whereas the vertical position counter is connected. The count pulse signal of 702 is the same except that the output of the AND gate 731 is connected.

The output of the AND gate 731 becomes active when the count value 1 is reset from 21 to 0 by the frame start signal input.

Therefore, the count value 2 is as shown in FIG.
As shown in (a), it is a cyclic counter that cycles through the values 0 to 4 and is updated when the count value 1 is reset from 21 to 0. It should be noted that the code a of the count value 2 in FIG. 10A is from 0 to 4 when 5 is a modulo.
Is one of.

The update timing of the count values of the horizontal position counter 703, the vertical position counter 704, and the vertical position counter 705 is the same as the update timing of the count values of the horizontal position counter 701 and the vertical position counter 702.

That is, as shown in FIG. 10B, the horizontal position counter 703 (count value 3) operates as a cyclic counter that cycles from 0 to 21 when a macroblock start signal is input.

The vertical position counter 704 (count value 4) operates as a cyclic counter that cycles through the values 0 to 2 that are updated when the count value 3 is reset from 21 to 0. The counter 705 (count value 5) operates as a cyclic counter that cycles through the values 0 to 4, which is updated when the count value 4 is reset from 2 to 0. Note that FIG. 10 (b)
The code b of the count value of 5 is 0 to 4 with 5 as a modulus (Modulo).

By the above operation, as shown in FIG.
Count value 1 and count value 3 indicate horizontal positions, and count value 2 and count value 5 indicate vertical positions in units of 3 macroblocks.

The comparator 741 inputs the count value 1 and the count value 3, and outputs a signal which becomes active when these values are equal to the AND gate 743.

The comparator 742 inputs the count value 2 and the count value 5, and outputs a signal which becomes active when these values are equal to the AND gate 743.

The AND gate 743 outputs a signal which becomes active when both the output of the comparator 741 and the output of the comparator 742 are active, as a compulsory intra-frame coding request signal.

Therefore, the compulsory intra-frame coding request signal has the count value 3 at the macro block position forcibly intra-coded in the current frame, that is, the macro block position designated by the count value 1 and the count value 2.
And becomes active when the current macroblock position indicated by the count value 5 matches.

With this signal, as shown in FIG. 5, the macroblock is forcibly intraframe-coded in units of three blocks in the vertical direction for each frame.

[0068]

In the above-described forced intraframe coding control of the conventional moving picture coding circuit, first, the position of the macroblock to be forcibly intraframe coded is determined for each frame, and then, In addition, the position of the current macroblock is checked for each macroblock, and when the current macroblock position matches the position of the previously set macroblock, the macroblock is forcibly encoded by intraframe coding. An intra-coded macroblock was inserted.

Therefore, a plurality of counters are required to forcibly determine the position of the macroblock to be intraframe-coded and to check the position of the current macroblock, and the previously determined forcible intraframe-code is required. This requires a comparator for detecting that the position of the macroblock to be converted and the position of the current macroblock match, which causes a problem that the circuit scale becomes large.

Further, as shown in FIG. 5, in the conventional forced intra-frame coding control method, the forced intra-frame coding macroblock monotonously moves within the frame, so that the movement can be visually followed. There is a drawback that the reproduced image becomes unnatural.

Therefore, the present invention solves the above-mentioned problems and forces the intra-frame coding in a moving picture coding circuit that adaptively switches between intra-frame coding and inter-frame coding for each macroblock. An object of the present invention is to provide a moving picture coding method and circuit for realizing insertion control of a macroblock to be coded by a simple circuit.

[0072]

In order to achieve the above object, the present invention provides a hybrid moving picture coding method in which intraframe coding and interframe predictive coding are adaptively switched and coded. Is a predetermined integer that is coprime to the number of macroblocks in a frame, and a macroblock is forcibly coded every n macroblocks by intraframe coding. .

Further, according to the present invention, in a moving picture coding circuit which adaptively switches between intraframe coding and interframe predictive coding to perform coding, the integer n is set to a predetermined number which is relatively prime to the number of macroblocks in the frame. A first means for counting macroblocks and generating an active signal for every n macroblocks, whichever is suitable for coding among intraframe coding and interframe predictive coding. The second means for selecting one of the encodings and the second means for encoding the macroblock when the signal generated by the first means is not active.
And a third means for selecting intraframe coding when the signal generated by the first means is active, the selection result of the means of FIG. To do.

[0074]

The operation of the present invention will be described below.

According to the present invention, if the number of macroblocks in a frame and the number n which are relatively prime to each other are selected, the intraframe coding is forcibly performed for every n macroblocks. The fact that the intra-frame coding is forcibly performed every time and the same macroblock is forcibly intra-coded at the n-frame cycle is used.

That is, the inventor of the present invention modifies an integer m modulo (m
odulo), if the integer n is relatively prime to m, then as a remainder of a multiple of n (where l = 0 to m−1), all the remainders 0 to m−1 The present invention has been completed by finding that the occurrence of each of these can be utilized for moving picture coding. In the present invention, the m corresponds to the number of macroblocks in the frame, and the remainder corresponds to the macroblock position in the frame.

For the sake of explanation, if m = 12 and n = 5, for example, a multiple of 5: 0, 5, 10, 15, 20, 25, 30, 3
5, 40, 45, 50, 55, 60, 65, ... Remainders (modulo divided by 12) modulo m = 12 are 0, 5, 10, 3, 3, 8, 1, 6, 11, respectively. 4, 9, 2,
7,0,5, ..., and 12 remainders of 5 × l (l = 0 to 11) are obtained.
You can see that 0-11 all appear once.

By the way, when divided into frames each consisting of the macroblock number m = 12, (0, 5, 10), (3,
8), (1, 6, 11), (4, 9), (2, 7),
It becomes (0, 5, 10), and it can be seen that the same pattern appears in the frame in 5 frame cycles.

Conventionally, first, the position of a macroblock for which intra-frame coding is forcedly performed is determined for each frame, and then,
Check the position of the current macroblock for each macroblock,
While the current macroblock position matches the position of the previously determined macroblock, the insertion of the forced intraframe-encoded macroblock is controlled by forcibly intracoding the macroblock. , In the present invention,
Controlling insertion of a forced intra-frame coding macro block by simply generating a signal that becomes active for every n macro blocks and forcibly intra-coding the macro block when the signal becomes active Is.

[0080]

Embodiments of the present invention will now be described with reference to the drawings.

The present invention relates to a method for forcibly deciding a macroblock to be intraframe-encoded so as to prevent interframe predictive encoding from being too continuous for each macroblock in a frame, and a circuit for realizing the method. It is a thing.

In the embodiment of the present invention, the configuration of the forced intra-frame coding control unit 520 of the conventional moving picture coding circuit shown in FIG. 6 is different from the conventional construction, but the moving picture coding circuit The overall processing flow is the same as that of the conventional moving picture coding circuit, and therefore its explanation is omitted. Therefore, the configuration and processing of the compulsory intra-frame coding control unit in the moving picture coding circuit of this embodiment will be described in detail below.

[0083]

First Embodiment FIG. 1 is a block diagram showing the configuration of a forced intraframe coding control unit of a moving picture coding circuit according to a first embodiment of the present invention.

This embodiment is for forced intraframe coding of macroblocks for every 131 macroblocks.

In the case of H.264, the number of macroblocks in a frame 330 in the SIF format of MPEG is H.264.
The number of macroblocks 396 in the frame in the case of the CIF format of 261 is also a prime number.

Since 131 is a prime number, the above 33
Even if the image size is the number of macro blocks other than 0 and 396, unless the number of macro blocks in a frame is a multiple of 131, the number of macro blocks is always relatively prime.

In this embodiment, the macroblock counter 10 is used.
1, 130 detection circuit 102, AND gate 103
And an OR gate 104. The macroblock counter 101 is a binary 8-bit counter.

Next, the operation will be described.

The system reset signal is a signal which is active before the moving picture coding processing is started and is inactive during the moving picture coding processing from beginning to end.

When the system reset signal is input, O
Macro block counter 1 via R gate 104
01 reset input, macroblock counter 1
The count value output of 01 is reset to 0.

After that, the moving picture is encoded, and the system reset signal is inactive during that time.

When the macroblock start signal is input,
The macroblock start signal is the macroblock counter 1
Since it is connected to the count pulse input of 01, the count value output of the macroblock counter 101 is incremented by 1 if the reset input is not active.

The detection circuit 102 inputs the count value of the macroblock counter 101, and the value is 130
Outputs a forced intra-frame coding request signal which becomes active only when Eq.

The compulsory intra-frame coding request signal is output to the outside and also to the AND gate 103.

The compulsory intraframe coding request signal is ANDed.
Only when the macroblock start signal input to the other input of the gate 103 is active, the AND gate 103 is turned on, is sent to the reset input of the macroblock counter 101 via the OR gate 104, and is sent to the reset input of the macroblock counter 101. The count value output is reset to 0.

By the operation described above, the macroblock counter 101 outputs the compulsory intraframe coding request signal for each 131 macroblocks, as shown in FIG.
With this compulsory intra-frame encoding request signal, intra-frame encoding is compulsorily performed for each 131 macroblocks as shown in FIG.

[0097]

[Embodiment 2] FIG. 3 is a block diagram showing a configuration of a forced intra-frame coding control unit of a moving picture coding circuit according to a second embodiment of the present invention.

This embodiment is the same as the first embodiment except that
Instead of the 8-bit counter that generates the compulsory intra-frame coding request signal for each 131 macroblocks, an 8-bit linear feedback shift register (Linear Fe
edback shift register; also referred to as “LFSR”).

The 8-bit linear feedback shift register is a shift register that outputs the same bit pattern in a maximum of 2 ⁸ −1 = 255 cycles, and is used here as a 131-cycle cyclic counter.

The linear feedback shift register shown in FIG. 3 has Galois field F _q = GF (q), where q =
2, polynomial with the above elements as coefficients X ⁸ + X ⁶ + X ⁵ + X ⁴ +1
And the initial value “1” is 10 at the time of counting 131.
It has been confirmed to output a decimal number 25 (for example,
(See Hiroshi Miyagawa, Yoshisuke Iwadare, Hideki Imai, "Code Theory", Shokodo, Computer Basic Course, Vol. 18, 1973).

In this embodiment, eight data flip-flops 201 to 208 and data flip-flops 201 to 208 are provided.
208 Selector 21 connected to each data input
1-218 and three exclusive OR gates 231-233
, 25 detection circuit 241, AND gate 234, O
R gates 235 and 236 are provided.

In the 25 detection circuit 241, the values of the eight data flip-flops 201 to 208 make the output data of the data flip-flop 208 the most significant bit (MSB),
The output data of the data flip-flop 201 is an 8-bit positive binary data having the least significant bit (LSB) as
When 25 (= 00011001), this is detected and an active signal is output.

Data flip-flops 201-208
Is a flip-flop with enable, which latches the input data when the enable signal becomes active.

Next, the operation of the linear feedback shift register will be described.

The system reset signal is a signal which is made active before starting the moving image coding process and is made inactive all the time during the moving image coding process.

When the system reset signal is input, O
The selection signals of the selectors 211 to 218 are activated via the R gate 236, and the selector 211 sets “1” to the data flip-flop 201 and the selectors 212 to 212.
Reference numeral 218 denotes data flip-flops 202-2, respectively.
“0” is output to 08.

Further, since the system reset signal is input to the enable signals of the data flip-flops 201 to 208 via the OR gates 235 and 236, the output data of the selectors 211 to 218 are respectively connected to the connected data flip-flops. The data flip-flop 201 is "1" because it is latched by the data sets 201 to 208.
However, the data flip-flops 202 to 208 have "0".
Is latched.

After that, it is assumed that the moving image is coded and the system reset signal is inactive during the coding.

When the system reset signal is inactive, the OR gate 235 connected to the enable signals of the data flip-flops 201 to 208 conducts and outputs the macro block start signal, which is one of the inputs, as it is. The data of groups 201 to 208 are updated only when the macroblock start signal becomes active.

When the forced intra-frame coding request signal output from the 25 detection circuit 241 is inactive when the macroblock start signal becomes active, the OR gate 2 connected to the selection signals of the selectors 211 to 218.
The output of 35 becomes inactive, and the selector 211
Are data flip-flops 208, 204, 20 obtained by exclusive OR gates 231, 232, 233.
1, which is the exclusive OR of the four output data of 3,202
The bit is output to the data flip-flop 201.

Selectors 212 to 218 output the output data of data flip-flops 201 to 207 to data flip-flops 202 to 208, respectively. At this time, when the macroblock start signal is input, the macroblock start signal is input to the enable signals of the data flip-flops 201 to 208 via the OR gate 236. Therefore, the data flip-flop 201 is input to the data flip-flop 201. 208,204,203,202
1-bit data which is the exclusive OR of the four output data of
208 includes data flip-flops 201 to 201, respectively.
The output data of 207 is latched.

If the forced intra-frame coding request signal output from the 25 detection circuit 241 is active when the macroblock start signal becomes active, the selector 2
OR gate 235 connected to the selection signals of 11 to 218
Output becomes active, and the selector 211 outputs "1" to the data flip-flop 201. Then, the selectors 212 to 218 output “0” to the data flip-flops 202 to 208.

The macroblock start signal is OR gate 2
Data flip-flops 201-208 via 36
The data flip-flop 201 is latched with “1” and the data flip-flops 202 to 208 are latched with “0”.

The 25 detection circuit 241 outputs the output data of the eight data flip-flops 201 to 208 and the output data of the data flip-flop 208 to the most significant bit (MS
B), input the output data of the data flip-flop 201 as 8-bit positive binary number data with the least significant bit (LSB), and activate only when the value is equal to 25 (decimal number) Output an encoding request signal.

The forced intra-frame coding request signal is output to the outside and also to the AND gate 234.

The number of 25 detected by the 25 detection circuit 241 is the same as the timing at which the macroblock counter of the first embodiment outputs the count value 130.
It is a value output by the data flip-flops 201 to 208. Therefore, this linear feedback shift register operates as a 131-cycle cyclic counter.

With the above operation, as in the first embodiment, the linear feedback shift register shown in FIG. 3 is used to output the compulsory intra-frame encoding request signal for each 131 macroblocks and compulsorily. Is intra-frame coded.

The 8-bit counter is realized by an 8-bit latch and an incrementer, while the linear feedback shift register is realized by an 8-bit latch and three exclusive OR gates. Since it can be realized, the circuit scale can be reduced by replacing the incrementer with three exclusive OR gates.

In the first and second embodiments, the present invention has been described above based on the example in which the intra-frame coding is forcibly performed every 131 macro blocks. Of course, the prime integer n can be replaced with a number other than 131.

Further, FIG. 4 shows an embodiment of the present invention.
Although the position of the compulsory intra-frame coding macroblock in the SIF format of MPEG is shown, the position of the H.264 standard is not shown. 261
In the CIF format of No. 2, since the order of processing of the macroblocks is different, only the location of the macroblock that is forcibly intra-frame coded is different from the SIF format of MPEG, and just like the case of MPEG,
It is possible to control the forced intra-frame coding.

[0121]

As described above, in the conventional forced intra-frame coding control of the moving picture coding circuit, the forced intra-frame coding is performed by using a plurality of vertical position and horizontal position counters and a circuit structure such as a comparator. In contrast to the insertion of the coded macroblock, the present invention simply generates a signal that becomes active every n macroblocks and forces the macroblock when that signal becomes active to be intraframe-coded. By doing so, the insertion of the forced intra-frame coding macroblock can be controlled, so that the forced intra-frame coding control circuit can be realized by one 8-bit counter or 8-bit linear feedback shift register. It has a special effect of simplifying and greatly reducing the circuit scale.

Further, as shown in FIG. 5, in the conventional forced intra-frame coding control method, the forced intra-frame coding macroblock monotonously moves within the frame, so that the motion can be visually followed. In contrast to the problem that the reproduced image becomes unnatural, the forced intra-frame coding control method of the present invention has the forced intra-frame coding macroblocks dispersed in the frame, and Since there is a large change in the location every time, the forced intra-coded macroblock is not noticeable, and this has the advantage of achieving an apparent improvement in image quality.

Further, in the present invention, when an 8-bit linear feedback shift register is used as a counter for forcibly controlling the intra-frame encoding for every n macroblocks, in addition to an 8-bit latch, Since it can be realized by three exclusive OR gates, the circuit scale can be further reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a forced intraframe coding control unit of a moving picture coding circuit according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation timing of a forced intraframe coding control unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a forced intra-frame coding control unit of the moving picture coding circuit according to the second embodiment of the present invention.

[Fig. 4] Fig. 4 is a diagram showing a transition of the position of a macroblock to be coded by forced intraframe according to the present invention.

FIG. 5 is a diagram showing a transition of a position of a macroblock to be subjected to forced intraframe coding in a conventional example.

FIG. 6 is a block diagram showing a configuration of a conventional general moving image encoding circuit.

FIG. 7 is a diagram showing a macroblock configuration of an MPEG SIF frame.

FIG. 8: It is a figure which shows the macroblock structure of a 261 CIF frame.

FIG. 9 is a block diagram showing an example of a forced intra-frame coding control unit of a conventional moving picture coding circuit.

FIG. 10 is a timing diagram showing an operation timing of a conventional forced intraframe coding control unit. (A) Horizontal position counter 701 and vertical position counter 7
FIG. (B) Horizontal position counter 703 and vertical position counter 7
It is a timing chart of 04 and 705.

FIG. 11 is an explanatory diagram showing the relationship between the position of a macroblock to be subjected to forced intraframe coding and a counter value in the conventional example.

[Explanation of symbols]

 101 Macroblock Counter 102 130 Detection Circuit 103 AND Gate 104 OR Gate 105 Prediction Value Calculation Unit 110 Memory Data Bus 201-208 Data Flip-Flop 211-218 Selector 24125 Detection Circuit 231-233 Exclusive OR Gate 234 AND Gate 235 , 236 OR gate 501 Coding type determination unit 502 Block scan unit 503 Subtractor 504 Selector 505 Information source coding unit 506 Entropy coding unit 507 Multiplexer 508 Local decoding unit 509 Reference frame storage unit 510 Prediction value calculation unit 520 Forced frame Inner coding control unit 521 Judgment data generation unit 522 Adaptive coding type selection unit 701 Horizontal position counter 702 Vertical position counter 703 Horizontal position counter 704 Straight position counter 705 the vertical position counter 711 21 detection circuit 712 fourth detection circuit 713 21 detection circuit 714 2 detector 715 4 detecting circuit 721 to 725 OR gate seven hundred and thirty-one to seven hundred thirty-five the AND gates 741, 742 comparator 743 the AND gate 751,753 SR latch

Claims (3)

[Claims] 1. A hybrid moving picture coding method in which intraframe coding and interframe predictive coding are adaptively switched and coded, and an integer n is a predetermined number that is relatively prime to the number of macroblocks in the frame. A moving picture coding method, which is an integer and forcibly codes a macroblock for every n macroblocks by intra-frame coding. 2. In a moving picture coding circuit for adaptively switching between intraframe coding and interframe predictive coding for coding, an integer n is a predetermined integer which is relatively prime to the number of macroblocks in the frame. , Counting macroblocks and generating an active signal every n macroblocks
Means for selecting a suitable one of intra-frame coding and inter-frame predictive coding for the macroblock, and the first block for coding the macroblock. When the signal generated by the means is not active, the selection result of the second means is selected as it is, and when the signal generated by the first means is active, intraframe coding is selected. A moving picture coding circuit comprising: a third means. 3. The second means for counting macroblocks and generating an active signal every n macroblocks comprises a linear feedback shift register. Video encoding circuit.