JPH0738358A - Automatic gain control circuit - Google Patents

Automatic gain control circuit

Info

Publication number
JPH0738358A
JPH0738358A JP15836193A JP15836193A JPH0738358A JP H0738358 A JPH0738358 A JP H0738358A JP 15836193 A JP15836193 A JP 15836193A JP 15836193 A JP15836193 A JP 15836193A JP H0738358 A JPH0738358 A JP H0738358A
Authority
JP
Japan
Prior art keywords
output
unit
conversion
absolute value
saturation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15836193A
Other languages
Japanese (ja)
Inventor
Seiji Miyoshi
誠司 三好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15836193A priority Critical patent/JPH0738358A/en
Publication of JPH0738358A publication Critical patent/JPH0738358A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To exactly execute automatic gain control even in the case an output of an A/D converting part is saturated. CONSTITUTION:A voltage control attenuating part 2 attenuates a spreaded spectrum signal in accordance with a control voltage and applies it to an A/D converting part 3. An output of the A/D converting part 3 is subjected to reverse diffusion by a PN code in a multiplying part 4, integrated by an integrating part 5, and its absolute value is calculated by an absolute value calculating part 6. Saturation detecting/switching parts 11 and 7 detect saturation of the output of the A/D converting part 3, and in the case it is detected, an output of the absolute value calculating part 6 is outputted, and in the case it is not detected, a constant value is outputted. Outputs of the saturation detecting/ switching parts 11 and 7 are provided to a comparing part 9 through a D/A converting part 8, compared with a reference voltage Vref, and an output of the comparing part 9 is low-pass-filtered by a low-pass filter part 10, and provided to the voltage control attenuating part 2 as a control voltage. The constant value is selected to a value by which an output of the D/A converting part 8 becomes maximum.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、自動利得制御回路に関
し、特にディジタル信号処理形式のスペクトラム拡散受
信機の自動利得制御回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic gain control circuit, and more particularly to an automatic gain control circuit for a digital signal processing type spread spectrum receiver.

【0002】[0002]

【従来の技術】スペクトラム拡散受信機の自動利得制御
は、例えば、特開平1−101040号公報、特開平2
−69033号公報、特開昭60−249445号公
報、特開昭61−33025号公報(PN発生器を用い
ている)、特開昭61−242431号方向などに開示
されている。
2. Description of the Related Art Automatic gain control of a spread spectrum receiver is disclosed in, for example, Japanese Unexamined Patent Publication Nos. 1-101040 and 2-10.
-69033, JP-A-60-249445, JP-A-61-33025 (using a PN generator), JP-A-61-242431 and the like.

【0003】ディジタル信号処理形式のスペクトラム拡
散受信機においては、自動利得制御のための信号処理も
ディジタル信号処理で行えば、経時変動に対して強い等
のディジタル信号処理の利点を生かすことができる。そ
のとき自動利得制御を施す信号帯域を可変したい場合に
は、自動利得制御ループ内に積分回数可変の積分部を有
することになる。この場合の実施例を図2に示す。
In the spread spectrum receiver of the digital signal processing type, if the signal processing for automatic gain control is also performed by the digital signal processing, it is possible to take advantage of the advantages of the digital signal processing such as being strong against the temporal change. At that time, if it is desired to change the signal band for which the automatic gain control is performed, the automatic gain control loop has an integrating unit that can change the number of integrations. An example of this case is shown in FIG.

【0004】図2の自動利得制御回路は、入力端子1か
らスペクトラム拡散信号を受信し、受信信号を制御電圧
に従って減衰する電圧制御減衰部2と、この電圧制御減
衰部2の出力をA/D変換するA/D変換部3と、この
A/D変換部3の出力をPN(pseudonois
e)コード(疑似ランダム符号)で逆拡散するかけ算部
4と、このかけ算部4の出力を積分する積分部5と、こ
の積分部5の出力の絶対値を計算する絶対値計算部6
と、この絶対値計算部6の出力を変換入力信号として受
け、この変換入力信号をD/A変換するD/A変換部8
と、このD/A変換部8の出力を基準電圧Vrcf に比較
し比較結果を出力する比較部9と、この比較部9の出力
を低減濾波し、濾波された信号を前記制御電圧として出
力する低減濾波部10とを、有する。
The automatic gain control circuit of FIG. 2 receives a spread spectrum signal from an input terminal 1 and attenuates the received signal according to a control voltage, and a voltage control attenuator 2 which outputs an A / D signal. The A / D conversion unit 3 for conversion and the output of the A / D conversion unit 3 are PN (pseudonois)
e) A multiplication unit 4 that despreads with a code (pseudo-random code), an integration unit 5 that integrates the output of this multiplication unit 4, and an absolute value calculation unit 6 that calculates the absolute value of the output of this integration unit 5.
And a D / A converter 8 for receiving the output of the absolute value calculator 6 as a conversion input signal and D / A converting the conversion input signal.
And a comparison unit 9 which compares the output of the D / A conversion unit 8 with a reference voltage V rcf and outputs a comparison result, and an output of the comparison unit 9 which undergoes reduction filtering and outputs the filtered signal as the control voltage. And a reduction filtering section 10 for

【0005】[0005]

【発明が解決しようとする課題】通常ディジタル信号処
理においては信号を2の補数で表現する。いま、PNコ
ードの同期が達成されていない場合を考えると、図2に
示す回路において、A/D変換部3出力、かけ算部4出
力はともに雑音状である。A/D変換部3出力が飽和し
ていない場合、A/D変換部3出力の実効値σA/D 、積
分部5出力の実効値σACC 、積分回数Nには以下の関係
がある。
Generally, in digital signal processing, a signal is represented by 2's complement. Considering now that the synchronization of the PN code is not achieved, in the circuit shown in FIG. 2, the output of the A / D conversion unit 3 and the output of the multiplication unit 4 are both noise-like. When the output of the A / D conversion unit 3 is not saturated, the effective value σ A / D of the output of the A / D conversion unit 3, the effective value σ ACC of the output of the integration unit 5, and the number of integration times N have the following relationships.

【0006】σACC =σA/D /N0.5 図2に示す回路では、電源投入時のように自動利得制御
回路の応答速度より速く入力が立ち上がる場合に、所望
のレベルで自動利得制御が行われないという問題があ
る。この理由を以下に述べる。
Σ ACC = σ A / D / N 0.5 In the circuit shown in FIG. 2, automatic gain control is performed at a desired level when the input rises faster than the response speed of the automatic gain control circuit, such as when the power is turned on. There is a problem of not being forgotten. The reason for this will be described below.

【0007】いま、低減濾波器10出力を切り、開ルー
プ特性を考えると、上式より、A/D変換部3入力が飽
和していない場合は、信号入力が増大するにつれて積分
部5出力の実効値、絶対値計算部6出力は増大する。と
ころがさらに信号入力が増大し、A/D変換部3出力が
飽和しはじめると、A/D変換部3出力には正の最大値
と負の最大値が多く現れはじめ、それらは互いに加算す
ると打ち消しあうことから、あるレベル異常の信号入力
に対しては積分部5出力の実効値、絶対値計算部6出力
は単調に増大せずに減少しはじめることになる。すなわ
ちこのような開ループ特性を有する自動利得制御回路
は、動作点が複数生じ得ることになる。
Now, when the output of the reduction filter 10 is turned off and the open loop characteristic is considered, from the above equation, when the input of the A / D converter 3 is not saturated, the output of the integrator 5 increases as the signal input increases. The output of the effective value / absolute value calculation unit 6 increases. However, when the signal input further increases and the output of the A / D conversion unit 3 begins to saturate, many positive maximum values and negative maximum values begin to appear in the output of the A / D conversion unit 3, and they cancel each other when they are added to each other. Therefore, the effective value of the output of the integrator 5 and the output of the absolute value calculator 6 do not monotonically increase but start to decrease with respect to the signal input of a certain level abnormality. That is, the automatic gain control circuit having such an open loop characteristic may have a plurality of operating points.

【0008】本発明の課題は、A/D変換器出力が飽和
した場合でも単調増加な検波特性を実現し、正確な自動
利得制御を行なえるようにした自動利得制御回路を提供
することにある。
An object of the present invention is to provide an automatic gain control circuit which realizes a monotonically increasing detection characteristic even when the output of the A / D converter is saturated and enables accurate automatic gain control. .

【0009】[0009]

【課題を解決するための手段】本発明によれば、スペク
トラム拡散信号を受信し、受信信号を制御電圧に従って
減衰する電圧制御減衰部と、この電圧制御減衰部の出力
をA/D変換するA/D変換部と、このA/D変換部の
出力をPNコードで逆拡散するかけ算部と、このかけ算
部の出力を積分する積分部と、この積分部の出力の絶対
値を計算する絶対値計算部と、この絶対値計算部の出力
を変換入力信号として受け、この変換入力信号をD/A
変換するD/A変換部と、このD/A変換部の出力を基
準電圧に比較し比較結果を出力する比較部と、この比較
部の出力を低減濾波し、濾波された信号を前記制御電圧
として出力する低減濾波部とを、含む自動利得制御回路
において、前記A/D変換部の出力の飽和を検出し、検
出した場合、前記絶対値計算部の出力を前記D/A変換
部に前記変換入力信号として供給し、検出しなかった場
合、定数値を前記D/A変換部に前記変換入力信号とし
て供給する飽和検出切り換え部を有することを特徴とす
る自動利得制御回路が得られる。
According to the present invention, a spread spectrum signal is received, a voltage control attenuator for attenuating the received signal according to a control voltage, and an output A / D for converting the output of the voltage control attenuator. / D conversion unit, a multiplication unit that despreads the output of this A / D conversion unit with a PN code, an integration unit that integrates the output of this multiplication unit, and an absolute value that calculates the absolute value of the output of this integration unit. The calculation unit and the output of this absolute value calculation unit are received as a conversion input signal, and this conversion input signal is received by the D / A.
A D / A converter for conversion, a comparator for comparing the output of the D / A converter with a reference voltage and outputting a comparison result, an output of the comparator for reduction filtering, and a filtered signal for the control voltage. In the automatic gain control circuit including a reduction filtering unit that outputs as, the saturation of the output of the A / D conversion unit is detected, and when detected, the output of the absolute value calculation unit is output to the D / A conversion unit. An automatic gain control circuit is provided which has a saturation detection switching unit that supplies a constant value to the D / A conversion unit as the conversion input signal when it is supplied as the conversion input signal and is not detected.

【0010】更に本発明によれば、前記飽和検出切り換
え部は、前記A/D変換部の出力の飽和を検出する飽和
検出部と、この飽和検出部が前記飽和を検出した場合、
前記絶対値計算部の出力を前記D/A変換部に前記変換
入力信号として供給し、前記飽和を検出しなかった場
合、前記定数値を前記D/A変換部に前記変換入力信号
として供給する切り換え部とを有することを特徴とする
自動利得制御回路が得られる。
Further, according to the present invention, the saturation detection switching unit detects the saturation of the output of the A / D conversion unit, and when the saturation detection unit detects the saturation,
The output of the absolute value calculation unit is supplied to the D / A conversion unit as the conversion input signal, and when the saturation is not detected, the constant value is supplied to the D / A conversion unit as the conversion input signal. An automatic gain control circuit having a switching unit is obtained.

【0011】また、本発明によれば、前記定数値は、前
記D/A変換部の出力が最大になる値に選択されている
ことを特徴とする自動利得制御回路が得られる。
According to the present invention, there is also provided an automatic gain control circuit characterized in that the constant value is selected to be a value that maximizes the output of the D / A converter.

【0012】[0012]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0013】図1に本発明の一実施例のブロック図を示
す。入力信号または中間周波数信号は、端子1から入力
され、電圧制御減衰部2を経てA/D変換部3でA/D
変換される。A/D変換部3出力は、かけ算部4でPN
コードと掛け合わされることにより逆拡散される。かけ
算部4出力は積分部5で積分され、絶対値計算部6で絶
対値が計算された後、切り換え部7の2つの入力の一方
に入力される。切り換え部7出力はD/A変換部8でD
/A変換され、さらに比較部9で基準電圧と比較され
る。比較部出力は低減濾波部10で低減濾波される。低
減濾波部10出力は電圧制御減衰部2に制御電圧として
入力され負帰還をかける。切り換え部7の2つの入力の
うち他の一方には、D/A変換部出力が最大になるよう
な定数が入力されている。また飽和検出部11はA/D
変換部3出力の飽和を判定し、飽和している場合には絶
対値計算部6出力を切り換え部7の出力に、飽和してい
ない場合には前記定数を切り換え部7の出力に切り換え
る。
FIG. 1 shows a block diagram of an embodiment of the present invention. The input signal or the intermediate frequency signal is input from the terminal 1, passes through the voltage control attenuator 2, and is A / D converted by the A / D converter 3.
To be converted. The output of the A / D conversion unit 3 is output to the PN in the multiplication unit 4.
It is despread by being multiplied with the code. The output of the multiplication unit 4 is integrated by the integration unit 5, the absolute value is calculated by the absolute value calculation unit 6, and then input to one of the two inputs of the switching unit 7. The output of the switching unit 7 is D by the D / A conversion unit 8.
A / A conversion is performed, and the comparison unit 9 compares it with the reference voltage. The output of the comparison unit is subjected to reduction filtering by the reduction filtering unit 10. The output of the reduction filter unit 10 is input as a control voltage to the voltage control attenuator unit 2 and negative feedback is applied. A constant that maximizes the output of the D / A conversion unit is input to the other one of the two inputs of the switching unit 7. Further, the saturation detection unit 11 is an A / D
Saturation of the output of the conversion unit 3 is determined, and if it is saturated, the output of the absolute value calculation unit 6 is switched to the output of the switching unit 7, and if not saturated, the constant is switched to the output of the switching unit 7.

【0014】一般的に自動利得制御装置では、開ループ
での利得制御特性が単調であることが必要であるが、比
較的単純な回路で単調な開ループ利得制御特性が得られ
る。また、積分部5の積分時間を変えることにより、自
動利得制御を施す信号帯域を比較的簡単に可変できる。
Generally, in an automatic gain control device, the gain control characteristic in the open loop is required to be monotonous, but a monotonous open loop gain control characteristic can be obtained with a relatively simple circuit. Further, by changing the integration time of the integrating section 5, the signal band for which the automatic gain control is performed can be changed relatively easily.

【0015】このように本実施例では、入力信号はA/
D変換部3でディジタル信号に変換され、かけ算部4で
PN逆拡散され、積分部5で平均化される。さらに、絶
対値計算部6で絶対値化される。一方、飽和検知部10
はA/D変換部1の飽和を検知し、切り換え部7は、A
/D変換部3の出力が飽和していないときは絶対値計算
部6出力を選択し、飽和しているときはD/A変換部8
入力の最大値を選択する。D/A変換部8は切り換え部
7が選択した信号を入力として、アナログ信号を出力す
る。そのアナログ出力は低減通過フィルタ9を経て、電
圧制御減衰器2に負帰還をかける。この結果、A/D変
換器入力が飽和した場合でも単調増加な検波特性を実現
し、利得を自動的に制御することができる。
As described above, in this embodiment, the input signal is A /
The digital signal is converted into a digital signal in the D conversion unit 3, PN despreaded in the multiplication unit 4, and averaged in the integration unit 5. Further, the absolute value calculation unit 6 converts the absolute value. On the other hand, the saturation detector 10
Detects the saturation of the A / D conversion unit 1, and the switching unit 7
When the output of the / D conversion unit 3 is not saturated, the absolute value calculation unit 6 output is selected, and when it is saturated, the D / A conversion unit 8 is selected.
Select the maximum input value. The D / A converter 8 receives the signal selected by the switch 7 and outputs an analog signal. The analog output is passed through the reduction pass filter 9 and negative feedback is applied to the voltage control attenuator 2. As a result, even if the input of the A / D converter is saturated, a monotonically increasing detection characteristic can be realized and the gain can be automatically controlled.

【0016】[0016]

【発明の効果】以上説明したように本発明は、比較的単
純な回路で正確な自動利得制御回路を実現でき、自動利
得制御を信号帯域幅を比較的簡単に可変できるという利
点がある。
As described above, the present invention has the advantages that an accurate automatic gain control circuit can be realized with a relatively simple circuit and the signal bandwidth of automatic gain control can be varied relatively easily.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図。FIG. 1 is a block diagram of an embodiment of the present invention.

【図2】従来技術の一例のブロック図。FIG. 2 is a block diagram of an example of a conventional technique.

【符号の説明】[Explanation of symbols]

1 入力端子 2 電圧制御減衰部 3 A/D変換部 4 かけ算部 5 積分部 6 絶対値計算部 7 切り換え部 8 D/A変換部 9 比較部 10 低減濾波部 11 飽和検出部 1 Input Terminal 2 Voltage Control Attenuation Section 3 A / D Conversion Section 4 Multiplication Section 5 Integration Section 6 Absolute Value Calculation Section 7 Switching Section 8 D / A Conversion Section 9 Comparison Section 10 Reduction Filter Section 11 Saturation Detection Section

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 スペクトラム拡散信号を受信し、受信信
号を制御電圧に従って減衰する電圧制御減衰部と、この
電圧制御減衰部の出力をA/D変換するA/D変換部
と、このA/D変換部の出力をPNコードで逆拡散する
かけ算部と、このかけ算部の出力を積分する積分部と、
この積分部の出力の絶対値を計算する絶対値計算部と、
この絶対値計算部の出力を変換入力信号として受け、こ
の変換入力信号をD/A変換するD/A変換部と、この
D/A変換部の出力を基準電圧に比較し比較結果を出力
する比較部と、この比較部の出力を低減濾波し、濾波さ
れた信号を前記制御電圧として出力する低減濾波部と
を、含む自動利得制御回路において、 前記A/D変換部の出力の飽和を検出し、検出した場
合、前記絶対値計算部の出力を前記D/A変換部に前記
変換入力信号として供給し、検出しなかった場合、定数
値を前記D/A変換部に前記変換入力信号として供給す
る飽和検出切り換え部を有することを特徴とする自動利
得制御回路。
1. A voltage control attenuator for receiving a spread spectrum signal and attenuating the received signal according to a control voltage, an A / D converter for A / D converting the output of the voltage control attenuator, and the A / D converter. A multiplication unit that despreads the output of the conversion unit with a PN code, and an integration unit that integrates the output of this multiplication unit,
An absolute value calculation unit that calculates the absolute value of the output of this integration unit,
The output of this absolute value calculation unit is received as a conversion input signal, and the output of this D / A conversion unit and the D / A conversion unit that performs D / A conversion of this conversion input signal are compared with the reference voltage and the comparison result is output. An automatic gain control circuit including: a comparison unit; and a reduction filtering unit that reduces and filters the output of the comparison unit and outputs the filtered signal as the control voltage. Detects saturation of the output of the A / D conversion unit. If detected, the output of the absolute value calculation unit is supplied to the D / A conversion unit as the conversion input signal, and if not detected, a constant value is supplied to the D / A conversion unit as the conversion input signal. An automatic gain control circuit having a saturation detection switching unit for supplying.
【請求項2】 前記飽和検出切り換え部は、 前記A/D変換部の出力の飽和を検出する飽和検出部
と、 この飽和検出部が前記飽和を検出した場合、前記絶対値
計算部の出力を前記D/A変換部に前記変換入力信号と
して供給し、前記飽和を検出しなかった場合、前記定数
値を前記D/A変換部に前記変換入力信号として供給す
る切り換え部とを有することを特徴とする請求項1に記
載の自動利得制御回路。
2. The saturation detection switching unit detects a saturation of an output of the A / D conversion unit, and outputs an output of the absolute value calculation unit when the saturation detection unit detects the saturation. A switching unit which supplies the D / A conversion unit as the conversion input signal and supplies the constant value to the D / A conversion unit as the conversion input signal when the saturation is not detected. The automatic gain control circuit according to claim 1.
【請求項3】 前記定数値は、前記D/A変換部の出力
が最大になる値に選択されていることを特徴とする請求
項1又は2に記載の自動利得制御回路。
3. The automatic gain control circuit according to claim 1, wherein the constant value is selected to be a value that maximizes the output of the D / A conversion unit.
JP15836193A 1993-06-29 1993-06-29 Automatic gain control circuit Pending JPH0738358A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15836193A JPH0738358A (en) 1993-06-29 1993-06-29 Automatic gain control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15836193A JPH0738358A (en) 1993-06-29 1993-06-29 Automatic gain control circuit

Publications (1)

Publication Number Publication Date
JPH0738358A true JPH0738358A (en) 1995-02-07

Family

ID=15670003

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15836193A Pending JPH0738358A (en) 1993-06-29 1993-06-29 Automatic gain control circuit

Country Status (1)

Country Link
JP (1) JPH0738358A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002247121A (en) * 2001-02-19 2002-08-30 Mitsubishi Electric Corp Automatic gain controller and demodulator
US6782061B2 (en) 1998-04-06 2004-08-24 Nec Corporation AGC circuit
WO2008139672A1 (en) * 2007-04-27 2008-11-20 Panasonic Corporation Receiving device and receiving method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410746A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Spread spectrum communication type agc circuit
JPH04151925A (en) * 1990-10-16 1992-05-25 Ricoh Co Ltd Automatic gain control circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6410746A (en) * 1987-07-02 1989-01-13 Mitsubishi Electric Corp Spread spectrum communication type agc circuit
JPH04151925A (en) * 1990-10-16 1992-05-25 Ricoh Co Ltd Automatic gain control circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6782061B2 (en) 1998-04-06 2004-08-24 Nec Corporation AGC circuit
JP2002247121A (en) * 2001-02-19 2002-08-30 Mitsubishi Electric Corp Automatic gain controller and demodulator
WO2008139672A1 (en) * 2007-04-27 2008-11-20 Panasonic Corporation Receiving device and receiving method
JPWO2008139672A1 (en) * 2007-04-27 2010-07-29 パナソニック株式会社 Receiving apparatus and receiving method
JP4977755B2 (en) * 2007-04-27 2012-07-18 パナソニック株式会社 Receiving apparatus and receiving method
US8693592B2 (en) 2007-04-27 2014-04-08 Panasonic Corporation Receiving device and receiving method

Similar Documents

Publication Publication Date Title
KR970702616A (en) METHOD AND APPARATUS FOR AUTOMATIC GAIN CONTROL IN A DIGITAL RECEIVER
US4185168A (en) Method and means for adaptively filtering near-stationary noise from an information bearing signal
US5917372A (en) Automatic gain control circuit
RU96122867A (en) METHOD AND DEVICE FOR AUTOMATIC ADJUSTMENT OF AMPLIFICATION IN A DIGITAL RADIO RECEIVER
KR100788638B1 (en) Low if receiver reducing the image signal and the image signal rejection method used by the receiver
US7535859B2 (en) Voice activity detection with adaptive noise floor tracking
KR880700539A (en) Noise suppression system
GB2208462A (en) Spread spectrum communications receiver
US5507022A (en) Electric field level detecting apparatus
JPH09229770A (en) Optical power meter
JPH0738358A (en) Automatic gain control circuit
JPS5832403B2 (en) control method
JPS55102972A (en) Removal unit for noise of picture
US7233271B2 (en) Noise shaper circuit and method for reducing switching noise
US7266353B1 (en) Control loop for digital signals
US5347534A (en) Automatic gain control system
JP2781776B2 (en) Spread spectrum communication AGC circuit
KR0147100B1 (en) Method for determining threshold value in communication apparatus with code acquisition circuit
JPH07321706A (en) Agc circuit
WO2004055980A2 (en) System for regulating the level of an amplified signal in an amplification chain.
SU1589402A1 (en) Device for suppression of narrow-band interference
SU1007055A1 (en) Follow-up filter for processing signal with suppressed carrier frequency, phase of which is modulated by binary pseudorandom sequence law
JPS6318408B2 (en)
JPS5480095A (en) Agc system for optical receiver
JPH08307175A (en) Gain controller in spread spectrum communication

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19970408