JPH073834B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION [Overview] In a multi-layer wiring process, when aluminum (Al) is embedded in an electrode window by polishing, a film having a low polishing rate such as plasma is used as a stopper. Providing grown silicon nitride (Si ₃ N ₄ ).

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a multilevel wiring on a semiconductor substrate with flatness.

[Conventional technology]

The wiring of the semiconductor device has a multilayer wiring structure in addition to forming the wiring with a fine pattern in order to increase the integration degree of the device.

An example of the multi-layer wiring will be described with reference to FIG. 2. A first-layer wiring 12 is formed of Al on a base, for example, a semiconductor substrate 11, and an inter-layer insulating film 13 is formed on the first wiring 12 by phosphorous silicate glass (PS).
G) is deposited to a thickness of 1.0 μm. In the actual process, since PSG is deposited high above the wiring 12, the PSG in the high portion is flattened by one etching for flattening, and then PSG is grown again. Then, the insulating film 13
Then, an electrode window 14 is opened, and then an Al film 15 is applied to a thickness of 1.5 μm.

Next, polishing with etching using a slurry, that is, polishing is performed to fill the electrode window 14 with Al. This is because the electrodes or wirings connected to the first layer wirings 12 are formed flat. FIG. 3 shows a case where such polishing is ideally performed, that is, Al is polished but PSG is not polished at all.

[Problems to be solved by the invention]

In the above-mentioned Al polishing, it is actually difficult to realize the polishing shown in FIG. The polishing is performed by polishing a silicon wafer on which the wiring shown in FIG. 2 is formed. However, since the polishing distribution in the wafer is not uniform, for example, a part of the wafer is polished in 15 minutes. In addition, since other parts are not sufficiently polished, for example, polishing for 20 minutes, so-called over polishing (over polishing,
Excessive polishing). Then, as shown in FIG. 4, the PSG is excessively polished and a sufficient breakdown voltage cannot be obtained.

Further, in the actual polishing, as shown in FIG. 5, where the first layer wirings 12 are widely spaced, it is also experienced that the PSG is polished as shown in the drawing even if the overpolishing is not performed.

The present invention was created in view of the above circumstances, and an object of the present invention is to provide a method in which, in a multilayer wiring forming step, the interlayer insulating film formed by PSG is not polished and the breakdown voltage does not decrease. To do.

[Means for solving problems]

FIG. 1 is a sectional view of an embodiment of the present invention, in which 16 is a plasma-grown silicon nitride film.

In the present invention, after the interlayer insulating film 13 is formed by growing PSG, a silicon nitride film is formed on its surface to a thickness of about 1000Å by using plasma.

[Action]

Since the above-mentioned silicon nitride film 16 has a polishing rate (polishing rate) of about 1/6 as compared with PSG, even if overpolishing is performed, the silicon nitride film functions sufficiently as a stopper, To prevent the polishing.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, first, a base, for example, a silicon substrate 11
The first-layer wiring 12 is formed on the upper surface in the same manner as in the conventional example. For that purpose, Al is applied to the entire surface and is patterned by a usual technique. The first layer wirings 12 are wirings for elements formed on the substrate or wirings for connecting elements to each other.

Next, PSG is grown to a film thickness of 1.0 μm and the surface is flattened. This process is also similar to the conventional example.

Next, a silicon nitride film 16 is formed on the surface of the insulating film 13 to have a film thickness of about 1000Å. If the growth is performed by, for example, a chemical vapor deposition method, a temperature higher than the melting point of Al is required and the Al wiring is damaged, so the plasma growth method that can be performed at a temperature of about 450 ° C. is used.

In the next step, the electrode window 14 was formed, the Al film 15 was formed to a thickness of 1.5 μm, and the Al film 15 was polished.

Here, when comparing the polishing rates of PSG and the silicon nitride film when using the same slurry as when polishing conventional Al, PSG is about 90 Å / min. Silicon nitride is about 15 Å / min. The polishing rate of the silicon nitride film is about 1/6.

In one experimental example, to properly polish Al
In the example where it took 30 minutes, when 50% overpolish (15 minutes polish) was applied to eliminate the polishing distribution in the wafer, the polished amount of the silicon nitride film was 200 to 300.
It was Å, and no film burring (polishing) of the PSG film was observed.

By providing the silicon nitride film in this manner, polishing can be carried out without much care in polishing distribution, and workability is improved.
Polishing of PSG was prevented and the pressure resistance between layers was not impaired.

〔The invention's effect〕

As described above, according to the present invention, in the multi-layer wiring process, during polishing of Al for filling the electrode window with Al, polishing of the PSG interlayer insulating film is prevented even if overpolishing is performed, and workability is improved. The improving effect was obtained.

Although the insulating film of the first layer wiring on the silicon substrate has been described above, the base may be an insulating film, and the scope of application of the present invention is not limited to the illustrated example and the above description. Also, instead of silicon nitride, titanium nitride (TiN)
May be used.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2 to 5 are sectional views of a conventional example. In FIGS. 1 to 5, 11 is a silicon substrate, 12 is a first layer wiring, 13 is an insulating film, 14 is an electrode window, 15 is an Al film, and 16 is a silicon nitride film.

Claims (1)

[Claims] 1. An interlayer insulating film (13) for wiring (12) formed on a base (11) is formed of phosphorus silicate glass, and is further polished on the interlayer insulating film (13). A method of manufacturing a semiconductor device, comprising forming a film having a low rate by a plasma growth method and then polishing the film.