JPH0737931A - Tape carrier type semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to reduce cost and simplify wiring work by connecting different kinds of tape carriers to electrodes having the same function, which respectively constitute common wiring portions, thereby permitting common wiring portions of LSI where a plurality of electrodes having the same function can exist at the central part only by the one surface of the tape carriers. CONSTITUTION:Different kinds of tape carriers 7 constituting common wiring portions 3 are respectively connected to a plurality of electrodes having the same function which exist on LSI4. For example, partial common wiring tape carriers 7 are used at the common wiring portions 3 when electrodes 22 are arranged on a straight line in the central part of the surface of LSI4 and a 16-Mbit DRAM having ground electrodes and power supply electrodes at plural side is modified to a tape carrier type semiconductor device. This common wiring tape carrier 7 is made as thin as possible so as to prohibit the occurrence of configurational interference with the tape carriers 5 not connected to a plurality of electrodes requiring common wiring on the LSI chip 4.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a tape carrier type LS.
With regard to the I package, it is possible to provide a common wiring section for electrodes for external extraction and electrodes on the LSI having the same function, without being affected by the electrode arrangement on the LSI, and thus a wide variety of LSIs can be provided. The present invention relates to a tape carrier type semiconductor device suitable for being a thin and highly functional tape carrier type semiconductor device.

[0002]

2. Description of the Related Art Conventionally, when an LSI is formed into a tape carrier type semiconductor device, a plurality of various electrodes on the LSI are connected to the L
If it is arranged so as to surround the periphery of SI, LSI
Each electrode on the tape carrier for connection with
By arranging around the perforation part for mounting, it was possible to easily connect the both. However, with the increase in the degree of integration of the circuits on the LSI, the electrodes on the LSI are arranged from the peripheral portion of the LS because of the design constraint of the circuit pattern that the surface on which the elements cannot be formed is eliminated as much as possible.
It has moved to the center of I. Especially memory LS
In the case of I, a power electrode and a ground electrode are required for each unit in which the memory cells on the LSI are collected, and in order to save the number of external extraction electrodes, these plural functional electrodes are connected by a common wiring. It has become necessary to provide a common wiring section.

In the prior art, an LSI having such an electrode arrangement is used.
On the other hand, a common wiring and a tape carrier have not been performed between predetermined electrodes, and the wire bonding method is used to form a three-dimensional structure for the Fe-Ni-based lead frame in which the common wiring portion is formed. By connecting various wires, connect while ensuring electrical insulation in the necessary parts,
The structure in which a resin mold is applied was the mainstream.

[0004]

However, in order to form a common wiring portion and a tape carrier for an LSI having an electrode at the central portion, only two-dimensional wiring is performed from the shape of the tape. Due to the nature of the tape carrier, it is necessary to provide wiring layers on both front and back surfaces of the tape carrier in order to electrically insulate between the common wiring part and the other electrodes. Therefore, there is a problem that the manufacturing cost is more than doubled, and it is necessary to provide through holes like a printed circuit board to obtain electrical connection between the wirings on the front and back surfaces of the tape carrier. There was a technical problem with the creation of wiring on both the front and back sides of the carrier.

The present invention has been made in view of the above problems of the prior art.
The common wiring part of the LSI having a plurality of electrodes having the same function in the central part can be formed on only one side of the tape carrier to reduce the cost and simplify the wiring work.
Achieves tape carrier for various LSIs without being restricted by the above electrode layout, reduces electrical noise in the package, and is a thin and highly functional device that can incorporate multiple LSIs in one package. An object is to provide a tape carrier type semiconductor device.

[0006]

There are roughly classified signal electrodes, ground electrodes, and power supply electrodes on an LSI. These wirings have come to be arranged in the center of the LSI chip in a close state with the high integration of the LSI. When multiple ground electrodes and power supply electrodes are present on the LSI, common wiring is used between them for the purpose of saving the number of wirings for drawing out to the outside and simplifying the wiring design on the mounting board. It will be necessary to do. A partial tape carrier is used for the purpose of this common wiring. This common wiring tape carrier is first connected to a predetermined electrode having the same function on the LSI, and then the remaining electrodes are connected to a tape carrier to be an external wiring, which is completed. A method is used in which the tape carrier is completed by connecting and adhering and then connecting to the LSI.

As an alternative to using a partial tape carrier for a common-function electrode for common wiring, a tape carrier which becomes a lead electrode from the entire LSI after connecting a pattern formed by molding only a copper foil into a predetermined shape Connect. Regarding this copper foil wire, a method of connecting it to the tape carrier first and then connecting it to the LSI is also conceivable. It is also possible to employ a method in which wire bonding is partially performed only on the electrodes having the same function that perform common wiring.

Further, a method of connecting a common wiring portion on a tape carrier by using an anisotropic conductive sheet and electrically insulating and connecting an electrode requiring common wiring and another electrode on the tape carrier. take.

By arranging the common wiring portion on the tape carrier, it is also possible to adopt a structure in which the lead wiring to the outside and the common wiring portion are unevenly distributed on the left and right of the tape carrier, respectively.

As an application technology of the thin tape carrier configured as described above, after connecting to one lead frame at a position where a plurality of LSI parts mounted on the tape carrier are laminated, molding is performed with an epoxy resin, A high-performance package that includes a plurality of LSIs in one package is configured.

By designing the common wiring portion, power supply noise and signal noise can be reduced, and the effect of the present invention can be further promoted.

[0012]

When a common wiring portion for a plurality of identical-function electrodes existing on the LSI is provided, it becomes possible to use a tape carrier having an electrode made of copper foil or the like on only one side of the tape carrier. It is possible to suppress an increase in cost due to the use of a double-sided wiring tape carrier in which wiring portions are provided on both surfaces of the tape carrier and through holes are provided. Further, by forming the LSI into a thin tape carrier in this manner, it is possible to reduce the thickness as a whole as compared with the conventional package using the wire bonding method and the resin mold, so that highly integrated mounting can be realized. The LSI is a tape carrier type semiconductor, these are connected at a position where they are stacked on one lead frame, and the entire outer peripheral portion is resin-molded, so that multiple LSIs are mounted in one package. It is possible to create a functionalized package. Also on the tape carrier 3
Since the three-dimensional wiring can be easily formed, the structure can reduce the electrical noise depending on the structure.

[0013]

EXAMPLES [First Example] Examples of the tape carrier having the structure described in claims 1 to 9 will be described below. 16MbitDR with next generation storage capacity
A case where AM (abbreviation of Dynamic Randam Access Memory) is made into a tape carrier type semiconductor device will be described.
In the 16 Mbit DRAM, as a result of increasing the degree of integration of each memory cell, the limitation of the element formation area due to the Al wiring deposited on the LSI chip is reduced as much as possible.
The electrodes are arranged in a straight line at the center of the LSI surface. Further, since this LSI has a form in which a plurality of unitized portions for each predetermined memory capacity are gathered together, electrodes corresponding to the power supply and the ground are formed for each unit. In particular, a plurality of ground electrodes are arranged for each unit because it is necessary to improve noise resistance with an increase in chip area itself and a reduction in operating voltage aiming at low power consumption. When a tape carrier package is formed by using an LSI having a plurality of power supply electrodes and ground electrodes in this way, common wiring is provided between electrodes having the same function to reduce the number of lead-out electrodes to the outside. It is necessary to reduce it. Further, by arranging the power electrode common wiring and the ground electrode common wiring at positions electrically independent from other wiring, consideration is given to reduce noise caused by electromagnetic induction inside the wiring. There is. The above tendency is due to 64M DRAM and further 2
The same applies to the 56M DRAM, and the same applies to the ASIC LSI.

FIG. 19 shows a conventional LOC (Lead).
An example of wiring of a plastic package having an On Chip structure is shown. 40 is an LSI chip, 41 is an external lead terminal, 42 is a wire for wire bonding, and 43 is L
The common wiring portion for the ground electrode and the power electrode arranged so as to lie on the SI chip 40 is also a part of the lead frame. 44 is a mold resin.

In this embodiment, as shown in FIG. 1, a tape carrier 7 for partial common wiring is used in the common wiring portion 3 to connect to the LSI chip 4. The tape carrier 7 for the common wiring is made as thin as possible so that the plurality of electrodes on the LSI chip 4 which require the common wiring and the tape carrier 5 not connected are geometrically interfered with each other. Keep it from happening. For example, the thickness of the tape carrier 7 for common wiring is 75 μm.
m, and the thickness of the tape carrier 5 connected to the remaining electrodes that are not shared wiring is 125 μm,
When both of them are connected to the electrodes on the LSI chip 4, the tape carrier 7 for the common wiring is more flexible, so that it is possible to easily avoid the geometrical interference.

As shown in FIG. 2 (a) and FIG. 2 (b), which is an enlarged view of a main part of FIG.
It is possible to completely avoid the portion of the tape carrier 5 that overlaps with the carrier tape 7 for common wiring (the portion shown by hatching in FIG. 2B) by molding (punching). By using a polyimide resin as the material of the tape carriers 5 and 7, heat resistance during thermocompression bonding of the electrodes 22 on the LSI chip 4 and the tape carriers 5 and 7 can be ensured.

The LSI chip 4 and the tape carriers 5, 7 are connected to each other by the Au-shaped protruding electrode 22 provided on the LSI chip 4 and the Au-plated tape carrier 5, 5.
It is pressure-bonded to a predetermined electrode on 7 at a temperature of 500 ° C. to 600 ° C. for several seconds with a pressure such that the electrode on the tape carrier 5, 7 in this portion is slightly deformed. In the crimping with the heating tool, the heating tool can be processed into a shape such that only the electrode 22 on the predetermined LSI chip 4 can be selectively crimped. The wiring on the tape carriers 5 and 7 is made of Cu foil with a thickness of about 35 μm, and by using, for example, a photo-etching method, a complicated wiring pattern can be molded with high accuracy. The wiring on the tape carrier 7 for common wiring is LS as long as it has a positional relationship such that it can be electrically insulated from the wiring on the tape carrier 5 connected to other electrodes by interposing the tape carrier 5.
It does not matter whether it is on the side in contact with the pattern forming surface of the I-chip 4 or on the opposite side. The wiring on the other tape carrier 7 to be combined is also not particularly limited as long as electrical insulation can be achieved between the two correspondingly. Even if the two are in direct contact with each other, it suffices that an electrical insulation measure such as a solder resist is applied to the wiring on either one of the tape carriers 7.

In the above structure, as shown in FIG. 3B (a view showing the LSI chip 4 disassembled from FIG. 3A showing the tape carrier 5 side), only the tape carrier 7 for the common wiring is previously prepared. A method may be used in which the electrodes 22 on the LSI chip 4 are connected or aligned and bonded, and then the other electrodes are connected together with the tape carrier 5.
FIG. 4A is an enlarged view of an essential part of FIG. 4A and FIG.
As shown in FIG. 5B, first, the two tape carriers of the tape carriers 5 and 7 are joined by adhesion or welding of the overlapping portion 23 (shown by cross hatched lines in the figure) of the two, and further, FIG. , (B), (c), the common wiring portion 3 provided for the purpose of connecting the electrodes on each tape carrier 5, 7 and the connection portion 8 (in the figure) for the wiring on the tape carrier 5 are provided. (Indicated by diagonal lines), the electrodes on the tape carriers 5 and 7 are connected to each other to form a composite tape carrier, and then the electrodes 22 on the LSI chip 4 are collectively connected. The chip 4 and each tape carrier 5, 7 can be connected. In particular, when highly accurate alignment with the tape carriers 5 and 7 with respect to the electrodes on the LSI chip 4 is required, the method of connecting the tape carriers 5 and 7 to the LSI chip 4 is advantageous.

Further, as shown in claims 7 and 8,
Among these plural types of tape carriers, as a method of concentrating the electrodes to be drawn to the outside on one tape carrier, on the tape carrier 5 shown in FIG.
If the electrodes on the SI chip 4 are not particularly sensitive to the use of plating applied to each electrode or thermocompression bonding such as high temperature soldering as shown in FIG. There are methods such as a method of connecting by using an anisotropic conductive sheet, a method of using an electrode especially provided on an LSI for the purpose of electrically connecting the tape carrier 7 for common wiring and the tape carrier 5 for drawing out an external electrode. Conceivable. In addition, FIG. 6 is a VI-VI arrow view of FIG.
In the figure, 9 is a thermocompression bonding stage, 10 is a connection tool for connecting the common wiring part 3 and the wiring on the tape carrier 5 at the connection part 8, and 11 is a connection for connecting the LSI chip 4 and the tape carriers 5, 7. Is a tool for.

Further, as shown in FIGS. 7 (a) and 7 (b), the electrodes may be independently drawn out from each tape carrier. In any case, the wiring width of the common wiring section 3 is
Noise inside the package can be reduced by making it as wide as possible. These tape carriers 5, 7 and L
After the connection with the SI chip 4 is completed, the LSI chip 4
The tape carrier portion that overlaps with the connection portion of the electrodes 22 on the LSI chip 4 and the tape carriers 5 and 7,
Potting is made with epoxy resin to improve mechanical resistance and moisture resistance.

In the first to fourth aspects, the tape carrier 7 for the partial common wiring is used for the electrodes requiring the common wiring, but the tape carrier for the common wiring is used. It is also possible to adopt a configuration in which the wiring using only Cu foil, which does not have 7 or only slightly leaves the tape portion for the purpose of holding the wiring portion, is used.

As shown in FIGS. 8 (a) and 8 (b), this is a method of initially connecting the wiring pattern 12 made of Cu foil in the form of a tape carrier to the electrode at the position where the common wiring is required. Or a Cu foil is formed into a strip shape of an appropriate shape, and the Cu foil for the common wiring is LS
A tape carrier for the purpose of aligning and thermocompression-bonding the electrodes on the I-chip 4 on which common wiring is necessary, cutting unnecessary tape portions, and drawing out electrodes to the finished LSI with common wiring. It does not matter whether the method of 5 is also thermocompression bonded as shown in FIG. Figure 8
Reference numeral 13 indicates a connection portion between the wiring pattern 12 for common wiring and the wiring on the tape carrier.

The electrode 25 required for the common wiring on the LSI chip 4 is secured in an area sufficient for thermocompression bonding of the two electrodes of the common wiring and the tape carrier for external drawing, or 2 Either method of using the electrode 25 on the LSI chip 4 for connecting the common wiring, which is drawn to a position where the two electrodes do not interfere with each other, can be adopted.

A part of the tape carrier 5 is punched or cut so that the wiring to which the common wiring is applied is exposed as seen from the surface opposite to the surface on which the pattern is formed on the tape carrier 5. The common wiring portion is connected from the side opposite to the surface on which the wiring is formed, by thermocompression bonding such as single point bonding using the plating applied to the surface, or by using high temperature solder. At this position, by interposing the tape, it is possible to electrically insulate the wiring other than the wiring requiring the common wiring.

In this case, the tape carrier 5 for pulling out the external electrode and the common wiring part 3 are connected by thermocompression bonding or the interposition of an anisotropic conductive sheet or the like so that the electrode can be pulled out from one tape carrier or Cu. An electrode part holding tape carrier 14 for the purpose of mechanical reinforcement and holding of each electrode is left on the outer periphery of the foil wiring part in the form shown in FIG. 10B, and the common wiring part 3 is formed as shown in FIG. Independently of the external lead-out terminal 6 on the tape carrier 5 shown in (a),
It does not matter whether the electrode is directly pulled out to the outside. After the connection of the common wiring section 3 using the tape carriers and the copper foil shown in FIG. 10C is completed, the LSI connection section is potted with an epoxy resin.

[Second Embodiment] Claims 9 to 12
An example relating to this will be shown below. In the first embodiment,
Although a tape carrier or a copper foil is mainly used as the common wiring for the electrodes 22 on the LSI chip 4, in the second embodiment, wire bonding is used instead of the tape carrier 7 for the common wiring. Au by law
A wire 21 made of a thin wire is used.

As shown in FIG. 11A and FIG. 11B, which is an enlarged view of a main part of FIG. 11A, an electrode 15 corresponding to a common wiring is provided on the tape carrier 5. Since the electrode 15 on which the common wiring is wire-bonded is connected a plurality of times, the width of the electrode 15 corresponding to the bonding position is ensured so that the bonding positions do not overlap at each stage. L that requires common wiring
The electrode 22 on the SI chip 4 and the other electrodes and the tape carrier are connected to the Au protruding electrodes on the LSI chip 4 and the tape carrier.
Connection is made by thermocompression bonding of electrodes on a plated tape carrier. After that, the electrode 1 on the tape carrier 5 to which the wire 21 for the common wiring is wire-bonded
5, the arch height of the wire 21 is reduced as much as possible to perform wire bonding to complete the common wiring.

LSI by wire bonding
Damage to the circuit pattern on the chip 4 or LS
If a problem such as cracking of the I-chip 4 is caused, this common wiring may be performed before the tape carrier 5 is connected to the LSI chip 4 and only with the tape carrier 5 as shown in FIG. In this case, the common wiring wire 21 is formed on the surface of the tape carrier 5 opposite to the surface on which the wiring pattern is formed in order to ensure electrical insulation from other wiring. At this time, the electrode 15 for wire bonding has a form in which the wiring made of copper foil is exposed when viewed from the surface opposite to the wiring surface of the tape carrier 5 with the tape carrier 5 removed and the tape carrier removed. Keep it.

The wire bonding is carried out at a temperature at which the tape carrier 5 is not so much thermally deformed.
It is performed in a preheated state of 0 ° C to 200 ° C. The portion on which the wire bonding is performed and the tape carrier are held flat on the stage in a state where the rigidity for ultrasonic pressure connection by the capillary can be ensured during the wire bonding. The productivity of the connection between the LSI chip 4 and the tape carrier 5 and the common wiring can be improved by performing all the operations when the tape carrier 5 is in the reel state. At this time, if it is necessary to mechanically reinforce and protect the portion to which the wire bonding is applied, it is preferable to attach a protective tape or the like to the wire bonding portion.

The portion where the common wiring is provided by the wire 21 does not have to be 5 on the tape carrier. For example,
When the electrodes on the LSI chip 4 are arranged at relatively wide intervals as shown in FIGS. 13A and 13B, wire bonding is performed on the LSI upper electrode 16 for which common wiring needs to be performed later. , The tape carrier 5 has a shape capable of avoiding interference with the wire bonding portion, and after the connection of the LSI chip 4 and the tape carrier 5 is completed, different types of common wiring portions, Also, wire bonding can be performed at a position avoiding contact with the electrodes on the tape carrier 5. At this time, the electrodes 16 on the LSI chip 4 for the purpose of performing common wiring to which wire bonding is applied
Is laid out by Al wiring on the LSI chip 4 to a position where interference does not occur when connecting to another tape carrier and wire bonding, and after connecting the LSI chip 4 and the tape carrier 5 to this portion, wire bonding However, it is necessary to manufacture a dedicated LSI chip for this purpose. When an electrode for wire bonding is provided on the LSI, it may be considered that the LSI with the common wiring portion is wire-bonded before the connection with the tape carrier. At this time, the tape carrier is designed to avoid geometrical interference, or a solder resist, a protective tape, or the like is used to electrically insulate the necessary parts.

In the above tape carrier for performing common wiring by wire bonding, it is possible to use a tape having a surface of the wire 21 used for wire bonding coated with an insulating paint. According to this, after the connection of the tape carrier is completed, an epoxy resin is applied to the upper surface portion of the LSI chip 4 for the purpose of improving mechanical reliability and reliability such as moisture resistance, or when the tape is used. When the entire carrier type semiconductor is molded with epoxy resin to form a single plastic package, it is possible to ensure electrical insulation between each wire and between electrodes. The degree of freedom in designing common wiring positions increases. For example, since wire bonding can be performed on the wiring surface, it is not necessary to perform processing such as making a hole on the tape carrier, which improves productivity.

[Third Embodiment] An embodiment in which an anisotropic conductive sheet is used when the common wiring portion described in claim 13 is provided on a tape carrier will be described below.

When the common wiring is carried out in the state of the tape carrier alone, as shown in FIG. 14 (a), the common common wiring is formed by the copper foil into a shape corresponding to the electrode portion requiring the common wiring on the tape carrier. The wiring part 17 is configured. The anisotropic conductive sheet 18 shown in FIG. 14 (b) is selectively sandwiched between the electrodes on both the tape carriers 5 shown in FIG. 14 (c) that require connection. After this, both are thermocompression bonded by a heating tool. Alternatively, when it is necessary to electrically insulate the electrode, a solder resist may be applied on the electrode, and the anisotropic conductive sheet 18 may be formed in a strip shape and interposed so as to come into contact with the entire electrode. .
In the tape carrier having the shape as shown in FIG. 14D configured in this way, when connecting the electrodes on the LSI chip 4, the surface on which the common wiring portion 17 does not exist is L
By connecting toward the front surface side of the SI chip 4, the anisotropic conductive sheet 18 and the common wiring portion 17 made of copper foil can be connected regardless of the increase in thickness.

A method of connecting the common wiring portion after connecting the tape carrier 5 and the LSI chip 4 can also be adopted. In this case, the surface of the tape carrier 5 on which the wiring is formed is made the surface opposite to the surface of the LSI chip 4, and the connection is made at the respective electrodes. After that, prepare a wiring part with a shape that matches the part that requires common wiring, and
The anisotropic conductive sheet 18 is aligned and bonded in a predetermined shape on the tape carrier 5 connected to the I-chip 4, and then the prepared common wiring portion 17 is connected. The temperature applied by the connection of the anisotropic conductive sheet 18 is 250 ° C. or lower, and the heating time is short, so that the LSI chip 4
There is no deterioration of the strength of the LSI and the tape carrier connecting portion, which is connected by the Au electrode above and the Au plating applied on the tape carrier 5.

If there is no problem with the adhesive strength in the connection using the anisotropic conductive sheet 18, a method of selectively pressurizing and connecting to a portion where the connection is required can be adopted. In this case, electrical insulation is maintained in the non-pressurized portion due to the property of the anisotropic conductive sheet 18, so that the anisotropic conductive sheet 18 is applied to the wiring portion where common wiring is not required. A shape can be used. It is possible to connect a plurality of points at once by devising the tip shape of the pressure tool, or to connect one point at a time using a pressure tool with a small tip.

[Fourth Embodiment] Claims 15 and 1
An example for No. 6 is shown below. In this embodiment, a tape carrier 5'provided with a wiring layer made of copper foil on either the back surface or the front surface is used. At this time, the portion connected to the required electrode of the common wiring on the LSI chip 4 is unevenly distributed on one of the left and right sides to form a pattern as shown in FIG. The part that serves as the external lead electrode of the tape carrier type semiconductor device is formed so as to be unevenly distributed on the side opposite to the part where the pattern of the common wiring part 3 is formed on either the left or right side of the tape carrier. However, the common wiring section 3 can perform wiring only to one kind of the same function electrode on the LSI chip 4 due to its structure.

When there are two types of electrodes on the LSI chip 4 that require common wiring, one for each of the left and right sides and two different types of tape carriers 5a, 5b are used for the common wiring. At this time, the tape carrier has a structure and arrangement as shown in FIG. Tape carrier 5a,
In this case, the connection between 5b and the electrodes on the LSI chip 4 is performed twice for each of the left and right tape carriers, or
Alternatively, either of them may be aligned and then bonded onto the LSI chip 4 and thermocompression bonded at once.

When connecting twice, in order to prevent deterioration of the connected portion due to reheating in the previously connected portion,
The heating tool is processed in such a shape that the bonding position at each stage can be selectively subjected to thermocompression bonding. Further, the tape carriers 5a and 5b are also shaped so as not to cause geometrical interference during thermocompression bonding of the respective electrodes and the LSI chip 4.

When the present embodiment is applied to the LSI chip 4 which requires two or more kinds of common wiring, the tape carriers corresponding to the respective common wirings are prepared by dividing the tape carrier in the left and right and further in the vertical direction. . However, at this time, the common wiring portion 3 and the portion serving as the external lead wiring of the tape carrier semiconductor device are unevenly distributed on one of the left and right sides, and the wiring from each tape carrier to the outside is independently drawn. .

[Fifth Embodiment] An embodiment for claim 17 will be described below. When the tape carrier type semiconductor device having the shape shown in claims 1 to 9 is used,
External lead-out terminal 6 on each tape carrier
When each tape carrier is folded back into a crank shape as shown in FIG. 17 and the tape carriers are arranged in a stacked state, the LSI mounting portions are not in contact with each other. On the lead frame 19 for connecting these tape carriers, a portion 2 to which the tape carrier is connected
6 is Sn-plated in advance, and the Au-plated electrode on the tape carrier is in the range of 350 ° C to 400 ° C.
Perform thermocompression bonding using a heating tool.

The material of the lead frame 19 is ordinary Fe.
A 42 alloy made of —Ni is used, but a material made of Cu can also be used. At this time, the load applied to the tape carrier is set so that the electrode made of Cu on the tape carrier is slightly deformed. Each tape carrier is potted with an epoxy resin 20 at the connection portion with the LSI chip 4 to improve mechanical reliability, reliability such as moisture resistance, and electrical insulation. However, in the structure shown in claim 16, since the entire outer peripheral portion is molded with the epoxy resin 20, the L of each layer is
There is no need to perform resin potting on the LSI chip 4 unless electrical insulation such as contact prevention is particularly required for the back surface of the SI chip 4 and the electrodes and wiring on the tape carrier.

When the tape carriers constructed by using the common wiring by wire bonding according to the tenth to fourteenth aspects are stacked and arranged, the arch of the wire 21 by wire bonding is formed in each layer. It is essential to prevent contact between this and the back surface of the LSI chip 4. Wire 21 and LSI chip 4
For the purpose of preventing electrical contact with the back surface on which the pattern is not formed, it is possible to attach a polyimide tape 27 or the like to the back surface of the LSI chip 4 as shown in FIG. 18 to achieve electrical insulation. Further, when the external lead-out terminal 6 on the tape carrier is bent in a crank shape, the folded back height thereof is set to be higher than the arch height of the wire 21.
Avoid contact between wire 21 and. A plastic package of 400 mil size can be formed in a stacked state of about two layers. However, depending on the thinness of the LSI chip 4 itself and the height of the arch portion of the wire 21, more LSI chips can be formed. It is also possible to store 4 in a package by stacking them.

It is arbitrary whether the wire bonding portions are connected to the lead frame 19 at positions facing each other or to the outside of the package.
A method of connecting all the LSI chips 4 in the same direction is also possible. At this time, whether the tape carrier type semiconductor is connected to the lead frame 19 by allocating it to the upper and lower surfaces or connecting to the same side on the lead frame 19 is a design problem and is free.

[0044]

If the present invention is used when the electrodes are concentrated in the central portion of the LSI chip and the common wiring is performed between a plurality of electrodes, a copper foil is provided on only one surface of the tape carrier. By using a tape carrier having wiring formed by cutting in a predetermined shape, a tape carrier type semiconductor can be obtained without being influenced by the electrode arrangement on the LSI. Therefore, compared with the case of using a tape carrier in which wiring is provided on both sides of the tape carrier, it is possible to significantly reduce the cost particularly in manufacturing the tape carrier. Further, by devising the routing of the common wiring, a circuit capable of reducing signal noise or power supply noise can be formed on the tape carrier. Furthermore, taking advantage of the extremely thin outer shape of the LSI package in which the tape carrier is used for external drawing and common wiring, a plurality of layers are stacked and connected to one lead frame, and a plurality of packages are formed in one package. It is possible to easily configure a package including an LSI chip.

[Brief description of drawings]

FIG. 1 is a schematic configuration explanatory diagram of the present invention.

FIG. 2 is an explanatory diagram of a state in which the shape of the tape carrier avoids geometrical interference with a common wiring portion.

FIG. 3 is an explanatory diagram of a method of connecting a common wiring section to an LSI in advance.

FIG. 4 is an explanatory diagram of a method of adhering a tape carrier to form a composite with a common wiring portion.

FIG. 5 is an explanatory diagram of a method of electrically connecting tapes together to form a composite.

FIG. 6 is a conceptual diagram in the case where the tape carriers are connected to each other and the LSI and the tape carrier are simultaneously connected.

FIG. 7 is an explanatory diagram of a method of independently pulling out an electrode from a tape carrier connected to a common wiring portion and other electrodes.

FIG. 8 is an explanatory diagram of a method of using a tape carrier to which a common wiring using only Cu foil is connected first.

FIG. 9 is an explanatory diagram of a method of thermocompression-bonding a Cu foil of a common wiring part on an LSI in advance.

FIG. 10 is an explanatory diagram of a method of independently extracting electrodes for external connection from a Cu foil for common wiring.

FIG. 11 is an explanatory diagram of a method of forming a common wiring section on a tape carrier by using wire bonding.

FIG. 12 is an explanatory diagram of a method of forming a common wiring by performing wire bonding in advance on the tape.

FIG. 13 is an explanatory diagram of a method of forming a common wiring portion by wire bonding by devising electrodes on the LSI.

FIG. 14 is an explanatory diagram of a method of forming a common wiring portion on a tape carrier with an anisotropic conductive sheet.

FIG. 15 is a diagram showing a structure in which a common wiring portion is unevenly distributed on one side of a tape carrier.

FIG. 16 is a structural explanatory diagram when two or more types of common wiring are required.

FIG. 17 is a diagram showing a positional relationship in the case where a plurality of LSIs are built in one package and the tape carrier leads are molded and connected to a lead frame.

FIG. 18 is a structural explanatory view when using a tape carrier combined with wire bonding.

FIG. 19 is a perspective view showing a structure of a plastic package using a lead frame and wire bonding, which is a conventional technique.

[Explanation of symbols]

1,44 ... Molded resin, 3,43 ... Common wiring section,
4, 40 ... LSI chip, 5, 5 '... tape carrier,
5a ... Tape carrier having common wiring section and external lead electrode arranged on one side (right), 5b ... Tape carrier having common wiring section and external lead electrode arranged on one side (left), 6, 4
DESCRIPTION OF SYMBOLS 1 ... External lead-out terminal, 7 ... Tape carrier for common wiring, 8 ... Connection part of common wiring and tape carrier upper wiring,
9 ... Thermocompression bonding stage, 10 ... Tool for connecting common wiring and wiring on tape carrier, 11 ... Tool for connecting LSI and tape carrier, 12 ... Common wiring of copper foil only, 13
... Connecting part of common wiring only with copper foil and wiring on tape carrier, 14 ... Tape carrier for holding electrode part, 15 ... electrode for common wiring by wire bonding, 16 ... L
Electrodes improved for common wiring by wire bonding on SI, 17 ... Common wiring portion connected by anisotropic conductive sheet, 18 ... Anisotropic conductive sheet, 19 ... Lead frame, 20 ... Resin for potting 21, 42
... Wires for common wiring by wire bonding, 22 ... Electrodes on LSI, 23 ... Connection parts between tape carriers, 25 ... Electrodes required for common wiring on LSI, 27 ... Polyimide tape.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akio Hasebe, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd.Hitachi, Ltd., Institute of Industrial Science (72) Inventor, Hisashi Ishida 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Production Engineering Research Laboratory, Hitachi, Ltd. (72) Kazuma Miura, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Production Engineering Research Laboratory, Hitachi, Ltd.

Claims (17)

[Claims] 1. A tape carrier type semiconductor device characterized in that a plurality of electrodes having the same function existing on an LSI are connected to different types of tape carriers constituting a common wiring section. 2. The tape carrier type semiconductor device according to claim 1, wherein the tape carrier connected to the same functional electrode and the tape carrier connected to the other electrode are connected by an adhesive or an electric circuit. A tape carrier type semiconductor device characterized in that it is connected to electrodes on an LSI after a carrier is formed. 3. The tape carrier type semiconductor device according to claim 1, wherein the tape carrier connected to the same function electrode is connected to an electrode on the LSI first, and then connected to another electrode to the other electrode. Connect the tape carrier,
A tape carrier type semiconductor device characterized in that an electric circuit is further connected between the respective tape carriers, and external electrodes are collectively pulled out from the one kind of connected tape carriers. 4. The tape carrier type semiconductor device according to claim 1, wherein after the tape carrier is connected to the electrodes on the LSI, external electrodes are independently pulled out from each tape carrier. . 5. A tape carrier characterized in that a common wiring portion is constituted by a copper foil formed by cutting a plurality of electrodes having the same function existing on an LSI on a tape carrier into a predetermined shape, which is adhered onto the tape carrier. Type semiconductor device. 6. The tape carrier type semiconductor device according to claim 5, wherein a copper foil for common wiring is first connected to an electrode provided on an LSI, and thereafter, a portion where common wiring is not required. A tape carrier type semiconductor device characterized in that it is configured by connecting a tape carrier to. 7. The tape carrier type semiconductor device according to claim 5, wherein the common wiring portion is formed of copper foil and the LS is formed.
I A tape carrier type semiconductor device characterized by using a tape carrier process for alignment and connection with an upper electrode. 8. The tape carrier type semiconductor device according to claim 1, wherein an electrode having a partially modified or enlarged shape for connecting a tape carrier for common wiring is formed on an LSI chip. A tape carrier type semiconductor device characterized in that a tape carrier for common wiring and a tape carrier other than the common wiring are electrically connected to each other by using the electrodes. 9. The tape carrier type semiconductor device according to claim 1, wherein the electrodes having the same function on the LSI chip are separated from each other by wiring on the LSI so as to avoid interference with each electrode. Tape carrier type characterized in that electrodes for connecting the tape carrier for shared wiring and the tape carrier for drawing out the external wiring are formed at different positions, and both are electrically connected using these electrodes. Semiconductor device. 10. The tape carrier type semiconductor device according to claim 5, wherein L is used instead of the common wiring made of copper foil.
Wiring by the wire bonding method is used for the electrodes of the same function on SI, and the tape carrier that has been electrically insulated from these wire bonding parts is used to connect to the remaining electrodes on the LSI. A tape carrier type semiconductor device characterized in that. 11. The tape carrier type semiconductor device according to claim 10, wherein a tape carrier, which is provided with an electrode for wire bonding in addition to electrical insulation at a necessary portion, is connected to an electrode on an LSI, and then the tape carrier. A tape carrier type semiconductor device, characterized in that a common wiring portion for electrodes having the same function on the LSI is provided on a predetermined electrode on the LSI or on the LSI by a wire bonding method. 12. The tape carrier type semiconductor device according to claim 10 or 11, wherein a wire coated with an electrically insulating function is used when performing wire bonding for common wiring. Characteristic tape carrier type semiconductor device. 13. The tape carrier type semiconductor device according to claim 10, wherein the wiring portion and the tape carrier are connected by wire bonding so that both can be connected to the same electrode on the LSI. The tape carrier type semiconductor device is characterized in that electrodes are formed in a shape that does not cause interference even if they are enlarged or connected at the same position, and the electrodes are electrically connected there. 14. An anisotropic conductive sheet is used when connecting a common wiring part to a tape carrier when a LSI that requires common wiring for a plurality of electrodes on the LSI is used as a tape carrier type semiconductor device. A tape carrier type semiconductor device characterized in that by using it, electrical insulation is obtained between a common wiring portion and a wiring portion connected to other electrodes. 15. When the LSI is used as a tape carrier type semiconductor device, a common wiring portion for the same function electrode on the LSI formed on the tape carrier is unevenly distributed on one side of the electrodes on the surface of the LSI. On the other hand, a tape carrier type semiconductor device in which lead-out electrodes to the outside are concentrated on the side of the other tape carrier where the common wiring portion does not exist. 16. The tape carrier type semiconductor device according to claim 15, wherein when two types of common wiring portions are required for the electrodes on the LSI to be mounted, the common wiring portion and the lead-out wiring to the outside. A tape carrier type semiconductor device characterized in that two kinds of tape carriers are separately distributed to the left and right, and each of them is successively connected to electrodes on an LSI in such a direction that external lead wires are divided into the left and right. 17. A tape carrier type semiconductor device according to claim 1, wherein a plurality of the tape carrier type semiconductor devices are connected to the same lead frame, and the outer peripheral portion is sealed with a resin. A tape carrier type semiconductor device having a plurality of LSI chips incorporated in a package.