JPH0736713A - Program execution management device - Google Patents

Abstract

PURPOSE:To perform sufficient protection with flexibility by the same method in thread operation instructions among threads sharing the same virtual address space by providing a list for registering information on from which thread operations can be performed to the respective threads. CONSTITUTION:First, the information of an operation thread ID and a memory area ID for which a system call is executed is obtained respectively from a thread ID storage part 6 and a memory area ID storage part 5. The table of a thread operation authority storage part 7 is referred to based on the information and a pertinent entry is searched. Then, the information of a part pertinent to intra-thread state read authority within the part for indicating the operation authority of the found entry is read and whether or not read is permitted is judged. The judgement is performed in an operation authority judging part 12. When it is permitted by the judgement, the referring operation of a thread management table for reading the internal state of the permitted thread is executed to an object thread in a thread state reference execution part 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for managing the execution of program execution threads in a computer system.

[0002]

2. Description of the Related Art In recent years, it has become common to use a plurality of small computers connected to a network by improving the performance of a microphone processor. Further, due to the expansion of the use range of the microprocessor, the operating system (OS) is required to support various application ranges, and it is required that the operating system (OS) can have a flexible configuration. For this reason, conventionally, a plurality of OSs have been used properly depending on the purpose of use and the type of hardware. There is an operating system technology that is microkernelized in order to cover a wide range of applications with one OS. This gives only the minimum necessary functions to this microkernel, and the other functions are provided as a user program outside the microkernel. By doing so, it is possible to provide a plurality of conventional OS functions in the form of a user program on one microkernel, and a flexible configuration can be realized.

In such an operating system, a control unit called a process or thread is used as a control target of program execution. Each thread has its own register value, stack, etc. of the processor, executes the program only while the processor is allocated by the operating system, and after a certain period of time or when a hardware interrupt occurs, the operating system is the processor for the thread. To deallocate the and allocate the processor to another thread. Since each thread has an independent register value, it can be regarded as a processor that operates virtually in parallel.

When it is desired to operate the thread itself on such an operating system, that is, to suspend or resume the execution of the thread, or to forcibly delete the thread, or information on the thread (register value or In order to check the internal state of the stack), the operating system is provided with a thread operation instruction group, and one thread can operate another thread. Such a thread operation instruction group is
It can be used by instructing the OS as a system call from the user program.

[0005] When such a thread operation instruction is present, if a thread operation instruction can be issued from any thread, an illegal operation can be performed, so a protection function is required. For example, it is necessary to allow a thread to be forcibly killed only by a thread with a specific privilege.

Further, there is a plurality of virtual spaces, one program and one data are arranged in each virtual space, and the threads are moved only within the space.
(Reference: "Distributed operating system" Mamoru Maekawa et al., Kyoritsu Shuppan) In the case of systems such as the same thread protection in the same space, the thread protection depends on the memory space protection How to do it. However, those threads cannot be protected separately. Also, like a single virtual space system,
When all programs are arranged in one address space and there are multiple threads, thread protection requires not only memory protection but also permission setting by the operating system.

[0007] One method is to determine the owner of a thread and allow the threads to operate between threads of the same owner.
signal corresponds to this. However, this lacks the flexibility of protection between threads of the same owner, and further, cannot pass the operation privilege to threads of other owners. In addition, there is a lack of a thread protection function that enables flexible thread operation, such as enabling or disabling thread operations from threads owned by multiple owners.

[0008]

As described above, in the conventional thread execution management mechanism, there is no flexibility in setting the operation authority, or there is no protection between threads sharing the same virtual address space. It was or was very restricted.

In view of the above situation, the present invention provides flexibility in the same method for thread operation instructions not only between threads in different virtual spaces but also among threads sharing the same virtual address space. It is an object of the present invention to provide a program execution management device that has sufficient protection.

[0010]

According to the present invention, a list in which information indicating which thread can be operated is registered is provided for each thread, and the operation is permitted only when the list permits the operation. Also, the thread protection method using the memory protection mechanism can be realized without requiring new hardware for thread protection.

[0011]

According to the present invention, since there is information indicating the accessibility of each thread, the thread can be protected from an illegal operation instruction or an erroneous operation instruction. Further, since such an erroneous operation instruction can be detected, it becomes easy to detect an error (bug) in the program.

In a system in which a plurality of threads share the same logical address space, the logical address space is divided into a plurality of segments, and an access control list can be designated for each segment, By assigning a segment that uniquely corresponds to that and using the access control list of that segment as the access control list of the thread, it is possible to speed up the operation without adding a new instruction for thread operation authorization judgment to the processor instruction set. Thread access authority management becomes possible.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. (Embodiment 1) This apparatus uses an operating system (O
It is a part of the constituent elements of S) which controls the execution of the entire computer system. The OS manages memory, which is a computer resource, a processor, and peripheral devices, and controls the execution of a program called a user program that performs a practical process instructed by the user. A plurality of user programs are loaded on one device, and the OS also controls these programs.

The user program secures resources such as a physical memory necessary for execution, inputs / outputs data to / from a peripheral device, transfers data to another user program, requests processing, It is necessary to give instructions to the OS to control the execution. The instruction to the OS is given by a special means called a system call. In this embodiment, of the system calls, the control of the user program will be described.

FIG. 1 is an overall configuration diagram of this embodiment. In the program storage unit 1, a user program in which instructions to be processed by a computer are written, data to be processed, data such as a stack for temporarily storing results during processing by the computer, and the like are stored in a memory space. . The memory space is
It is divided into a plurality of areas and managed, and each area is provided with an identifier for distinguishing each other, and programs, data, and stacks are arranged in each memory area.

Further, the processor 2 which is an execution subject for interpreting and executing the program stored in the program storage unit 1 and processing data, the thread management unit 3 for managing the state in the processor, and switching of the execution state of the processor There is an execution state switching unit 4 that performs processing.

In the processor 2, the registers temporarily used during the execution of the instruction, the program counter (PC) for indicating the position of the currently executed instruction in the program storage unit, the top position of the stack data There is a stack pointer (SP) or the like that indicates that, and by exchanging a series of these data, it is possible to perform processing of a plurality of different user programs in parallel in a time-sharing manner.

A thread refers to a series of data used in the processor, and a plurality of sets of this data are prepared. By switching these threads and setting them in the processor to actually execute them, time division processing becomes possible. Become.

The memory area ID storage unit 5 stores in which memory area of the program storage unit 1 the program currently being executed exists as an ID of the memory area. This uses the value of the PC in the processor to find and store the memory area ID that is currently being executed. This memory area ID can also be regarded as the program ID currently being executed.

The thread management unit 3 has a table called a thread management table, which manages information of registers set in the processor and other information for each thread. Threads are provided with thread identifiers (thread IDs) to distinguish them from each other.

The execution state switching unit 4 suspends the thread (thread ID = 1) currently being executed on the processor,
In order to save the state of the thread (thread ID = 1) to a predetermined position in the thread management table and start another thread (thread ID = 2), the information of the thread (thread ID = 2) in the thread management table is processed by the processor. It is reset to 1 and the execution of the thread (thread ID = 2) is resumed. The execution state switching unit 4 also sets the thread ID currently being executed in the thread ID storage unit 6. The execution state switching unit 4 further includes a thread scheduling mechanism that determines which thread is set and saved, and a timer unit that instructs when to schedule (not shown).

The thread operation authority storage unit 7 holds a table relating to thread protection and stores the authority to execute an operation for each thread, and is used by the operation authority determination unit 12.

As an example in which a thread executing a user program as a system call tries to control another thread, Thread_Get_
A case of issuing the Status system call will be described.

This system call notifies the user program of the caller of this system call about the state of the thread designated by the thread ID, that is, the information about the registers of the thread. Now, it is assumed that the thread of the thread 1 (thread ID = 1) is executing the program A (memory area ID = A) and the information of the thread 2 (thread ID = 2) is to be obtained by this system call. In the program A written in C language, it is written as follows.

Err = Thread_Get_Status (2, & Thread_Statu
s); where the function Thread_Get_Status
s is a system call for obtaining thread information, the first argument 2 indicates obtaining thread ID = 2 information, and the second argument & Thread_Status is
Indicates the start position of the memory area for storing the information of the thread 2 obtained as a result of the system call. Further, whether or not the execution of this system call is successful is stored in the variable err as the return value of this function.

When the thread 1 of the program A executes this function, the thread 1 changes the execution mode of the processor from the user level to the privilege level by a system call and calls the OS. The privilege level is a dedicated level for processing by the OS.

In the called OS, the processing moves to the system call accepting unit 8 in the OS. Here, the original user program that called this system call is interrupted, the type of the requested system call and the designated argument are received, and the information is respectively received by the argument detection unit 9 and the system call type determination unit 10. Send to.

In this example, the indicated system call is
Since Thread_Get_Status is set, the system call type determination unit 10 then
Call the et_Status execution unit 11.

The processing there is performed using the thread operation authority storage unit 7 shown in FIG. This storage unit holds a table as shown in the figure. The table has each area of the operation thread ID, the target thread ID, the memory area ID in which the operation thread exists, and the thread operation authority.

The operation thread ID is the thread ID of the thread that is about to execute the thread operation system call, and the target thread ID is the thread ID of the operation target specified by the argument of this system call.
The memory area ID in which the operation thread exists is the ID of the memory area in which the program including the system call to be executed exists, and the thread operation authority indicates what kind of thread operation is possible. In this case, three authorities can be independently specified: authority to read the internal state of the thread, authority to change the internal state of the thread, and authority to stop / resume execution of the thread.

For example, in the example shown in the figure, in the system call issued by thread 1 (thread ID = 1), thread 2
This indicates that the internal state of (thread ID = 2) can be referenced and changed, but the execution / stop of the execution of thread 2 (thread ID = 2) cannot be performed. Further, the thread 1 (thread ID = 1) is the thread 3 (thread ID = 3)
Can be stopped / restarted, but other thread operations cannot be performed. Furthermore, thread 1 (thread I
D = 1) for threads other than thread 2 (thread ID = 2) and thread 3 (thread ID = 3),
It indicates that no thread operation is accepted.

In the example of the case where the thread 1 (thread ID = 1) is the target thread, the information "all" is held in the memory area ID portion in the table where the operation thread is present. Is the same regardless of which user program is executed, indicating that the effective authority depends only on the thread ID that executes the system call.

When the memory area ID column is not all, the operating authority when the system call is executed from the program existing in the memory area of the ID is defined. For example, while thread 3 (thread ID = 3) is executing program A (memory area ID = A), all operations can be performed on thread 1 (thread ID = 1). When, the operation is not possible. That is, while the thread 3 (thread ID = 3) is executing the program B (memory area ID = B), the thread 1 (thread ID =
Even if a similar system call is executed for 1), the operation cannot be performed, and thread 5 (thread ID = 5) has the same system as thread 1 (thread ID = 1) in program A (memory area ID = A). I can't operate a call. Thread operations not described in this table cannot be performed at all.

The Thread_Get_Status processing unit processes according to the steps shown in FIG. First,
In step 1, the operation thread ID and memory area ID that executed this system call are obtained from the thread ID storage unit 6 and the memory area ID storage unit 5, respectively. As described above, the thread ID currently being executed is set by the execution state switching unit 4, and the memory area ID currently being executed is
It is set from the information of the PC inside the processor. Furthermore, the target thread ID detection unit 13 obtains the target thread ID from the first argument of the system call. From the second argument, the thread information storage position detection unit 14 detects the memory position of the user program that stores the execution result of this system call.

Next, in step 2, based on the above three pieces of information, the table of the thread operation authority storage unit 7 is pulled and the corresponding entry is searched. If found, go to step 3; otherwise go to step 8 error processing unit 15
Go to.

In the search, comparison is performed in order from the top of the table, and the information of the first matching entry is used in the subsequent steps. The all part of the table field is
Means match everything. If the last entry in the table is compared and no match is found, the search fails.

In step 3, the information of the portion corresponding to the thread internal state reading authority is read out from the portion showing the operation authority of the found entry, and it is determined whether or not it is permitted. This determination is performed by the operation authority determination unit 12. If the determination is permitted, the process proceeds to step 4, and if not permitted, the error process of step 8 is performed.

In the next step 4, the reference operation of the thread management table for reading the internal state of the permitted thread is executed for the target thread. This processing is performed by the thread state reference execution unit 16. Here, the thread information, which is the internal state of the thread, is stored in the memory designated by the thread information storage position detection unit 14.

At step 5, the processing result at step 4 is judged. When the processing is successful, in step 6, a code indicating success is transmitted to the system call termination unit 17. If it fails, a code indicating the failure is transmitted to the system call termination unit 17 in step 7.

At step 8, the error code is transmitted to the system call termination section 17. Thread_Get_S
When the processing in the status executing unit 11 is completed, the process finally proceeds to the system call ending unit 17. This system
The return value returned to the user program that executed the call is returned as the return value of the system call, and the return processing is performed so that the interrupted caller user program can be executed. Perform processing to return from the level to the user level.

Another system call for operating a thread will be described below. Thread_Set_St
The system call "atus (thread ID, thread status)" is the Thread_Ge described above.
By the reverse operation of t_Status, the thread information specified by the argument is set in the thread specified by the first argument.

The internal processing of the OS is performed by the system call accepting unit 8 through the system call type determining unit 10 and then Thr
Move to the ad_Set_Status execution unit. Threa
The d_Set_Status execution unit uses Thread_G
It has a configuration in which the thread state reference execution unit 16 of the et_Status execution unit 11 is replaced with a thread state change execution unit. Internal processing is Thread_Get_Stat
Similar to us, but when searching the table of the thread operation authority storage unit 7, unlike the previous example, the authority to change the internal state of the thread is checked to determine whether or not there is authority. Then, if the user has the authority, the thread state change execution unit performs the change process. The change processing is to store the thread information specified by the second argument in the relevant portion of the relevant thread in the thread management table inside the thread management unit 3.

The system call Thread_Suspend (thread ID) is used to suspend the execution of the thread designated by the argument. This processing is performed by the Thread_Suspend execution unit, which replaces the Thread_Get_Status execution unit 11. The determination as to whether or not the user has the execution right is similar to the above, but is different depending on the authority to stop / resume the execution of the thread among the thread operation authorities. If the user has the authority, the thread stop processing execution unit in the Thread_Suspend execution unit obtains the state of the target thread from the thread management table in the thread management unit 3. Some management tables store status information. If the information is in the executable state, change to the stopped state. If it is stopped, nothing is done. When the target thread is the thread itself that issued this system call, following the above processing, control is transferred to the execution state switching unit 4 at the end of this system call, and the thread to operate next is determined and started.

As another embodiment, when the stop state can have a plurality of stop state levels, when the Thread_Suspend system call is issued in the executable state, the stop state level is changed to 0, and If it is in the stopped state, the stop level is raised by one. This level is given a large value when the stopped state is severe and the execution is difficult.

Thread_Resume (thread I
The system call D) is for resuming execution of the thread specified by the argument. This process
The Thread_Resume execution unit makes the determination as to whether or not there is an execution right, as in the Thread_Spend execution unit. If you have the authority, Th
The thread restart execution unit in the read_Resume execution unit obtains the state of the target thread from the thread management table in the thread management unit 3. There is a place where status information is stored in the management table, and if the information is in a stopped state, it is changed to an executable state. If it is already ready, do nothing.

As another example, if the stop state can have multiple stop state levels, Thread_R
When the "esume" system call is issued, if it is in the stopped state, the stop level is lowered by one. If the stopped state level is already 0, the state is changed to the executable state, and if it is already executable, nothing is done.

In this embodiment, the thread execution / resume authority is grouped into one authority. However, in order to have different authorities, the execution stop authority is defined as the authority to write the internal state of the thread and the thread execution. An embodiment in which it is possible when there are both the right to stop / resume and the authority to resume execution is possible when there are both the right to read the internal state of the thread and the right to stop / resume the execution of the thread. Is also possible.

In this embodiment, the authority to read the internal state of a thread, the authority to change it (including the authority to erase),
Although three types of authority to suspend / resume execution of a thread can be specified independently, the present invention is not limited to this. Increase the types that can be specified (the number of fields included in the operation authority of the thread operation authority storage unit),
Even if the restart authority can be specified separately, the authority to delete the thread may be provided separately.

Although the execution units corresponding to the respective system calls have been separately described above, in the actual system, these execution units are provided in parallel as much as necessary. At this time, for the common functions 13, 14, 15, 7, 12, the same or common one is used for all system calls, and the contents executed by each system call are different 16. It is only necessary to provide only those to be performed in parallel, and to distribute the processing to the corresponding execution unit in parallel with or after the operation authority determination. (Second Embodiment) Next, an example in which a time constraint is added to the thread control in the first embodiment will be described. This is a process required when the process must be completed within a predetermined time, such as a real-time process for controlling a plant.

The program structure of the embodiment is shown in FIG. There are a process control program (memory area ID = B) that actually performs real-time processing for plant control, and a real-time thread (thread ID = 5) that resides in the program and executes real-time processing.

Further, there are a process control program, a control program for controlling a real-time thread (memory area ID = C), and a control thread (thread ID = 4). In addition, a plurality of general user programs and threads other than the above may exist on the same system. Examples thereof include a debug program (memory area ID = D) for maintaining the above program, and an arbitrary thread (thread ID = 6) for debugging processing. The program arrangement in the memory space in this example is shown in FIG.

In this example, the time required for real-time processing during the operation of the plant control is from 9:00 to 17:00.
Is. During this time, the real-time thread concentrates on its processing and is not controlled by other threads. The exception is control from the controlling thread. That is, only the control thread that executes the control program can perform only the processing such as the stop when the plant operates abnormally.

After 17:00 when the operation of the plant ends, real-time processing is not required, so the above-mentioned limitation is eliminated, and ordinary threads can control. This enables the debugger to control the real-time red when debugging the process control program, which is an effective measure.

The overall configuration of the system of this embodiment is the same as that of the first embodiment.
Is almost the same as FIG. Only the added function will be described with reference to FIG. First, the configuration of the table of the thread operation authority storage unit 7 changes as shown in FIG. An entry indicating the expiration date is newly added to the table. Here, information indicating at what time the set thread operation authority is valid is held.

In order to realize the plant control example using the above settings, the thread operation authority is set in the table of the thread operation authority storage unit 7 as shown in FIG. It should be noted that new setting / deletion / modification to this table is carried out by a dedicated system call from the user program. At that time, it is also checked whether or not there is a contradiction with the authority set up to now, and the setting of the table is reflected in a form in which the setting is consistent.

By setting (1) in the table, the thread ID = from the operating hours of 9:00 to 17:00.
The control thread of No. 4 can perform all thread operations on the real-time thread of thread ID = 5 during execution of the control program of memory area ID = C. Further, by the setting of (3), the same operation can be performed after 17:00.

Threads other than the control thread with the thread ID = 4 have the threat ID = by the setting of (2).
9:00 to 1 for 5 real-time threads
All threads cannot be operated until 7:00. However, after that time period, since the operation thread column is all in the setting of (3), all operations can be performed from any thread.

In order to realize the above control, the current time storage section 18 is added to the configuration of the first embodiment. Then, in step 2 of FIG. 3 in the first embodiment, the table is searched by adding the current time information. Everything else remains the same.

An example in which the table of the thread operation authority storage unit 7 is changed as shown in FIG. 7 will be described below. This is a table in which a memory area ID field in which the target thread exists is newly added to the conventional table. In this case, the specified operation thread executing the program in the specified operation memory area limits the thread operation authority for the specified target thread in the specified target memory area.

According to this, in order to realize the process control real-time processing as in the previous example, the arrangement of the memory and the threads can be arranged as shown in FIG. In this case, unlike the previous example, a dedicated control thread for executing the control program and a dedicated real-time thread for process control are not required and can be realized by arbitrary threads.

That is, it is possible to realize a thread configuration in which a series of processing is performed while transferring control between a plurality of programs. The designation of the table of the thread operation authority storage unit 7 in this example is as shown in FIG. That is, the memory area C (control program) is described by the description of (1) in the table.
For any thread executing the memory area B (process control program), any thread executing the above can perform all thread operations from 9:00 to 17:00. Also, according to the description of (3), 1
All operations can be performed after 7:00. However, according to the description of (2), from any thread executing a memory area other than the memory area C to all threads existing in the memory area B from 9:00 to 1
No thread operation is possible during 7:00. However, after 17:00, all thread operations can be performed according to the description in (3).

The overall configuration including the thread operation authority storage unit 7 is shown in FIG. A new addition is the target memory area ID detection unit 19. This is to detect the memory area ID in which the thread currently exists from the target thread ID designated by the system call using the thread management table. The detection flowchart is shown in FIG.

Then, in step 2 of FIG. 3 in the first embodiment, the current time information and the target memory area ID information are added for the search. Everything else remains the same. (Third Embodiment) In the third embodiment, control of permission / prohibition of thread operation and memory management are performed in cooperation with each other.

FIG. 10 shows a memory management mechanism in this embodiment. The logical address space as shown in the figure has a size of 64 bits and is divided into some areas (segments).

Here, the address 64 bits are divided into two fields, the upper 32 bits indicate the segment number, and the lower 32 bits indicate the offset within the segment. The size of one segment is variable.

This segment is protected by the memory protection function of the memory management mechanism so that each of them will not be illegally accessed. This memory protection function is for checking whether or not the access is valid at high speed when the processor accesses the memory, and this is managed by the OS.

FIG. 11 illustrates the memory protection function, which is realized by the memory management unit MMU30. This MMU includes a thread ID storage unit 25, which is a register that holds the number CURTH of the thread currently being executed, and a program counter (P
C) A segment extraction unit 26 that extracts the segment number in which the program currently being executed exists from the value of 22, a segment extraction unit 27 that extracts the segment number of the address (23) to be accessed from now, and memory protection information. The associative memory TLB 28, which is a cache for high-speed searching, is provided. Each entry of the associative memory TLB includes an operation thread ID, a target segment ID,
It is composed of fields of an operation segment ID (the above is referred to as “tag”) and memory access authority (read R, write W, execute X).

Here, the 64-bit logical address ADD
The upper 32 bits of R are the segment number MSID, and the lower 32 bits are the in-segment offset OFS,
The operation of this memory protection mechanism will be described below. When the processor attempts to access the memory of a certain logical address ADDR, the segment extraction unit 27 of the MMU causes the segment extraction unit 26 to set ADDR to the segment number MSI.
D and the offset OFS in the segment are separated. Further, the segment value PCMSID in which the program currently being executed is present is extracted from the value of the program counter PC indicating the program currently being executed. These MSID and PCMSI
D and CURTH indicating the current thread number are added to the associative memory TLB 28. The TLB looks for entries with tags that match these inputs. However, if there is a field in the tag such that all the bits are 1, it is considered as an item that matches any input. For example, if the field of the operation segment ID is all 1s, even if the operation thread ID exists in the segment of the operation thread, the entry having the tag is selected as being suitable for the current situation.

Then, if there is a matching entry,
The TLB outputs the content PERM of the memory access authority field for it. The access authority determination unit 29 compares the value of PERM with the signal ACCESS representing the content of the type storage unit 24 of the access to be performed, and determines whether or not this memory access request is permitted. If not permitted, the FAULT signal is returned to the error processing unit 31 of the processor 21. Also, when no matching tag is found in the TLB 28, the FAULT signal is similarly returned to the processor 21. If permitted, the MMU 30 translates the virtual address output by the processor into a physical address by an address translation mechanism (not shown) and outputs it to the system address bus. The operating system realizes the memory access protection required by the user and the operating system by appropriately updating the contents of the TLB.

In a system having such a memory management mechanism, a unique segment is allocated to each execution thread as shown in FIG. 12A, and a user rewritable portion of thread information is placed in the segment. By doing so, it is possible to reduce the protection attribute of thread operation to the protection of memory operation, without adding new hardware.
Access control for thread operations can be performed using memory protection hardware.

Similar to the first embodiment, an example will be described in which the thread 1 executing the program on the program segment A tries to access the control information of the thread 2. Since the memory management mechanism described above is provided unlike the case of the first embodiment, different memory protection conditions can be set in programs on different memory segments even within the same logical address space. Therefore, by placing the programs that make up the operating system in a certain segment and setting the memory protection conditions so that the programs in that segment can access any memory, the memory access is equivalent to the transition to the privilege level. The effect of can be obtained. In this case, the system call to the OS can be made not by a special instruction but by a normal inter-segment subroutine call instruction.

Here, it is assumed that the thread information has a one-to-one correspondence with the thread number 1 as shown in FIG. 13 and the thread number 2 as the segment number 102. The operating system records this correspondence in the thread management table as shown in FIG.

FIG. 12B shows an example in which the contents of the TLB 28 are set so as to operate in the same manner as the operation example shown in the first embodiment. For example, in this example, when thread 1 reads the memory contents in segment 102 to check the internal information of thread 2 while thread 1 is executing the program in segment 91, MMU 30 uses segment number 10 from the virtual address that the processor wants to access.
2 is extracted, and this, thread number 1 and segment number 9
The TLB 28 is searched by using 1 as a key, and since there is a matching entry, the memory protection information for that is output to the access authority determination unit 29. Read permission (R) in this example
Access is allowed.

As another example, when thread 1 tries to access the information of thread 4 in the situation of FIG. 12B, the memory in segment 104 is accessed, but thread number 1 and segment number 104 are assigned. Search TLB as a key. In this case, since there is no matching entry, the TLB outputs a mismatch signal, and the MMU sends a FAULT signal indicating that access is not permitted to the processor.

That is, in this embodiment, the contents of the thread management table in the first embodiment are arranged at a predetermined position in the logical address space, and the thread operation authority storage unit is replaced with the TLB so that the same operation as in the first embodiment is performed. It is the one.

[0076]

As described in detail above, according to the present invention, it is possible to appropriately protect a thread from an operation by the thread. Moreover, by using the memory protection mechanism, high-speed thread operation protection can be performed without the need for new hardware.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an internal configuration example of a thread operation authority storage unit 7 in FIG.

FIG. 3 is a flowchart showing the operation of the system of this embodiment.

FIG. 4 is a diagram showing a program configuration example in the second embodiment.

FIG. 5 is a thread operation authority storage unit 7 according to the second embodiment.
FIG. 3 is a diagram showing an example of the internal configuration of FIG.

FIG. 6 is a diagram showing another program configuration example according to the second embodiment.

7 is a diagram showing an internal configuration example of a thread operation authority storage unit 7 corresponding to FIG.

FIG. 8 is a diagram showing an overall configuration of a system for the second embodiment shown in FIG.

9 is a flowchart showing the operation of the target memory area ID detection unit 19 of FIG.

FIG. 10 is an explanatory diagram of a logical address space according to the third embodiment.

FIG. 11 is a diagram showing an overall configuration of a system according to a third embodiment.

FIG. 12 is an explanatory diagram of a relationship between thread information and a segment according to the third embodiment and a diagram showing a setting example of the TLB 28 in FIG.

FIG. 13 is a diagram showing an example of arrangement of thread control information in a logical address space according to the third embodiment.

[Explanation of symbols]

1 ... Program storage unit, 2, 21 ... Processor, 3
... thread management unit, 4 ... execution state switching unit, 5 ... memory area ID storage unit, 6 ... thread ID storage unit, 7 ... thread operation authority storage unit, 8 ... system call reception unit,
9 ... Argument detection unit, 10 ... System call type determination unit, 11 ... System call execution unit, 12 ... Operation authority determination unit, 13 ... Target thread ID detection unit, 14 ... Operation type determination unit, 15 ... Error processing unit , 16 ... Thread state reference execution unit, 17 ... System call end unit,
18 ... Current time storage unit, 19 ... Target memory area ID detection unit, 22 ... Program counter, 23 ... Access address storage unit, 24 ... Access type storage unit, 25 ...
Thread ID storage unit, 26, 27 ... Segment extraction unit, 28 ... TLB, 29 ... Access right determination unit,
30 ... MMU.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Hideki Yoshida 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research and Development Center (72) Inventor Toshinari Takahashi Komukai-Toshiba, Kawasaki-shi, Kanagawa Town No. 1 Toshiba Corporation Research & Development Center

Claims (4)

[Claims] 1. A means for executing a program by a plurality of threads executed in parallel, a means for storing authority information indicating from which thread a thread can be operated, and a thread adding an operation to another thread. And a means for verifying whether or not the user has the authority to perform this operation based on the authority information, and a means for permitting execution of the operation when the authority is verified. Program execution management device. 2. The information for designating a time interval is stored in addition to the authority information of the operation on the thread, and the verification is performed so that the authority is applied during the designated time interval. Item 1. The program execution management device according to item 1. 3. A means for executing each program arranged in a logical address space divided into a plurality of areas by a plurality of threads executed in parallel, and a thread when a thread exists in which area. A means for storing authority information indicating whether or not the thread can be operated, and a means for verifying whether or not a thread has an authority to perform this operation based on the authority information when an operation is applied to another thread from a certain area. A program execution management device comprising: means for permitting execution of the operation when it is verified that the user has the authority. 4. A means for executing each program arranged in a logical address space divided into a plurality of areas by a plurality of threads executed in parallel, and a memory access indicating which thread can access a certain area. Means for storing permission / denial information, means for verifying whether or not this access is permitted by the permission / denial information when a thread attempts to access another area, and access if it is verified as permitted A thread operates on another thread by storing the information of each thread in an area in the logical address space secured corresponding to each thread, provided with means for converting the logical address to be converted into a physical address. When trying to add, it is verified that the authority to perform this operation is verified by the permission or denial indicated by the permission or denial information. Program execution management apparatus according to symptoms.