JPH0736572A - Reset circuit - Google Patents

Abstract

PURPOSE:To output a reset signal by which it is possible to facilitate a countermeasure to the restoration of the malfunction of a system by combining a capacity which holds a power supply voltage when the power supply voltage supplied to the corresponding system is dropped, with a MOS transistor which is turned to an 'on' state accompanying the drop of the power supply voltage. CONSTITUTION:In a time zone T2 in a state that a high potential power supply terminal 21 is dropped and the system is abnormal, a potential V21 of the high potential power supply terminal 21 is gradually dropped, a terminal voltage V6 of a capacitor 6 is held since a PMOS transistor 1 is diode-connected, and a state that V21<V6 is obtained. Then, a PMOS transistor 2 and a NMOS transistor 5 are moved to an 'on' state, and a reset signal 101 is outputted from an output terminal 23 at that time. Thus, the reset signal 101 possible to sufficiently deal with the restoration of the malfunction of the system can be outputted.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to reset circuits.

[0002]

2. Description of the Related Art A conventional reset circuit has power supply terminals 25 and 27 and an output terminal 26 as shown in FIG.
Corresponding to the resistor 13, the capacitor 14 and the inverter 15
And the potential at the connection point between the resistor 13 and the capacitor 14 reaches the threshold voltage of the inverter 15 as a reset signal via the inverter 15 via the output terminal. When the potential at the connection point between the resistor 13 and the capacitor 14 exceeds the threshold voltage of the inverter 15, the output level of the inverter 15 is inverted and output, and the reset signal is released.

[0003]

The above-mentioned conventional reset circuit is constructed by using an inverter, and the on / off of the reset signal is controlled based on the threshold voltage of the inverter. However, it is generally difficult to keep the threshold voltage of the inverter constant, and the threshold voltage fluctuates due to fluctuations in the power supply voltage and temperature characteristics. In particular, when it is necessary to detect that a malfunction has occurred in the system due to fluctuations in the power supply voltage and output a reset signal, the reset signal is not output due to fluctuations in the threshold voltage of the inverter, and this Due to
There is a drawback that a situation occurs in which the malfunction of the system cannot be repaired.

[0004]

In a reset circuit according to a first aspect of the present invention, a source is connected to a high-potential power supply terminal, and a gate and a drain are connected to form a diode connection.
A MOS transistor and a source are connected to a gate and a drain of the first PMOS transistor through a first resistor, a gate is connected to the high potential power supply terminal, and a drain is at a low potential through a second resistor. A second PMOS transistor connected to the power supply terminal; a drain connected to the output terminal, a gate connected to the drain of the second PMOS transistor, and a source connected to the low potential power supply terminal; , The first
And a capacitance connected between the gate and drain of the PMOS transistor and the low-potential power supply terminal.

In the reset circuit of the second invention, the source is connected to the low-potential power supply terminal, the gate and the drain are connected to form a diode connection, and the source is connected via the first resistor. The first N
A second NMOS transistor connected to the gate and drain of the MOS transistor, the gate connected to the low potential power supply terminal, the drain connected to the high potential power supply terminal through the second resistor, and the drain output terminal A PMOS transistor having a gate connected to the drain of the second NMOS transistor and a source connected to the high potential power supply terminal; and the first NMOS.
It is configured to include a capacitor connected between the gate and drain of the transistor and the high-potential power supply terminal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment corresponds to the high potential power supply terminal 21, the low potential power supply terminal 22 and the output terminal 23, and corresponds to the PMOS transistors 1 and 2 and the resistor 3.
And 4, an NMOS transistor 5, and a capacitor 6.

In FIG. 1, during normal operation of the system using this embodiment, the high-potential power supply terminal 21 is supplied with a stable high-potential power supply voltage V _cc, and the low-potential power supply terminal 22 is grounded. Be present. Therefore, in this normal operation state, the voltage V ₂₁ of the high-potential power supply terminal 21 has a voltage value equal to the stable power supply voltage V _cc , and a predetermined amount of charge is stored in the capacitor 6. ,
The voltage V ₆ across the terminals becomes a voltage approximately equal to V _cc . Further, in this state, both the PMOS transistor 2 and the NMOS transistor 5 are in the off state, and the reset signal 101 is not output from the output terminal 23.

FIG. 2 shows the voltage V ₂₁ of the high-potential power supply terminal ₂₁ and the terminal voltage V of the capacitor 6 with the passage of time.
₆ is a diagram showing a change in ₆ and a state of generation of a reset signal 101, where T ₁ and T ₃ indicate a time period during which the power supply voltage V _{cc is} normally supplied, and T ₂ indicates that the high-potential power supply terminal is lowered. The power supply voltage is fluctuating and the system is in the abnormal state during the time zone. In the time period T ₂ , the potential V ₂₁ of the high potential power supply terminal 21 gradually decreases, but the terminal voltage V ₆ of the capacitor 6 is held because the PMOS transistor 1 is diode-connected, and V ₂₁ <V ₆ It becomes a state. As a result, the PMOS transistor 2 and the NMOS transistor 5 are turned on, and at that time,
The reset signal 101 is output from the output terminal 23 as shown in FIG. Since an inverter is not used in this embodiment, unlike the case of the conventional example, it is possible to sufficiently cope with the malfunction of the system.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram showing this embodiment. As shown in FIG. 3, this embodiment corresponds to the high potential power supply terminal 24, the low potential power supply terminal 25, and the output terminal 26, and corresponds to the NMO.
S transistors 7 and 8, resistors 9 and 10, and P
It is configured to include a MOS transistor 11 and a capacitor 12. This embodiment is the PMO in the first embodiment described above.
In this embodiment, the S transistor and the NMOS transistor are replaced with an NMOS transistor and a PMOS transistor, respectively.

In FIG. 3, during normal operation of the system using this embodiment, the high-potential power supply terminal 24 is supplied with the stable high-potential power supply voltage V _cc, and the low-potential power supply terminal 25 is grounded. Be present. In this normal operation state, the voltage V ₂₄ of the high-potential power supply terminal 24 has a voltage value equal to the power supply voltage V _cc , and the inter-terminal voltage V ₁₂ of the capacitor 12 becomes a voltage substantially equal to the power supply voltage V _cc. ing.
Further, in this state, both the NMOS transistor 8 and the PMOS transistor 11 are in the off state, and the reset signal is not output from the output terminal 26. On the other hand, in the abnormal state of the system in which the power supply voltage supplied to the high-potential power supply terminal 24 is lowered, the potential V ₂₄ of the potential power supply terminal ₂₄ is lowered,
The terminal voltage V ₁₂ of the capacitor 12 is held because the NMOS transistor 7 is diode-connected, and the state becomes V ₂₄ <V ₁₂ . As a result, the NMOS transistor 8 and the PMOS transistor 11 are turned on, and the reset signal is output from the output terminal 26 at that time. Also in the present embodiment, unlike the case of the conventional example, the point that it can sufficiently cope with the malfunction recovery of the system is similar to the case of the first embodiment.

[0012]

As described above, according to the present invention, there is provided a capacitor that holds the power supply voltage level when the power supply voltage supplied to the corresponding system drops and a MOS transistor that is turned on when the power supply voltage drops. By being configured in combination, there is an effect that when the power supply voltage fluctuates, the power supply fluctuation can be accurately sensed and a reset signal that can sufficiently deal with the malfunction recovery of the system can be output.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing an operating state of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional example.

[Explanation of symbols]

 1, 2, 11 PMOS transistors 3, 4, 9, 10, 13 Resistors 5, 7, 8 NMOS transistors 6, 12, 13 Capacitance 15 Inverter

Claims (2)

[Claims] 1. A first PMOS transistor having a source connected to a high-potential power supply terminal, a gate and a drain connected to each other and a diode connection, and a source having a gate connected to the first PMOS transistor via a first resistor. And a drain, a gate connected to the high-potential power supply terminal, a drain connected to a low-potential power supply terminal through a second resistor, and a drain connected to the output terminal, The gate is the second P
An NMOS transistor connected to the drain of the MOS transistor and having a source connected to the low-potential power supply terminal; a capacitor connected between the gate and drain of the first PMOS transistor and the low-potential power supply terminal; And a reset circuit. 2. A first NMOS transistor having a source connected to a low potential power supply terminal, a gate and a drain connected to each other and a diode connection, and a source having a gate connected to the first NMOS transistor via a first resistor. And a drain, a gate connected to the low-potential power supply terminal, a drain connected to a high-potential power supply terminal via a second resistor, and a drain connected to the output terminal, The gate is the second N
A PMOS transistor connected to the drain of the MOS transistor and having a source connected to the high potential power supply terminal; a capacitor connected between the gate and drain of the first NMOS transistor and the high potential power supply terminal; And a reset circuit.