JPH073450B2 - Fault location method for DC electric railway feeder circuit - Google Patents

Description

The present invention relates to a fault point locating method for a DC electric railway feeding circuit.

This type of fault location method is well known in principle. This will be explained based on the principle diagram of FIG.
If a short-circuit fault occurs at a point, the following equation holds until the high-speed circuit breakers 54F of both substations A and B that sandwich the fault point open.

However, a = r / L (3) where iA is the fault current flowing in the substation A, iB is the fault current flowing in the substation B, Eo is the feeding voltage, r is the resistance per unit length, and L is the Inductance per unit length, l
Is the distance from the substation A to the fault point p, and D is the distance between both substations.

On the other hand, the following relationship exists between the distance from each substation to the fault point p and iA, iB if the internal resistance of the substation is omitted.

l: (D-1) = iB: iA (4) Therefore, when l is obtained from (1) to (4), Therefore, the distance l to the failure point p can be obtained from this equation. In this case, the average value of iA and iB instead of ▲
The same relationship holds even if ▼ and ▲ ▼ are used.

If possible, it is more accurate to use the orientation formula (6) based on the average value of the current in order to reduce the current detection error.

For simplicity of explanation, the internal resistance of the substation was omitted, but when the substation has internal resistance, the measured current sharing ratio is measured. By multiplying by a correction factor due to the internal resistance of the substation, correct orientation can be easily achieved.

By the way, what should be noted when locating the failure point in the above (6) is that ▲ ▼ and ▲ ▼ must be values at the same time. If the values are not at the same time, the above theoretical formula does not hold and the fault point cannot be located. For this reason, research has been conventionally performed to measure iA and iB at the same time. The technique disclosed in Japanese Patent Publication No. 53-12058 is one solution for measuring iA and iB at the same time. However, since this conventional technique is to connect a connecting line between adjacent substations and to secure iA and iB at the same time through this connecting line, it is related to the long distance between adjacent substations. The cost for establishing a communication line has become enormous, and there was a problem in putting it to practical use.

Therefore, the present invention provides an extremely useful method in which iA and iB can be synchronized at the same time without connecting any connecting line between the substations.

Thus, in the present invention, the current detectors are provided on the feeders of both substations A and B that sandwich the fault point, and the average value of the detected current in the same time period before the breaker is opened ▲ ▼, ▲ A method of locating a failure point from ▼, wherein a storage operation processing circuit is separately connected to each of the current detectors, and by this circuit,
The detected currents iA (t) and iB (t) of the current detector are stored and delayed for a predetermined time to obtain the currents ΔiA (t) and ΔiB (t) which are the difference between the detected current and the delayed current. , ΔiA (t) and ΔiB before the circuit breaker opens
The maximum time point Tm of (t) is searched for, and the average value of the detected current from that time point Tm to the predetermined time To past is further calculated.
The gist is to calculate ▼ and ▲ ▼, and to perform the fault point localization based on the data of the average values ▲ ▼ and ▲ ▼ output from each storage operation processing circuit.

The method of the present invention will be described below with reference to the embodiments shown in the drawings. In FIG. 2, 1 is a bus bar, 2A and 2B feeders, 3 is a train line, 4A and 4B are high-speed circuit breakers (hereinafter simply referred to as circuit breakers) inserted in the feeders, and 5A and 5B are As a current detector for detecting the current of the feeder, for example, a Hall generator is used. 6A and 6B are unsaturated transformers that detect current changes at the time of failure, RA and RB are failure detection relays that generate start signals based on the detection signals of these transformers 6A and 6B, and 7A and 7B are memory operation processing circuits. Detection current iA (t), iB of the current detector 5A, 5B
An AD converter ADC for converting (t) into a digital signal, a computer CPU for performing the various arithmetic processes described below, and a sending section F for sending ▲ ▼, ▲ ▼ processed by the CPU to the orientation center 8. And an oscillating unit OSC. It is necessary to use a stable oscillator OSC with the same oscillation frequency in both arithmetic circuits 7A and 7B. The computer CPU stores the detected currents iA (t) and iB (t) in a cycle determined by the oscillation frequency of the oscillator OSC. The period of the oscillator OSC is 1 mS in this embodiment, and
The CPU stores the detected currents iA (t) and iB (t) in the past 100 mS. Then, it is rewritten to a new detection current in units of 1 mS. This storage operation is also performed during normal times when no failure has occurred. If a short circuit failure occurs in the feeder circuit, the computer CPU operates as follows and calculates ▲ ▼ and ▲ ▼.

First, when a failure occurs in the feeder circuit, the currents iA (t) and iB (t) flowing in the feeders 2A and 2B are changed to the values shown in FIGS. 3 (a) and 3 (d).
Changes as shown by the solid line. That is, although the gradients are different, a large current due to the occurrence of a failure starts to flow simultaneously.
Tk and Tl in the figure are the times when the circuit breakers 4A and 4B are opened. The computer CPU stores the value of this current,
Receiving the fault recognition signals [the signals shown in FIGS. 3 (c) and 3 (f)] from the fault detection relays R _A and R _{B for} detecting faults.

At this time, the CPU reversely stores the detection current iA stored for a certain period (longer than the maximum value of the period from the occurrence of an accident until the fault recognition signals from the fault detection relays R _A and R _B occur). Currents iA (t-ΔT) and iB (t-ΔT) delayed by a certain time while calling the values of (t) and iB (t).
Call the value of. Then, the detected currents iA (t), iB
The delayed current iA (t−ΔT), iB from the value of (t)
The difference between the values of (t−ΔT) is calculated, and this is the difference current ΔiA.
(T) and ΔiB (t). The phantom lines in FIGS. 3 (a) and 3 (d) respectively represent the delayed current iA (t
-[Delta] T), iB (t- [Delta] T), and FIGS. 3 (b) and (e) show the values of the difference currents [Delta] iA (t) and [Delta] iB (t), respectively. [These currents iA (t-Δ
T), iB (t−ΔT), ΔiA (t), ΔiB (t) are not actual currents, but are shown to explain the internal processing of the CPU] ΔiA (t) = iA (t) − iA (t-ΔT) (7) ΔiB (t) = iB (t) -iB (t-ΔT) (8) Here, the delay time ΔT can be set as appropriate, but in any case, the failure occurs. Time to open the circuit breaker
Do not be longer than Tk and time Tl. That is, the delay time ΔT is set so that the values of the currents iA (t) and iB (t) measured from the occurrence of the failure until the delay time ΔT passes are always increased. In the present embodiment, as an example, Ten
stipulated in mS.

When the delay time ΔT is set as described above, the difference current Δ
iA (t) and ΔiB (t) are as shown in (b) and (e) in the same figure, and the detected current iA (t), iB (t) must be detected from the occurrence of the failure of the circuit breakers 4A, 4B before opening. Will start to increase due to the influence of the increase of .tau. And the delay time Δ
When T has elapsed, the difference currents ΔiA (t) and ΔiB (t)
Starts to decrease under the influence of the delayed current iA (t-ΔT) and iB (t-ΔT) subtraction, and reaches a maximum value when the delay time ΔT has just passed from the time when the hometown was generated.

Therefore, the computer CPU determines that the difference current ΔiA
It suffices to detect the time Tm at which (t) and ΔiB (t) become a maximum value and a certain value or more at which it can be recognized that the current is a fault current, not just a change in the load current. In other words, this time Tm is the time when the delay time ΔT has elapsed from the time of the accident at any of the substations A and B, so the determination of the time Tm was made independently at both substations A and B. Even if
At each substation A, B, the time at which the delay time ΔT has elapsed can be determined reliably and easily from the time of failure occurrence.

Since this delay time ΔT is the same in the computer CPUs of both substations A and B, the time Tm at which the maximum value of the difference currents ΔiA (t) and ΔiB (t) calculated by both computer CPUs is the same. It can be the time. As a result, the same time property of the detected current is ensured even if the substations A and B are not connected. And the computer CP
U further integrates the detected currents iA (t) and iB (t) in the past for a predetermined time To from this time Tm, and the average value ▲
Ask for ▼ and ▲ ▼. Average value of each current ▲ ▼, ▲
▼ are respectively sent from the sending section F to the orientation center 8.
At the orientation center 8, these average currents ▲ ▼, ▲
The data of ▼ is processed based on the equation (6) and the fault point is located. In this embodiment, the signals from the relays RA and RB are used as the starting vibration of the computer CPU, but other signals, for example, the photodetector that detects the arc at the time of opening the opening operation of the circuit breakers 4A and 4B. It is also possible to use a signal or the like detected by, for example.

Next, the above embodiment deals with a general case where both iA (t) and iB (t) increase monotonically until the circuit breaker opens, for example, a resistive fault near one of the substations. In the case of occurrence, the fault current iB (t) flowing in the substation on the far side does not increase monotonously, and may have a node in the middle of the increase as shown in FIG. Therefore, the current ΔiB (t), which is the difference between the detected current and the delay current, has two local maxima as shown in the figure, and when the second and local maxima are larger than the first local maxima. Is a problem. That is, in this case, if the time point at which ΔiB (t) becomes the maximum is simply searched for, it is not possible to secure the same-time property of iA (t) and iB (t), and the theoretical formula (6) cannot be established. . However, if we grasp the first maximum value of ΔiB (t), iA (t) and iB
Since the same time property of (t) can be secured, it can be said that the program of the computer CPU that can always grasp the first maximum value should be adjusted. To do this, the change Ii (described later) at each instant of ΔiA (t) and ΔiB (t) is determined in the computer CPU, and the time when the change Ii first changes from positive to negative can be grasped. Good. More specifically, the change Ii of ΔiB (t) at time ti is now represented by Ii = ΔiB (ti) −ΔiB (ti−Δt) (7). If ΔiB (t) does not reach the first maximum value and is increasing, then Ii> 0. Then, when the maximum value is passed, Ii <0 because it decreases for a certain period.

Therefore, this change in Ii in the computer is detected and Ii
It suffices to be able to grasp the time when is first turned from positive to negative.

In addition, (i) in FIG. 4 is a start signal from the relay RA, (e)
Indicates a start signal from the relay RB.

Since the fault locating method of the DC feeder circuit according to the present invention is performed as described above, the electric currents of feeder cables are separately detected at both substations A and B, which sandwich the fault point, and the storage operation is performed. Although the processing circuits 7A and 7B process the signals separately, the average values ▲ ▼ and ▲ ▼ of the detected current during the same time period before the breaker of each feeder is opened can be calculated. As a result, it is possible to accurately locate a fault point without establishing a connecting line between both substations.

[Brief description of drawings]

FIG. 1 is a principle diagram of the fault location method, FIG. 2 is a diagram showing an example of an apparatus for carrying out the method of the present invention, and FIG. 3 is a waveform diagram for explaining the operation of the apparatus of FIG. , FIG. 4 is a waveform diagram for explaining the operation of the apparatus when a resistive failure occurs near the A substation. 2A, 2B: Feeder, 4A, 4B: Circuit breaker, 5A, 5B: Current detector, RA, RB: Fault detection relay, 7A, 7B: Memory arithmetic processing circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuzo Kitagawa 4-4-10 Segawa, Minoh City, Osaka Prefecture Tsuda Denki Keiki Co., Ltd.

Claims (1)

[Claims] 1. A current detector is provided on the feeders of both substations A and B sandwiching a fault point, and the average current ▲ ▼, ▲ ▼ of the detected current during the same time period before the breaker is opened breaks down. A method for locating a point, in which a storage operation processing circuit is separately connected to each of the current detectors, and the detected currents iA (t) and iB (t) of the current detector are stored by this circuit. Also, after delaying for a certain period of time, the currents ΔiA and ΔiB of the difference between the detected current and the delayed current are obtained, and
And search for the time point Tm where ΔiB becomes maximum, and
Average value of detected current from Tm to the specified time To past ▲
DC electric railway feeders characterized by causing ▼ and ▲ ▼ to be calculated, and by using the data of the average values ▲ ▼ and ▲ ▼ output from each storage operation processing circuit Circuit fault location method.