JPH07336600A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To project 2-dimension image information as linear information in which row and column directions are independent and to increase the number of picked up images by arranging transistor(TRs) outputting charge in the row and column directions for each picture element with respect to the solid- state image pickup element so as to provide a summing function in the unit of rows and columns. CONSTITUTION:A photoelectric conversion element 11 providing the output of charge to a row read line Lv based on a row selection signal phiVi and a column read line Lh based on a column selection signal phiHi respectively, a 1st charge addition element 12 adding charges on row read lines Lv based on a row reset signal phiRV and a 2nd charge addition element 13 adding charges on column read lines Lh based on a column reset signal phiRH and are provided. Furthermore, a switching element Sv controlling the output of the 1st charge addition element 12 based on the row selection signal phiVi is provided and a switching element Sh controlling the output of the 2nd charge addition element 132 based on the row selection signal phiHVi is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to improvement of an XY address type charge read circuit in which a field effect transistor (MOSFET) is arranged in each pixel. is there. recent years,
With the development of integrated circuit technology for semiconductor devices, the number of pixels and the size of pixels in the solid-state imaging device are increasing. Further, a solid-state image sensor is adopted as an eye (artificial retina) of various robots.

According to this, there is a visual information processing chip to which a three-dimensional integrated circuit technology is applied. This is formed by stacking a solid-state image sensor and a processing circuit on the same chip. For example, a 5 × 5 pixel optical sensor is provided in the uppermost layer, the light received therein is converted into an electric signal, which is converted into a digital signal by the AD converter in the intermediate layer, and by the logical operation circuit in the lowermost layer. , The digital signal is smoothed
This is a type for which contour extraction is performed.

Further, a solid-state image pickup device having a function of detecting the position and long axis direction of an image projected on a chip by arranging a light receiving element at the intersection of a resistance network has been devised. However, the image information obtained from the solid-state image sensor is taken into an external computer and subjected to image processing, so that the data processing speed is significantly reduced. Therefore,
Transistors that output charges in the row and column directions are arranged for each pixel, and two-dimensional image information is projected as independent one-dimensional information in the row and column directions by providing an addition function for each row and column. Therefore, an element that can increase the number of captured images is desired.

[0004]

2. Description of the Related Art FIGS. 8 and 9 are explanatory views of a conventional example. FIG. 8 is a configuration diagram of a solid-state imaging device (2 × 2) according to a conventional example, and FIG. 9 shows operation waveform diagrams thereof. For example, as shown in FIG. 8, the solid-state image pickup device of the XY address system which outputs the serial image data DOUT has a photoelectric conversion cell array 1, a vertical shift register 2, a horizontal shift register 3, and a read transistor To.
1, To2 and output amplifier 4. The photoelectric conversion cell array 1 has four photodiodes D1 to D4 and switching transistors M1 to M4.

Next, the function of the solid-state image pickup device will be described. For example, in FIG. 8, the row shift signal S11 as shown in FIG. 9 is output from the vertical shift register 2 to the transistors M1 and M2 while the diodes D1 to D4 receive light and generate electric charges. The row selection signal S12 is output to M3 and M4, and the transistors To1 and To
The column selection signals S21 and S22 are output to 2 respectively.

As a result, the output amplifier 4 outputs the serial image data DOUT. For example, S11, S21 =
At “H” (high) level, S12, S22 = “L” (low) level, the charge detected by the diode D1 is output from the read line Ld1 to the data bus Ld0, and is converted into a voltage by the output amplifier 4. Is output. Also,
At S11, S22 = "H" level and S12, S21 = "L" level, the charges detected by the diode D2 are output from the read line Ld2 to the data bus Ld0. Furthermore, S
At 12, S21 = “H” level and S11, S22 = “L” level, the charge detected by the diode D3 is read out by the read line L.
The data is output from d1 to the data bus Ld0, and S12 and S22 =
At "H" level, S11, S21 = "L" level, the charges detected by the diode D4 are output from the read line Ld2 to the data bus Ld0. The charge on the bus Ld0 is converted into a voltage by the output amplifier 4 and output.

[0007]

By the way, according to the conventional solid-state image pickup device, it is possible to add the charges output to the data bus Ld0 at the input portion of the output amplifier 4 and convert the charges into a voltage. . However, it is difficult to add signals of different reading times such as the diodes D1, D3 and D2, D4, and read the added charge detected by the diodes D1, D2 in the column direction, and the diode D3. The added charge detected by D4 cannot be read out in the column direction. This allows the 2D image information to be displayed in the row direction (vertical direction) and the column direction (horizontal direction).
There is a problem in that it is difficult to project as the one-dimensional information of 1.

Thus, when the solid-state image pickup device is applied to a pattern inspection apparatus or the like and there is a request to extract the edge portion of the image pickup target, the output amplifier 4
It is necessary to once expand the serial image data DOUT obtained from the above into a memory or the like and perform image processing by an external computer. In the visual information processing chip and the network-type solid-state imaging device, it is difficult to form the device, and therefore, only several tens to several hundreds of pixels are realized.

The present invention was created in view of the problems of the conventional example. A transistor for outputting electric charges in the row / column direction is arranged for each pixel, and the addition function is provided for each row / column. Accordingly, it is an object of the present invention to provide a solid-state imaging device that can project two-dimensional image information as independent one-dimensional information in the row and column directions and easily increase the number of images.

[0010]

FIGS. 1 and 2 show the principle diagrams (Nos. 1 and 2) of a solid-state image pickup device according to the present invention. As shown in FIG. 1, the first solid-state image pickup device of the present invention uses a row read line Lv based on a row selection signal φVi.
And the column read line Lh based on the column selection signal φHi.
In addition, a photoelectric conversion element 11 that outputs charges, a first charge addition element 12 that adds the charges of the row read line Lv based on a row reset signal φRV, and a column read line based on a column reset signal φRH And a second charge addition element 13 for adding the charge of Lh.

The second solid-state image pickup device of the present invention is provided with a switching element Sv for controlling the output of the first charge addition element 12 based on the row selection signal φVi, and based on the column selection signal φHi. A switching element Sh for controlling the output of the second charge addition element 13 is provided respectively. In the first and second solid-state image pickup devices of the present invention, the photoelectric conversion element 11 outputs the charge to the row read line Lv based on a diode Di that generates a charge by receiving light and a column selection signal φHi. Transistor T1 and a second transistor T2 which outputs the electric charge to the column read line Lh based on the row selection signal φVi.

In the first and second solid-state image pickup devices of the present invention, the first charge addition device 12 is based on an amplifier device Av for converting the charges of the row read line Lv into a voltage and a row reset signal φRV. And a transistor Tv for resetting the row read line Lv, the second charge addition element 13 is based on a row reset signal φRH and an amplifier element Ah for converting the charge on the row read line Lh into a voltage. A transistor Th for resetting the row read line Lh.

In the first and second solid-state image pickup devices of the present invention, the row reset signal φRV and the column reset signal φ
The RV is variable at a timing according to the addition mode or the imaging mode. First and second aspects of the present invention
In the solid-state image sensor of, the amplification elements Av and Ah are
It is characterized by comprising a source follower amplifier circuit having a field effect transistor and a load element.

In the first and second solid-state image pickup devices of the present invention, the load device is commonly used for a plurality of source follower amplifier circuits, and the above object is achieved.

[0015]

[Operation] The operation of the first solid-state imaging device of the present invention will be described. For example, when light is received, charges are generated by a diode Di as shown in FIG. 2A. In this state, when the row selection signal φVi and the column selection signal φHi are supplied to the photoelectric conversion element 11, these signals φVi and φHi are supplied. Based on the above, electric charges are output to the row read line Lv and the column read line Lh.

That is, when the column selection signal φHi = “H” level, the first transistor T1 is turned on, and the charge is output to the row read line Lv. In addition, the row selection signal φVi =
At the “H” level, the second transistor T2 is turned on, and the charges are output to the column read line Lh. Further, in the first charge addition element 12, for example, the row reset signal φ
When RV = “L” level is supplied to the transistor Tv, the row read line Lv is reset, and the charge of the row read line Lv is added by the amplifier element Av as shown in FIG. Is converted to.

Similarly, in the second charge addition element 13, for example, when the column reset signal φRH = “L” level is supplied to the transistor Th, the column read line Lh is reset, and the amplifier element Ah resets the column read line. The charge of Lh is converted into a voltage. Therefore, the charges detected by the diode Di are read out in the column direction and the row direction,
Also, at the input points of the charge addition elements 12 and 13, it becomes possible to add the charges for each column unit and for each row unit.

As a result, the two-dimensional image information obtained by the photoelectric conversion element 11 can be projected as the one-dimensional information x, y in the row direction (vertical direction) and the column direction (horizontal direction). The operation of the second solid-state image sensor of the present invention will be described. For example, when the row selection signal φVi = “H” level and the switching element Sv is turned on, the output voltage of the first charge addition element 12 is added to the output voltage of the other charge addition element 12. Similarly, the column selection signal φHi =
When the switching element Sh is turned on at the “H” level, the output voltage of the second charge addition element 13 is added to the output voltage of the other charge addition element 13.

Therefore, it is possible to independently add the one-dimensional information x and y projected in row and column units in the row and column directions. This makes it possible to execute the addition mode in which the column reset signal φRH is raised to the “H” level every time one frame is scanned. This makes it possible to configure a solid-state image sensor having a function of detecting an edge of an object to be imaged. Further, it becomes possible to configure a solid-state image pickup device having several thousand to several hundreds of thousands of pixels as compared with a visual information processing chip or a network-type solid-state image pickup device as in a conventional example, and the element is used as a pattern inspection device or the like. Can be applied to.

According to the first and second solid-state image pickup devices of the present invention, the amplifying devices Av and Ah which are the source follower amplifier circuits are provided, and, for example, the load element is common to a plurality of source follower amplifier circuits. Then used. Therefore, when the switching element Sv or Sh is in the OFF operation, the load element is disconnected from the amplifying elements Av and Ah.

As a result, the switching element Sv or S
Power is supplied only to the amplifiers Av and Ah where h is ON.
A current can be passed between the ground line Vcc and GND, and the power consumption of the device can be reduced.

[0022]

Embodiments of the present invention will now be described with reference to the drawings. 3 to 7 are explanatory views of the solid-state image sensor according to the embodiment of the present invention. (1) Description of First Embodiment FIG. 3 shows a solid-state image sensor (2) according to a first embodiment of the present invention.
4 is a configuration diagram of (2), and FIG. 4 is an explanatory diagram of an amplifier and a load element according to each example of the present invention.

For example, in the XY address system, x
The solid-state image sensor (2 × 2) that outputs the projected image data XOUT and the y projected image data YOUT is, as shown in FIG.
Four photoelectric conversion cells 21A to 21D, two row reset amplifier circuits 22A and 22B, two column reset amplifier circuits 23A,
23B, two row selection circuits Sv1, Sv2, two column selection circuits Sh1, Sh2, a vertical shift register 24, a horizontal shift register 25, and two resistors Rx, Ry.

Each of the photoelectric conversion cells 21A to 21D is an example of the photoelectric conversion element 11 and constitutes an image area. For example, the photoelectric conversion cell 21A has a photodiode D11, a vertical read transistor MV11, and a horizontal read transistor MH11. The diode D11 is an example of the diode Di, and generates charges by receiving light. The transistor MV11 is an example of the first transistor T1 and outputs charges to the row read line Lv1 based on the column selection signal φH1. The transistor MH11 is an example of the second transistor T2, and outputs the charge to the column read line Lh1 based on the row selection signal φV1.

Similarly, the photoelectric conversion cell 21B has a photodiode D12, a vertical read transistor MV12 and a horizontal read transistor MH12. Transistor MV
Reference numeral 12 is a row read line Lv for supplying electric charges based on the column selection signal φH2.
Output to 1. The transistor MH12 is a row selection signal φV1.
The electric charge is output to the column read line Lh2 based on The photoelectric conversion cell 21C has a photodiode D21, a vertical read transistor MV21, and a horizontal read transistor MH21. The transistor MV21 outputs charges to the row read line Lv1 based on the column selection signal φH1. The transistor MH21 outputs charges to the column read line Lh1 based on the row selection signal φV2.

The photoelectric conversion cell 21D is a photodiode D2.
2. It has a vertical read transistor MV22 and a horizontal read transistor MH22. The transistor MV22 outputs charges to the row read line Lv2 based on the column selection signal φH2. The transistor MH22 outputs charges to the column read line Lh2 based on the row selection signal φV2. This allows
Row selection signals φV1 and φV2 and column selection signals φH1 and φH
2 from the image area to the row read lines Lv1 and L
It is possible to output electric charges to v2 and the column read lines Lh1 and Lh2, respectively.

Each row reset amplifier circuit 22A and 22B is an example of the first charge addition element 12. The amplifier circuit 22A has a source follower amplifier Av1 and a reset transistor Tv1, and adds the charges of the row read line Lv1 based on the row reset signal φRV. Source follower amplifier A
v1 is an example of the amplifying element Av of FIG. 2B, and converts the charge of the row read line Lv1 into a voltage. Transistor T
v1 is an example of the transistor Tv in FIG. 2B, which resets the row read line Lv1 based on the row reset signal φRV.

Similarly, the amplifier circuit 22B has a source follower amplifier Av2 and a reset transistor Tv2,
The charges of the row read line Lv2 are added based on the row reset signal φRV. Source follower amplifiers Av1 and Av2
Generally has a field effect transistor T and a load element Ro, as shown in FIG. In FIG. 4A, the drain of the transistor T is connected to the power supply line Vcc, the source thereof is connected to one end of the load element Ro, and the other end of the element Ro is connected to the ground line GND.

However, in the embodiment of the present invention, in order to reduce the power consumption, one resistor Ry is provided for two source follower amplifiers Av1 and Av2 as shown in FIG. 4B.
Commonly used. The row selection circuit Sv1 is connected to the source of the amplifier Av1 and one end of the resistor Ry, and the row selection circuit Sv2 is connected to the source of the amplifier Av2 and one end of the resistor Ry. The other end of the resistor Ry is connected to the ground line GND, and the drains of the amplifiers Av1 and Av2 are connected to the power supply line VCC.

Each column reset amplifier circuit 23A and 23B is an example of the first charge addition element 13. The amplifier circuit 23A has a source follower amplifier Ah1 and a reset transistor Th1, and adds the charges of the column read line Lh1 based on the column reset signal φRH. Source follower amplifier A
h1 is an example of the amplifying element Av of FIG. 2B, and converts the charge of the column read line Lh1 into a voltage.

The transistor Th1 is an example of the transistor Tv in FIG. 2B and resets the column read line Lh1 based on the column reset signal φRH. Similarly, the amplifier circuit 23B has a source follower amplifier Ah2 and a reset transistor Th2, and adds the charges of the column read line Lh2 based on the column reset signal φRH. The source follower amplifiers Ah1 and Ah2 and the resistor Rx are connected to the amplifier Av.
The configuration as shown in FIG. 4B is adopted in the same manner as 1, 1, Av2 and the resistor Ry.

The row selection circuit Sv1 uses the row selection signal φV.
The output of the amplifier Av1 is controlled based on 1 and the row selection circuit Sv2 controls the output of the amplifier Av2 based on the row selection signal φV2. The column selection circuit Sh1 controls the output of the amplifier Ah1 based on the column selection signal φH1, and the column selection circuit Sh1
Reference numeral 2 controls the output of the amplifier Ah2 based on the column selection signal φH2.

The vertical shift register 24 has a row selection signal φV.
1 is output to the transistors MH11 and MH12, and the row selection signal φV2 is output to the transistors MH21 and MH22, respectively. The horizontal shift register 25 outputs a column selection signal φH1 to the transistors MV11 and MV12, and the column selection signal φ
H2 is output to the transistors MV21 and MV22, respectively.

Next, the operation of the solid-state image pickup device according to the first embodiment of the present invention will be described. FIG. 5 is an operation waveform diagram of the solid-state image pickup device according to the first embodiment of the present invention, and FIG. 6 is an explanatory diagram of an image pickup mode and an addition mode according to each embodiment of the present invention. For example, when light is received, charges are generated by the four diodes D11 to D22 as shown in FIG. 3, and in this state, the row selection signals φV1 and φV2 and the column selection signals φH1 and φH2 are supplied to the photoelectric conversion cells 21A to 21D. Then, these signals φV1, φV2 and φH1, φ
Based on H2, charges are output to the row read lines Lv1 and Lv2 and the column read lines Lh1 and Lh2, respectively.

Now, the operation in the addition mode will be described. The addition mode is a mode in which the number of lines to which the one-dimensional information x on a column basis is added is specified, and specifically, it is executed by changing the timing of the column reset signal φRH. In the embodiment of the present invention, every time one frame is scanned,
Raise φRH to “H” level. For example, as shown in the operation waveform diagram of FIG. 5, the column reset signal φRH is “L”.
Level, the row reset signal φRV is at the “L” level,
Row selection signal φV1 is at “H” level, φV2 is at “L” level, column selection signal φH1 is at “H” level, and φH2 is at “L” level. In this case, the transistor MV11,
Both MV21, MH11 and MH12 are turned on, and the transistors MV12, MV22, MH21 and MH22 are all turned off.

As a result, the charges generated by the diode D11 are read out in the row and column directions. For example, the charge of the diode D11 is output from the column read line Lh1 to the amplifier Ah1, which is converted into a voltage by the amplifier Ah1, and the output voltage based on the charge of D11 passes through the column selection circuit Sh1 and becomes x-projected image data XOUT. . At the same time, the charge of the diode D11 is transferred from the row read line Lv1 to the amplifier Av1.
The output voltage based on the electric charge of D11 passes through the row selection circuit Sv1 and becomes y-projection image data YOUT.

Further, the row selection signal φV1 is at "H" level,
When the column selection signal φH1 goes to the “L” level and φH2 goes to the “H” level while φV2 remains at the “L” level, the transistors MH11 and MH12 continue the ON operation, and the transistors MH21 and MH22 continue the OFF operation. , The transistors MV12 and MV22 are turned on, and the transistors MV11 and MV21 are both turned off.

As a result, the charges generated by the diode D12 are read out in the row and column directions. For example, the charge of the diode D12 is output from the column read line Lh2 to the amplifier Ah2, which is converted into a voltage by the amplifier Ah2, and the output voltage based on the charge of D12 passes through the column selection circuit Sh2 and becomes x-projected image data XOUT. . At the same time, the charge of the diode D12 is transferred from the row read line Lv2 to the amplifier Av2.
Is output to the row selection circuit S and the output voltage based on the charge of D11 + D12 is converted into a voltage by the amplifier Av2.
After passing v2, it becomes y projected image data YOUT.

Further, as shown in FIG. 5, the row reset signal φRV is maintained while the column reset signal φRH remains at the “L” level.
Becomes the "H" level, the row selection signal φV1 is at the "L" level, φV2 is at the "H" level, the column selection signal φH1 is at the "H" level, and φH2 is at the "L" level. In this case, the transistors MV11, MV21, MH21 and MH22
Both turn on and transistors MV12, MV22, MH
Both 11 and MH12 operate OFF.

As a result, the charges generated by the diode D21 are read out in the row and column directions. For example, the charge of the diode D21 is output from the column read line Lh1 to the amplifier Ah1, which is converted into a voltage by the amplifier Ah1, and the output voltage based on the charge of D11 + D21 is output to the column selection circuit S.
It passes through h1 and becomes x-projected image data XOUT. At the same time, the charge of the diode D21 is output from the row read line Lv1 to the amplifier Av1, which is converted into a voltage by the amplifier Av1, and the output voltage based on the charge of D21 passes through the row selection circuit Sv1 to become y projection image data YOUT. .

Further, the row selection signal φV1 is at the "L" level,
When the column selection signal φH1 is set to the “L” level and φH2 is set to the “H” level while φV2 remains at the “H” level, the transistors MH21 and MH22 continue the ON operation, and the transistors MH11 and MH12 continue the OFF operation. , The transistors MV12 and MV22 are turned on, and the transistors MV11 and MV21 are both turned off.

As a result, the charges generated by the diode D22 are read out in the row and column directions. For example, the charge of the diode D22 is output from the column read line Lh2 to the amplifier Ah2, which is converted into a voltage by the amplifier Ah2, and the output voltage based on the charge of D21 + D22 is output to the column selection circuit S.
It passes through h2 and becomes x-projected image data XOUT. At the same time, the charge of the diode D22 is output from the row read line Lv2 to the amplifier Av2, which is converted into a voltage by the amplifier Av2, and the output voltage based on the charge of D21 + D22 passes through the row selection circuit Sv2 and becomes y projection image data YOUT. .

As a result, it becomes possible to detect the edge of the object to be imaged as shown in FIG. 6 (B). Note that the imaging mode as shown in FIG. 6A can be executed as in the conventional example. In this way, according to the solid-state image sensor according to the first embodiment of the present invention, as shown in FIG.
Photoelectric conversion cells 21A to 21D, row reset amplifier circuit 22A,
22B, column reset amplifier circuits 23A and 23B, row selection circuit S
v1 and Sv2 and column selection circuits Sh1 and Sh2 are provided.

Therefore, the charges detected by the four diodes D11 to D22 are read out in the column direction and the row direction, respectively, and the amplifier circuits 22A, 22B, 23A and 23 are read out.
At the input point of B, it becomes possible to add these charges column by column and row by row. As a result,
As described above, the two-dimensional image information obtained by the photoelectric conversion cells 21A to 21D can be projected as the one-dimensional information x and y in the row direction (vertical direction) and the column direction (horizontal direction).

That is, the charges in the column direction are read out during the period in which the horizontal reset transistors Th1 and Th2 are in the OFF operation to add the charges in the Y (column) direction for each pixel (D11 + D12 + D21 + D22) x projection. Image data XOU
We get T. Similarly, by reading out charges in the row direction while the vertical reset transistors Tv1 and Tv2 are in the OFF operation, the y projection in which the charges in the X (row) direction are added every other pixel (D11 + D12, D21 + D22). Image data Y
OUT is obtained.

Therefore, both image data XOUT after this addition
, YOUT can be sample-held and read into the external image processing circuit. At the time of this sample hold, it is necessary to devise the sample timing for the y projection image data YOUT. In addition, according to the first embodiment of the present invention, the two source follower amplifiers Av1 and Av2 are
, The resistor Ry is commonly used, and the resistor Rx is commonly used for the source follower amplifiers Ah1 and Ah2.

Therefore, when any of the row selection circuits Sv1 and Sv2 or the column selection circuits Sh1 and Sh2 performs the OFF operation, the resistor Ry is disconnected from the amplifier Av1 or Av2 and the resistor Rx is disconnected from the amplifier Ah1 or Ah2. Be done. As a result, the circuits Sv1, Sv2 or Sh1, Sh
Amplifier Av1 or Av only when 2 is ON
2, a current flows through Ah1 or Ah2. As a result, the power consumption of the solid-state image sensor can be reduced. Further, it becomes possible to execute data processing such as contour extraction, which has been performed by an external image processing device or the like, inside the solid-state image sensor.

As a result, it is possible to construct a solid-state image pickup device internally having an edge detection function (preprocessing function) of the object to be imaged. Further, it becomes possible to configure a solid-state image pickup device having several thousand to several hundreds of thousands of pixels as compared with a visual information processing chip or a network-type solid-state image pickup device as in the conventional example, and the element is used for a pattern inspection device or the like. Its performance is expected to improve by applying to.

(2) Description of Second Embodiment FIG. 7A is a block diagram of a solid-state image sensor (one-dimensional) according to a second embodiment of the present invention, and FIG. The block diagram which concerns on the application example is each shown. Unlike the first embodiment, the second embodiment forms a line CCD sensor (one-dimensional solid-state image sensor).

For example, as shown in FIG. 7A, the line CCD sensor 100 for outputting the projected image data DOUT has n
Photoelectric conversion cells 31A, 31B to 31n, shift register 3
2, reset amplifier circuits 33A, 33B to 33n, pixel selection circuits S1, S2 to Sn, and one resistor Ro. Each photoelectric conversion cell 31A, 31B to 31n constitutes an image line. For example, the photoelectric conversion cell 31A is a photodiode D
1, having a read transistor MH1. The transistor MH1 outputs charges to the read line L1 based on the pixel selection signal φH1.

Similarly, the photoelectric conversion cell 31B has a photodiode D2 and a read transistor MH2. The transistor MH2 outputs charges to the read line L2 based on the pixel selection signal φH2. The nth photoelectric conversion cell 31n also has a photodiode and a read transistor. Each reset amplifier circuit 33A has a source follower amplifier A1 and a reset transistor T1 and has a reset signal φR.
The charge of the read line L1 is added based on The source follower amplifier A1 converts the charge of the read line L1 into a voltage. The transistor T1 resets the read line L1 based on the reset signal φR.

Similarly, the amplifier circuit 33B has a source follower amplifier A2 and a reset transistor T2, and adds the charges of the read line L2 based on the reset signal φR. The n-th reset amplifier circuit 33n also has a source follower amplifier and a reset transistor, and adds the charges of the read line Ln based on the reset signal φR. In addition,
The pixel selection circuit S1 controls the output of the amplifier A1 based on the pixel selection signal φH1, and the pixel selection circuit S2 controls the output of the amplifier A2 based on the pixel selection signal φH2. The nth pixel selection circuit Sn controls the output of the amplifier A based on the pixel selection signal φHn.

The shift register 32 has a pixel selection signal φH1.
To the transistors MH1 and S1, the signal φH2 to the transistors MH2 and T2, and the signal φHn to n.
It is output to the th photoelectric conversion cell 31n and the pixel selection circuit Sn. As a result, charges can be output to the read lines L1 to Ln based on the pixel selection signals φH1 to φHn. Other configurations and those having the same names as those in the first embodiment have the same functions, and therefore their explanations are omitted.

In this way, according to the line CCD sensor 100 of the second embodiment of the present invention, as shown in FIG. 7A, n photoelectric conversion cells 31A, 31B to 31n, shift registers are provided. 32, reset amplifier circuit 33A, 33B to 33
n, pixel selection circuits S1, S2 to Sn, and one resistor Ro
Equipped with. Therefore, as shown in FIG. 7B, a simple image acquisition device can be configured by the line CCD sensor 100, the reflecting mirror 102, the polygon mirror 102, and the like. For example, the object to be imaged is received via the reflecting mirror 102, and the polygon mirror 102 causes a line C to be received.
When scanning is performed on the CD sensor 100, charges are sequentially generated by the n photoelectric conversion cells 31A, 31B to 31n. In this state, the pixel selection signals φH1, φH2 ...
When supplied to 31A, 31B to 31n, these signals φH1,
Based on φH2 ..., Transistors MH1 and MH2 are sequentially
Are turned on, and charges are output to the read lines L1 to Ln, respectively.

As a result, the charges generated by the diodes D1, D2 ... Are added for each horizontal line and become the projected image data DOUT. This makes it possible to configure a simple pattern inspection device or the like to which the column-direction reading function of the first embodiment is applied.

[0056]

As described above, according to the solid-state image pickup device of the present invention, the photoelectric conversion device and the first and second charge addition devices are provided, and the charge of the row read line is determined based on the row reset signal. 1 is added by the charge addition element, and the charges of the column read line are added by the second charge addition element based on the column reset signal.

Therefore, the charges detected by the respective diodes of the photoelectric conversion element are read out in the column direction and the row direction, respectively, and at the input point of each charge addition element, the charges are column-wise and row-wise. It is possible to add each. Further, according to another solid-state imaging device of the present invention, a switching element is provided at the output of each charge addition element.

Therefore, the one-dimensional information projected on a row / column basis can be added independently in the row / column direction, and the two-dimensional image information obtained by the photoelectric conversion element can be added in the row direction (vertical direction). ) And the column direction (horizontal direction) can be projected as one-dimensional information. As a result, it is possible to configure a low power consumption type solid-state imaging device having an edge detection function of an object to be imaged and to increase the number of captured images as compared with the conventional example. This greatly contributes to the provision of a high-performance and high-speed image processing pattern inspection apparatus to which the solid-state imaging device is applied.

[Brief description of drawings]

FIG. 1 is a principle diagram (1) of a solid-state image sensor according to the present invention.
Is.

FIG. 2 is a principle diagram of a solid-state image sensor according to the present invention (Part 2).
Is.

FIG. 3 is a solid-state image sensor (2) according to the first embodiment of the present invention.
It is a block diagram of x2).

FIG. 4 is an explanatory diagram of an amplifier and a load element according to each embodiment of the present invention.

FIG. 5 is an operation waveform diagram of the solid-state imaging device according to the first embodiment of the present invention.

FIG. 6 is an explanatory diagram of an imaging mode and an addition mode according to each embodiment of the present invention.

FIG. 7 is a configuration diagram of a solid-state imaging device (one-dimensional) according to a second embodiment of the present invention.

FIG. 8 is a configuration diagram of a solid-state image sensor (2 × 2) according to a conventional example.

FIG. 9 is an operation waveform diagram of a solid-state image sensor according to a conventional example.

[Explanation of symbols]

 11 ... Photoelectric conversion element, 12 ... 1st charge addition element, 13 ... 2nd charge addition element, T1, T2 ... 1st, 2nd transistor, Di ... Diode, Sv, Sh ... Switching element, Av ... Amplification Element, Tv ... Transistor, .phi.Vi ... Row selection signal, .phi.Hi ... Column selection signal, .phi.RV ... Row reset signal, .phi.RH ... Column reset signal, Lv ... Row read line, Lh ... Column read line, x, y ... One-dimensional information.

Claims (7)

[Claims] 1. A photoelectric conversion element which outputs electric charges to a row read line (Lv) based on a row selection signal (φVi) and to a column read line (Lh) based on a column selection signal (φHi), respectively. 11) and a first charge addition element (12) for adding the charges of the row read line (Lv) based on the row reset signal (φRV).
And a second charge addition element (13) for adding the charges of the column read line (Lh) based on the column reset signal (φRH)
And a solid-state image sensor. 2. A switching element (Sv) for controlling the output of the first charge addition element (12) based on a row selection signal (φVi), and the second element based on a column selection signal (φHi). Switching element (Sh) for controlling the output of the charge addition element (13) of
The solid-state image pickup device according to claim 1, wherein the solid-state image pickup device is provided respectively. 3. The photoelectric conversion element (11) outputs a charge to a row read line (Lv) based on a diode (Di) that generates a charge by receiving light and a column selection signal (φHi). Solid state according to claim 1 or 2, characterized in that it comprises a transistor (T1) and a second transistor (T2) for outputting the charges to a column read line (Lh) based on a row selection signal (φVi). Image sensor. 4. The first charge addition element (12) reads out the row based on an amplification element (Av) that converts the charge of the row read line (Lv) into a voltage and a row reset signal (φRV). Transistor (T that resets line (Lv)
v), the second charge addition element (13) includes an amplification element (Ah) that converts the charges of the row read line (Lh) into a voltage,
3. The solid-state imaging device according to claim 1, further comprising a transistor (Th) that resets the row read line (Lh) based on a row reset signal (φRH). 5. The solid-state imaging device according to claim 1, wherein the row reset signal (φRV) and the column reset signal (φRV) are variable at timings according to the addition mode or the imaging mode. 6. The solid-state imaging device according to claim 4, wherein the amplification device (Av, Ah) is formed of a source follower amplifier circuit having a field effect transistor and a load device. 7. The solid-state image sensor according to claim 6, wherein the load element is commonly used for a plurality of source follower amplifier circuits.