JPH07336014A - Mounting structure of ic package - Google Patents

Abstract

PURPOSE:To improve the efficiency of mounting, by a method wherein a plurality of stacked IC packages of which terminals are joined mutually are mounted on a base. CONSTITUTION:Memory IC packages 2 in a plurality of sets each comprising two memory IC packages 2 of which terminals 3a belonging to a terminal group 3 are joined directly are mounted on a base. The memory IC packages 2 in each set are joined to the base by joining terminals 3b not beloning to the terminal group 3 to a pattern on the base. Besides, the terminals 3a of the memory IC packages 2 in each set are connected to each other directly without using the pattern on the base as intermediary, and moreover, the terminals 3a of the terminal group 3 disposed at the final end are connected to a power source, the ground, an address bus and a data bus on the base 1 respectively. Accordingly, memory chips in the memory IC packages 2 in a plurality of sets are joined parallel to each of bus lines and power lines and thus it is made possible to drive and access an arbitrary memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC package mounting structure and a memory IC package mounting structure.

[0002]

2. Description of the Related Art Conventionally, an IC package is formed by projecting a plurality of leads from a package enclosing an IC chip. Each lead is arranged according to a predetermined pin code, and is configured to perform a predetermined operation by applying a predetermined signal current or voltage to each pin code.

The IC packages are connected to each other through a pattern formed on the substrate to form a module or the like as a whole.

[0004]

However, in the above-mentioned conventional example, since the connections between the IC packages are all made through the patterns on the substrate, when the circuit scale becomes large, the patterns are This has a drawback that the occupied area is expanded and the mounting efficiency is reduced.

The present invention has been made to solve the above drawbacks, and can improve the mounting efficiency.
It is intended to provide a mounting structure of a C package.

[0006]

According to the present invention, as described above, the above object is to provide a plurality of ICs in which terminals connected in parallel to a bus line on a substrate 1 are bonded and laminated to each other.
This is achieved by providing an IC package mounting structure for mounting the package 2 on the substrate 1.

[0007]

In the present invention, a plurality of IC packages 2
Are mounted on the substrate 1 in a state where terminals connected in parallel to the bus line on the substrate 1 are connected to each other and stacked.

As a result, at least the target terminals of the IC package 2 stacked in the vertical direction are connected to the bus lines in parallel with each other, and the pattern occupying area on the substrate 1 can be reduced.

The IC package 2 according to the second aspect of the invention is connected in parallel to the bus line on the substrate 1,
It includes a plurality of sets of terminal groups 3 having the same pin code, and the pin code arrangement of each terminal group 3 is the package body 4
Are arranged symmetrically with respect to the center line of.

As a result, the above-mentioned mounting structure can be easily obtained by simply joining the two IC packages 2 with the tips of the terminals facing each other. Further, in the invention according to claim 3, an internal structure of the IC package 2 is provided. That is, in the package body 4,
A plurality of chips 5 corresponding to the terminal group 3 are sealed,
The chips 5 are connected to the terminal group 3.

In a fourth aspect of the invention, the common lines of the pattern formed on the chip 5 are package main bodies 4
To be joined within. As a result, the chips 5 in the plurality of vertically stacked IC packages 2 are connected in parallel to each other with respect to the bus line, and the packaging density is further improved.

According to the fifth aspect of the present invention, the terminal groups 3 of the IC package 2 are arranged along both side edges of the package body 4, and the terminal groups 3 of the adjacent IC packages 2 are directly connected to each other.

As a result, a plurality of vertically mounted ICs are mounted.
The chips 5 in the package 2 are connected to the bus lines in parallel with each other, and the pattern on the substrate 1 for these connections is not required.

In the invention according to claims 6 to 10, application to the memory IC package 2 is provided. That is, in the invention according to claim 6, at least data input / output terminals or address terminals having the same pin code are bonded and laminated to each other, and these data input / output terminals or address terminals are connected to the data bus line on the substrate 1. , Or to the address bus line, the area occupied by the data bus or address bus on the substrate 1 is reduced.

According to the ninth aspect of the invention, common lines such as data lines on the memory chip 5 sealed in the package body 4 are joined in the package body 4 to connect the memory cells.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. First, FIGS. 2 and 3 show an IC package 2 used in the present invention. The illustrated IC package 2 is configured as a memory IC, and includes a plurality of TSOP-type terminals 3a, 3a ... 3b, 3b, ... Arranged along opposite edges of the package body 4.

Each terminal has a power supply (Vcc), a ground (GND), a row address strobe (RAS), a column address strobe (CAS), a write enable (WE), an output enable (OE), and an address (A1, A2). ...) and other pin codes are sorted.

The memory IC package 2 includes a memory IC
All the necessary terminals are prepared in two sets on both side edges of the package body 4. Among the terminals of each set, Vcc, GN
A terminal group 3 is composed of D, address, and data input / output terminals.

At least the terminals 3a, 3a, ... belonging to the terminal group 3 are arranged on the side edges of the package body 4 so as to face each other, and the pin code arrangement in each terminal group 3 is the package body 4 Are centered around each other.

Further, the terminals 3a, 3 belonging to the terminal group 3 are
are bent in the same direction, and as shown by the chain line in FIG. 3, by stacking the two memory IC packages 2 with the ends of the terminals 3a, 3a .. It is possible to directly join terminals having the same pin code.

On the other hand, the terminals 3b, 3b not belonging to the terminal group 3
As will be described later, those located above are shown in FIG.
As shown in FIG. 2 (b), those located in the same direction as the terminal terminals 3a belonging to the terminal group 3 and longer than these terminals 3a, and located below the terminals 3a, as shown in FIG. 2 (c).
Are bent in the opposite direction to the bending direction of the terminals 3a belonging to the above, and each of them can be joined to the pattern on the substrate 1.

Two memory chips 5 and 5 are enclosed in the package body 4 as shown in FIG. The memory chips 5 are arranged vertically in two stages with the memory cell forming surfaces 5a facing each other, and the I / O of one memory chip 5 is arranged.
The pads 5b, 5b, ... Are arranged on one side edge of the package body 4 and the I / O pads 5b ', 5b', .. of the other memory chip 5 are arranged on the opposite side edges of the package body 4. Connected to each terminal. In FIG. 3B, reference numeral 6 denotes an inner lead that connects the terminals 3a and 3b to the memory chip 5.

Bonding bumps 7 are provided between the memory chips 5 to prevent short circuit between the memory cell forming surfaces 5a and to connect internal common wirings for connecting a plurality of memory cells in parallel. ing.

The mounting structure of the memory IC package formed as described above is shown in FIG. Memory IC package 2
Is mounted on the substrate 1 with two memory IC packages 2 and 2 in which the terminals 3a belonging to the terminal group 3 are directly joined as one set. Each set of memory IC package 2
Is bonded to the substrate 1 in each memory IC package 2.
This is performed by joining the terminals 3b that do not belong to the terminal group 3 to the pattern on the substrate 1.

Further, the terminal groups 3 of the memory IC packages 2 of each set mounted on the substrate 1 as described above are directly connected to each other without interposing the pattern on the substrate 1, and further arranged at the final end. The terminal 3a of the terminal group 3 is connected to the power supply, the ground, the address bus, and the data bus on the substrate 1, respectively, as shown at the left end in FIG.

Therefore, in this embodiment, the terminal group 3
The memory chips 5 in the plurality of sets of memory IC packages 2 connected to each other are connected in parallel to each bus line and the power supply line, without passing through the pattern on the substrate 1, It is possible to drive and access any memory cell.

In the above description, the case where a plurality of sets of memory IC packages 2 stacked vertically are connected to each other has been shown. However, each set is individually mounted on the substrate 1 without being connected to each other. Even in this case, it is possible to reduce the area occupied by the pattern on the substrate 1.

Further, the shape of the terminals provided in the memory IC package 2 is not limited to the TSOP type, but the terminals of the terminal group 3 can be formed in the bump type as shown in FIG. 4, for example.

Furthermore, the present invention can be applied not only to the memory IC package 2 but also to all IC packages 2 including terminals connected in parallel to the bus line on the substrate 1.

[0030]

As is apparent from the above description, according to the present invention, a plurality of elements can be connected in parallel to a bus line without using a pattern on a substrate, so that the pattern occupied area Can be reduced and the mounting efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

2A and 2B are views showing the outer appearance of an IC package used in the present invention, FIG. 2A being a plan view and FIG. 2B being a front view.

FIG. 3 is a diagram showing an internal structure of an IC package.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

 1 substrate 2 IC package 3 terminal group 4 package body 5 chips

Claims (10)

[Claims] 1. An IC package mounting method for mounting on a substrate (1) a plurality of IC packages (2, 2) in which terminals connected in parallel to a bus line on the substrate (1) are bonded to each other and laminated. Construction. 2. The IC package (2) is a substrate (1).
A plurality of sets of terminal groups (3, 3) having the same pin code and connected in parallel to the upper bus line are included, and the pin code array of each terminal group (3) is aligned with the center line of the package body (4). The IC package mounting structure according to claim 1, wherein the IC package mounting structures are arranged symmetrically with respect to each other. 3. The mounting structure for an IC package according to claim 3, wherein a plurality of chips (5, 5) corresponding to the terminal group (3) are formed by being sealed in a package body (4). 4. The mounting structure for an IC package according to claim 3, wherein common lines of patterns formed on the chip (5) are joined together in the package body (4). 5. A terminal group (3) of the IC package (2).
Are arranged along both side edges of the package body (4), and the terminal groups (3, 3) of the adjacent IC packages (2, 2)
The IC package mounting structure according to claim 4, wherein the IC packages are directly connected to each other. 6. A plurality of memory IC packages (2, 2) in which at least data input / output terminals or address terminals having the same pin code are joined and laminated, are mounted on a substrate (1), and the data input terminal is provided. A mounting structure of a memory IC package in which an output terminal or an address terminal is connected to a data bus line or an address bus line on a substrate (1). 7. The memory IC package (2) has at least two sets of address terminal groups (3, 3) or data input / output terminal groups (3, 3) having the same pin code arrangement.
7. The mounting structure of the memory IC package according to claim 6, wherein the pin code array of each terminal group (3) is arranged symmetrically with respect to the center line of the package body (4). 8. A terminal group formed by sealing two memory chips (5, 5) in a package body (4) and corresponding to address terminals or data input / output terminals of each memory chip (5). The memory IC according to claim 7, which is connected to (3).
Package mounting structure. 9. The mounting structure of a memory IC package according to claim 8, wherein common lines on the memory chip (5) are joined together in the package body (4). 10. The terminal group (3) of the memory IC package (2) is arranged along both side edges of the package body (4), and the terminal groups (3) of the adjacent memory IC packages (2) are adjacent to each other. The mounting structure of an IC package according to claim 9, which is directly connected.