JPH07335735A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide the manufacture of a semiconductor device, in which the lowering of isolation breakdown strength due to a constriction formed between a buried oxide film and a sidewall oxide film is prevented and elements having high breakdown strength are isolated. CONSTITUTION:A silicon support substrate 1 and a silicon substrate 2 are joined through a buried oxide film 3, and an oxide film 4 as a mask is formed onto the surface of the silicon substrate 2. The silicon substrate 2, the buried oxide film 3 and the silicon support substrate 1 are etched by using the mask. The surfaces of the sidewalls of the silicon substrate 2 in an isolation groove 5 and the surface of the silicon support substrate 1 are oxidized through a thermal oxidation method, and oxide films 8 brought into contact with the buried oxide film 3 are formed onto the inwall sections of the isolation groove 5. Lastly, polycrystalline silicon 11 is buried into the isolation groove 5, and flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device having element isolation, and more particularly to element isolation having a high breakdown voltage.

[0002]

2. Description of the Related Art As a method for insulating and isolating elements of a semiconductor integrated circuit, as shown in FIG.
01 and a second semiconductor substrate 102, an SOI (Silicon O
n Insulator) structure substrate, and the second semiconductor substrate 10
A trench (separation groove) extending from the main surface of No. 2 to the buried oxide film 102 is formed, and thereafter, the inner wall of the trench is covered with an oxide film 104 by a thermal oxidation method or the like, and the inside thereof is filled with a buried member 105. There have been various proposals for flattening the surface. Polycrystalline silicon is often used as the embedding member 105 in consideration of the coefficient of thermal expansion with the silicon substrate, but silicon oxide by CVD or the like can also be used.

According to this method, reverse-biased PN is used.
As compared with the method of separating the elements by using the junction, it is possible to perform reliable separation with no leak current, with no dependence on voltage polarity, and with high breakdown voltage. However, the first problem of this method is that when the inside of the trench is oxidized, a constriction (edge portion) indicated by a circle in FIG. The process of causing this necking can be explained as follows.
That is, in the oxidation of the trench bottom corner, an oxide film that grows from the trench side wall in a direction perpendicular to the wall,
Since the oxide film growing upward from the bottom surface of the trench meets at the corner portion, the growth of the other oxide films is hindered from each other at that position, and the volume expansion cannot be performed, resulting in the constriction. Since the tip of the constriction has a sharp edge shape, electric field concentration occurs and the breakdown voltage is lowered, which is a problem.

A second problem is that stress concentration occurs in the trench bottom corner as oxidation progresses. This reason is also due to the limitation of the two-dimensional shape. When stress concentration occurs, crystal defects occur due to the stress concentration, resulting in deterioration of the electrical characteristics of the device, which is a problem. Also, as another isolation method of forming a trench in an SOI substrate and insulatingly isolating elements from each other, Japanese Patent Publication No.
There is a method disclosed in Japanese Patent No. 48.

In this method, a trench 106 is formed so as to reach the buried oxide film 103 as shown in FIG. 11 (FIG. 11A), and then a mask made of an insulating film used for etching and the buried oxide film are removed. An appropriate amount of isotropic etching is used to expose the silicon at the top and bottom corners of the trench (see FIG. 11).
(B)), the exposed silicon is isotropically etched (FIG. 11C), and then an oxide film is formed on the inner wall of the trench by a thermal oxidation method (FIG. 11D). is there. This method has the effect of suppressing the occurrence of crystal defects as a result of the trench corners being rounded.

However, even in this method, FIG.
As indicated by a circle in (d), where the oxide film grown from the corner of the buried oxide film meets the oxide film grown from the bottom of the trench, a sharp edge similar to that shown in FIG. A shape is formed. Therefore,
Also in this case, electric field concentration occurs as in the previous case, and the breakdown voltage is lowered.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a method for manufacturing a semiconductor device having a high breakdown voltage and having a reduced breakdown voltage, which is reduced or prevented. The purpose is to do.

[0008]

In order to achieve the above object, the present invention provides a second semiconductor according to the first aspect of the invention, wherein the second semiconductor is formed on the surface of the first semiconductor substrate through the first insulating film. A step of joining the substrates; a step of forming a mask on the surface of the second semiconductor substrate; and a step of etching the second semiconductor substrate using the mask to form a separation groove reaching the first insulating film. Forming, followed by etching the first insulating film in the isolation trench using the mask until the first semiconductor substrate is reached, and subsequently using the mask to etch the first insulating film in the isolation trench. The step of etching the first semiconductor substrate, and the side wall surface of the second semiconductor substrate and the surface of the first semiconductor substrate in the separation groove are oxidized by a thermal oxidation method so that the inner wall portion of the separation groove has the first surface. Contact with the insulating film of 1 Forming a second insulating film, it is characterized by having a step of forming the element formation region dielectrically isolated by the isolation trench on the second semiconductor substrate.

According to a second aspect of the invention, the step of joining the second semiconductor substrate to the surface of the first semiconductor substrate via the first insulating film, and the step of bonding the second semiconductor substrate to the surface of the second semiconductor substrate. A step of forming a mask on the second semiconductor substrate, a step of etching the second semiconductor substrate using the mask to form a separation groove reaching the first insulating film, and a step of continuously forming a separation groove in the separation groove using the mask. Etching the first insulating film until it reaches the first semiconductor substrate, and oxidizing the sidewall surface of the second semiconductor substrate and the surface of the first semiconductor substrate in the isolation trench by a thermal oxidation method. And then forming a second insulating film in contact with the first insulating film on the inner wall portion of the isolation trench, and forming an element formation region that is insulated and isolated by the isolation trench on the second semiconductor substrate. Characterized by having .

According to a third aspect of the present invention, in the first or second aspect of the present invention, the mask is composed of a plurality of mask layers so as to be different masks in the plurality of etching steps. It has a feature. In the invention according to claim 4, the step of joining the second semiconductor substrate on the surface of the first semiconductor substrate via the first insulating film, and the step of joining the second semiconductor substrate from the surface of the second semiconductor substrate to the second semiconductor substrate. Forming a separation groove that reaches at least the first semiconductor substrate through the semiconductor substrate and the first insulating film, and a sidewall surface of the second semiconductor substrate in the separation groove by a thermal oxidation method. And oxidizing the surface of the first semiconductor substrate to form a second insulating film in contact with the first insulating film on the inner wall portion of the separation groove, and insulatingly separating the second semiconductor substrate by the separation groove. And a step of forming a formed element formation region.

According to a fifth aspect of the present invention, the first semiconductor substrate and the second semiconductor substrate are bonded and formed via the first insulating film, and at least the surface of the second semiconductor substrate is at least the above. A separation trench is formed to reach the first insulation film, and a second insulation film is formed on the side wall surface of the second semiconductor substrate in the separation trench to form a first insulation film. A step of preparing a semiconductor substrate having an edge portion formed between them; a step of increasing the radius of curvature of the edge portion; and a step of increasing the radius of curvature of the edge portion by this step and embedding a member in the separation groove. And a step of filling.

According to the invention of claim 6, in the invention of claim 5, the step of preparing the semiconductor substrate comprises:
A step of joining a second semiconductor substrate on the surface of the first semiconductor substrate via a first insulating film, and a step of bonding the second semiconductor substrate from the surface of the second semiconductor substrate and at least the first semiconductor substrate. Forming a separation groove until reaching the insulating film; and oxidizing the side wall surface of the second semiconductor substrate and the surface of the first semiconductor substrate in the separation groove by a thermal oxidation method to form an inner wall of the separation groove. And a step of forming the second insulating film in contact with the first insulating film.

The invention according to claim 7 is characterized in that, in the invention according to claim 5 or 6, the step of increasing the radius of curvature of the edge portion is a step of etching the separation groove. There is. In the invention according to claim 8, in the invention according to claim 5 or 6, the step of increasing the radius of curvature of the edge portion is a step of depositing polycrystalline silicon in the separation groove and oxidizing it. It is characterized by being.

The invention according to claim 9 is characterized in that, in the invention according to claim 7, the oxidation of the polycrystalline silicon in the isolation trench is performed only partially. The invention according to claim 10 is characterized in that, in the invention according to claim 5 or 6, the step of increasing the radius of curvature of the edge portion is a step of forming a nitride film in the separation groove. .

[0015]

In the invention described in claim 1,
The first semiconductor substrate and the second semiconductor substrate are bonded together via the first insulating film, and a mask is formed on the surface of the second semiconductor substrate. Then, the second semiconductor substrate, the first insulating film, and the first semiconductor substrate are etched using this mask. Then, the side wall surface of the second semiconductor substrate and the surface of the first semiconductor substrate in the separation groove are oxidized by a thermal oxidation method to form a second insulating film in contact with the first insulating film on the inner wall portion of the separation groove. To do. As a result, an element formation region is formed on the second semiconductor substrate, which is insulated and separated by the separation groove.

Therefore, by oxidizing the isolation trench formed in the first semiconductor substrate, the second insulation film formed in the isolation trench is formed so as to smoothly cover the first insulation film. To be done. As a result, a sharp edge due to the above-mentioned constriction is not formed, and thus it is possible to prevent the breakdown voltage from decreasing. In the invention described in claims 2 and 4,
An isolation groove is formed from the surface of the second semiconductor substrate to the first semiconductor substrate through the first insulating film, and the sidewall surface of the second semiconductor substrate and the first semiconductor in the isolation groove are formed. The surface of the substrate is oxidized to form a second insulating film in contact with the first insulating film on the inner wall of the separation groove.

Therefore, the oxide film formed on the side wall surface of the second semiconductor substrate by oxidizing the isolation trench formed until reaching the first semiconductor has the first oxide film at the portion in contact with the first insulating film. Is formed so as to smoothly cover the insulating film. In this case, the oxide film formed on the surface of the first semiconductor substrate grows toward the upper space, and a sharp edge due to the constriction is formed between the oxide film and the first insulating film. Since the semiconductor substrate of No. 2 is separated from the corner and the bottom of the semiconductor substrate by at least a distance equal to the thickness of the first insulating film, it is possible to suppress the influence on the decrease in breakdown voltage.

In a fifth aspect of the present invention, a sidewall oxide film is formed on the sidewall surface of the second semiconductor substrate in the isolation trench and has an edge portion between the sidewall oxide film and the first insulating film. A step of increasing the radius of curvature of the edge portion is provided for the semiconductor substrate formed as described above, and by this step, the embedded member is filled in the separation groove with the radius of curvature of the edge portion being increased.

Therefore, the side wall oxide film or the like is formed by oxidation instead of oxidation after rounding as in the conventional method described above, and then the radius of curvature of the edge portion is increased to fill the filling member. Therefore, the electric field concentration due to the edge portion in the separation groove can be alleviated and the breakdown voltage can be increased.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIGS. 1A to 1D are sectional views of respective steps showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a silicon support substrate 1 (first semiconductor substrate) and a silicon substrate 2 for element formation (second semiconductor substrate) are embedded in an oxide film 3 (first). Bonding is performed by a direct bonding method via an insulating film. The buried oxide film 3 is formed on the element forming substrate 2 prior to the bonding.
Alternatively, it is formed in advance on both or one of the surfaces of the supporting substrate 1 by, for example, a thermal oxidation method. After that, an oxide film 4 is formed on the element-forming main surface of the silicon substrate 2 by a thermal oxidation method, a CVD method, or the like. This oxide film 4
Is patterned into a predetermined shape, and the silicon substrate 2 is etched into a deep groove shape (for example, a width of about 2 μm and a depth of about 10 μm) by the trench etching technique using the reactive ion etching method using this as a mask. Then, the trench 5 is formed.

Next, as shown in FIG. 1B, this time, the reaction gas is switched to anisotropic etching of the oxide film to continue anisotropic etching, and the bottom portion 6 of the trench 5 becomes the supporting substrate 1. To reach. Next, as shown in FIG. 1C, the reaction gas is switched again to the silicon trench etching to continue the etching so that the trench bottom portion 6 is below the interface 7 between the supporting substrate 1 and the buried oxide film 3. To do.

Through the above etching process, the film thickness t _oxm of the oxide film 4 is set so that the oxide film 4 remains on the silicon substrate 2 in a predetermined shape. That is, the selection ratio of silicon and oxide film in the trench etching is r (etching amount of silicon per unit time / etching amount of oxide film per unit time), and the thickness of the silicon substrate 2 is t.
_{If soi} , the thickness of the buried oxide film is t _box , and the etching depth of the supporting substrate 1 is t _ovr ,

[0024]

## _EQU1 ## The film thickness t _oxm of the oxide film 4 is set so that t _oxm ≧ (t _soi / r) + t _box + (t _ovr / r). This is because the silicon substrate 2 is etched by trench etching using the oxide film 4 as a mask until the buried oxide film 3 is reached, and then the etching gas is switched to fill the buried oxide film 3 with the etching gas.
Is removed by etching, the reaction gas is switched to the silicon trench etching gas again, and the support substrate 1 can be overetched by a predetermined amount using the mask made of the oxide film 4 remaining on the silicon substrate 2 as it is. It is the minimum film thickness.

Next, the etched substrate is washed to remove the reaction products on the sidewalls of the trenches 5 and, at the same time, to remove the oxide film 4 as a mask material. An oxide film 8 (second insulating film) is formed on the surface of the support substrate 1 exposed at the bottom of the groove so as to contact the buried oxide film 3 (FIG. 1D). In addition,
Regarding the mask material, when the process is simplified, the oxide film 8 may be directly formed without removing the mask material.

In this way, the oxide film 8 formed on the side wall of the trench 5 is formed so as to smoothly cover the end portion of the buried oxide film 3 at the portions 9 and 10 in contact with the buried oxide film 3. As a result, electric field concentration is caused in the prior art as shown by a circle in FIG. 10, so that a sharp edge shape due to the constriction of the oxide film is not formed and it is possible to prevent the breakdown voltage from being lowered. Become.

Thereafter, as shown in FIG. 1 (e), the inside of the trench 5 is filled with polycrystalline silicon 11, flattened, and elements are formed in the silicon substrate 2 by a normal device process. Buried oxide film 3 for each block
And an insulating film is isolated by the oxide film 8 inside the trench 5 to obtain an insulator-isolated semiconductor device having a desired isolation voltage. In addition,
In the above-mentioned embodiment, a single layer film made of the oxide film 4 is used as an insulating film used as a mask for trench etching, but a multilayer mask layer made of two or more insulating films is used to cope with a plurality of etchings. The masks used may be different.

For example, a three-layer film in which the uppermost layer is a silicon oxide film or a silicon nitride film, the intermediate layer is silicon, and the lowermost layer is a silicon oxide film or a silicon nitride film can be used. Here, the uppermost layer made of a silicon oxide film or a silicon nitride film is a film having a large selection ratio for etching silicon, and is used as a mask when etching the silicon substrate 2. Further, the silicon used as the intermediate layer serves as a mask when the buried oxide film 3 is etched, and the use of silicon (polycrystalline silicon or amorphous silicon) sets a large selection ratio to the oxide film. Because you can. The silicon oxide film or silicon nitride film used for the bottom layer is
It serves as a mask when the support substrate 1 is etched.

The mask material used for the uppermost layer and the lowermost layer is not limited to the above materials as long as it has a high trench etching selection ratio with respect to silicon. Similarly, the mask material used as the intermediate layer is not limited to the above materials as long as it has a high etching selection ratio with respect to the oxide film. When the two-layer film is used as a mask, the upper layer is composed of a silicon oxide film and the lower layer is composed of a silicon nitride film. The upper silicon oxide film is used as the most mask for trench etching the silicon substrate 2 due to the selection ratio, and the lower silicon nitride film is used as the mask for etching the buried oxide film 3 and the supporting substrate 1. (Second Embodiment) FIG. 2 shows a second embodiment of the present invention. In the second embodiment, unlike the first embodiment shown in FIG. 1, the buried oxide film 3 is etched until reaching the supporting substrate 1 by using the oxide film 4 as a mask in FIG. The etching of the supporting substrate 1 as shown in c) is not performed, and the sidewall oxidation step similar to that shown in FIG. 1D is immediately performed.

As a result, the shape of the inside of the trench 5 becomes as shown in FIG. That is, the oxide film 8 is formed on the surface of the silicon substrate 2 so as to be in contact with the buried oxide film 3.
The oxide film 8 thus formed on the side wall of the trench 5 is formed so as to smoothly cover the end portion of the buried oxide film 3 at the portion 9 in contact with the buried oxide film 3, as in the first embodiment. The corner portion 12 is shaped so as to go under the edge of the buried oxide film 3. as a result,
A sharp edge is formed in the bottom corner portion 12 based on the constriction of the buried oxide film 3. However, since the bottom of the trench 5 is formed so as to remove the buried oxide film 3 and reach the support substrate 1, the above-mentioned edge is formed. It is separated from the corner and the bottom of the element forming silicon substrate 2 by at least a distance equal to the thickness of the buried oxide film 3. Therefore, according to the second embodiment, it is possible to minimize the effect on the breakdown voltage.

In the second embodiment, a single layer film made of the oxide film 4 is used as an insulating film used as a mask for trench etching. However, the uppermost layer is a silicon oxide film or a silicon nitride film in a multilayer film. Used for multiple etchings, such as a three-layer film in which the intermediate layer is silicon and the bottom layer is a silicon nitride film, or a two-layer film in which the upper layer is a silicon oxide film and the lower layer is a silicon nitride film. Different masks may be used.

That is, trench etching of the silicon substrate 2 is performed using the uppermost silicon oxide film or silicon nitride film as a mask, and then the buried oxide film 3 is used using the intermediate layer silicon (polycrystalline silicon or amorphous silicon) as a mask. Etching is performed. The lowermost silicon nitride film is inserted to distinguish the boundary between the silicon substrate 2 and the silicon used as a mask, and the silicon nitride film is exposed after the etching of the buried oxide film 3 is completed. The film thickness of the multilayer film is set in advance. After the etching of the buried oxide film 3 is completed in this way, the silicon nitride film is selectively removed by etching with phosphoric acid or the like to obtain a desired shape.

When a two-layer film is used, trench etching of the silicon substrate 2 is performed by using the upper silicon oxide film as a mask, and the buried oxide film 3 is etched by using the lower silicon nitride film as a mask. . After that, the silicon nitride film is selectively removed by etching with phosphoric acid or the like to obtain a desired shape. The mask material used in this second embodiment is the same as the first one.
The materials are not limited to the materials described in the above-mentioned embodiments as long as they are selected based on the same criteria as described in the embodiments and have a high selection ratio with respect to the object to be etched. (Third Embodiment) Next, a description will be given of a third embodiment in which the dielectric strength is improved by increasing the radius of curvature of the sharp edge due to the constriction of the buried oxide film 3 described above. To do.

FIG. 3 shows a manufacturing method of the third embodiment. First, as shown in FIG. 3A, the supporting substrate 1 and the silicon substrate 2 for element formation are bonded by the direct bonding method through the buried oxide film 3 to form the oxide film 4, and then the oxide film 4 is formed.
Is patterned into a predetermined shape, and using this as a mask, the silicon substrate 2 is etched and removed in a deep groove shape to reach the buried oxide film 3 by a trench etching technique using a reactive ion etching method to form a trench 5.

Next, after removing the oxide film 4 as the mask material, the oxide film 8 is formed on the side wall of the trench 5 by using a thermal oxidation method or the like.
Are formed to obtain the structure shown in FIG. In this state, the shape of the bottom portion of the trench 5 has a sharp edge portion (the portion where the edge portion is formed is called a convex hollow portion) as shown in the figure. Next, etching is performed with a dilute HF solution to increase the radius of curvature of the edge as shown in FIG. 3C, and finally, as in FIG. 1E, the trench 5 is filled with polycrystalline silicon 11. , Flattening (FIG. 3D).

Here, the radius of curvature of the edge portion shown in FIG. 3B is about 0.02 μm. In this state, HF etching is performed as shown in FIG. Is isotropically etched, the radius of curvature of the convex cavity is 0.02μ.
It is the sum of about m + HF etching amount. Further, since the HF etching amount is proportional to the HF etching time, the radius of curvature and the etching time have the relationship shown in FIG. 4 with the concentration of the HF solution as a parameter.

FIG. 5 shows the result of actual measurement of the breakdown strength (= dielectric strength / sidewall oxide film × 2) when the HF etching conditions are changed and the radius of curvature is changed. It can be seen that the fracture strength decreases as the radius of curvature decreases. The film thickness of the side wall oxide film 8 becomes the oxide film thickness before etching-the amount of HF etching by etching.
The breakdown voltage is the breakdown strength × (oxide film thickness before etching−HF etching amount) × 2.

Therefore, the breakdown voltage can be predicted by obtaining the breaking strength from FIG. For example, when the oxide film thickness before etching is 0.7 μm, the relationship between the radius of curvature of the convex cavity and the withstand voltage is as shown in FIG. From this figure, it is understood that when the radius of curvature is set to about 0.07 μm by HF etching, the withstand voltage is improved by about 10% as compared with the conventional structure (when the radius of curvature is about 0.02 μm). Furthermore, the radius of curvature is 0.05 to 0.10 μm.
With this, the breakdown voltage is improved by 5%, and 0.04 to 0.
By setting the thickness to 13 μm, the breakdown voltage is improved by 3%.

In the third embodiment, the sidewall oxide film is not formed after rounding the edge in the trench as in the prior art, but the edge portion in the trench is formed after the sidewall oxide film 8 is formed. Since the radius of curvature is increased, a sharp edge shape is not finally formed, so that the problem of reduction in breakdown voltage due to electric field concentration can be solved. (Fourth Embodiment) In the fourth embodiment, after forming the sidewall oxide film 8 shown in FIG. 3B, polycrystalline silicon is deposited and oxidized to thicken the oxide film in the trench 5. It was done like this.

That is, after forming the sidewall oxide film 8 shown in FIG. 3B, polycrystalline silicon 13 is deposited in the trench 5 (FIG. 7A). Polycrystalline silicon 13 is depressurized CV
By using D, the coverage property becomes good, and it is possible to accumulate without gaps. By thermally oxidizing all of this polycrystalline silicon 13, the radius of curvature of the convex cavity can be increased as shown in FIG. 7B, and as a result, electric field concentration can be reduced and dielectric strength can be improved. it can. Finally, as in FIG. 1E, the trench 5 is filled with polycrystalline silicon 11 and planarized.

According to this embodiment, not only the radius of curvature of the convex cavity is increased, but also the side wall oxide film itself is thickened, so that there are two excellent features: relaxation of electric field concentration and increase of oxide film thickness. effective. For example, the polycrystalline silicon 13 may be replaced by 0.
It was confirmed that the breakdown strength (calculated in consideration of the polycrystalline silicon oxide film thickness) was increased when the polycrystalline silicon 13 was oxidized to a thickness of 05 μm or more and oxidized. It can be said that this is due to not only the increase in the oxide film thickness but also the effect that the electric field concentration is alleviated because the radius of curvature of the convex hollow portion is increased. (Fifth Embodiment) In the fourth embodiment, the polycrystalline silicon 1 is used.
Although all of 3 are thermally oxidized, only a part of the polycrystalline silicon 13 may be oxidized.
That is, after forming the side wall oxide film 8 shown in FIG. 3B, the polycrystalline silicon 13 is deposited, and only a part thereof is oxidized to form the polycrystalline silicon oxide film 13a to obtain the structure shown in FIG. . After that, the polycrystalline silicon 11 is deposited in the trench 5 as in FIG.

Also in this case, as in the case of the fourth embodiment described above, the dielectric strength voltage can be improved by thickening the entire oxide film in the trench 5. In this case, the film thickness of the polycrystalline silicon 13 that is thermally oxidized may be enough to compensate for the decrease in the dielectric strength due to the electric field concentration. For example, the radius of curvature of the convex cavity is 0.02
When the thickness of the side wall oxide film 8 is 0.7 μm and the dielectric strength is breakdown strength = breakdown strength × (side wall oxide film × 2), the dielectric strength is about 530V. Polycrystalline silicon oxide film 13a
When the breakdown strength of the film thickness is about 5 MV / CM, if the film thickness of the polycrystalline silicon oxide film 13a is about 0.18 μm or more, the electric field concentration in the convex cavity can be compensated.

In the fifth embodiment, not only the breakdown voltage can be improved, but also the following effects are obtained.
First, S that forms a device with the same oxide film thickness
That is, the stress applied to i (silicon substrate 2) can be reduced. Generally, silicon oxide film (SiO ₂ )
Between Si and Si, stress remains due to the difference in the expansion coefficient. This stress causes defects in Si, causing a problem of degrading device performance. In this embodiment, the oxide film thickness that bears the dielectric breakdown voltage is the total film thickness of the sidewall oxide film 8 and the polycrystalline silicon oxide film 13a, but the sidewall oxide film 8 is the only oxide film that generates stress in Si, and It is possible to reduce defects generated in Si while ensuring the above.

Secondly, in this embodiment, the breakdown voltage is taken care of by the sidewall oxide film 8 and the polycrystalline silicon oxide film 13a. Therefore, even if one of the oxide films is dielectrically broken down, the other oxide film is used. Withstand voltage can be secured. Therefore, it is possible to reduce the probability of dielectric breakdown as compared with the case where a single oxide film has a withstand voltage as in the fourth embodiment. (Sixth Embodiment) In this embodiment, a nitride film (SiN film) 14 is deposited as shown in FIG. 9 instead of depositing the polycrystalline silicon 13 of the fourth embodiment. In this embodiment, as in the fourth embodiment, the SiN film 14 is embedded in the convex cavity to relax the electric field concentration. Since the SiN film 14 is an insulator, this method not only alleviates the electric field concentration but also the thickness of the insulator (Si
This has the effect of improving the withstand voltage by increasing the (O ₂ film thickness + SiN film thickness).

In the third and subsequent embodiments, the support substrate 1 and the silicon substrate 2 for element formation as described above are bonded via the buried oxide film 3, and then the isolation trench and the sidewall are formed. Not only the one that forms the oxide film 8,
As shown in Japanese Patent Application Laid-Open No. 2-966350, a separation groove is formed in advance on a silicon substrate for element formation, an oxide film is formed on the separation groove, and thereafter, the separation groove is bonded to the supporting substrate 1 to form a separation groove.
You may make it use what formed the semiconductor substrate as shown in (b).

Further, in those embodiments, the case where the isolation trench reaches the buried oxide film 3 is shown, but the invention is not limited to this, and the isolation trench may be formed even in the buried oxide film 3. .

[Brief description of drawings]

FIG. 1 is a sectional view of each step showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view of each step showing the third embodiment of the present invention.

FIG. 4 is a characteristic diagram showing a relationship between a radius of curvature of a convex cavity and etching time.

FIG. 5 is a characteristic diagram showing a relationship between a radius of curvature of a convex hollow portion and a breaking strength.

FIG. 6 is a characteristic diagram showing the relationship between the radius of curvature of a convex cavity and the withstand voltage.

FIG. 7 is a sectional view of a partial process, showing a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a fifth embodiment of the present invention.

FIG. 9 is a sectional view showing a sixth embodiment of the present invention.

FIG. 10 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 11 is a sectional view of each step showing a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

 1 Silicon support substrate (first semiconductor substrate) 2 Silicon substrate (second semiconductor substrate) 3 Embedded oxide film (first insulating film) 4 Oxide film (mask) 5 Trench (separation groove) 8 Oxide film (second) Insulating film) 11 Polycrystalline silicon (embedded member)

Claims (10)

[Claims] 1. A step of joining a second semiconductor substrate to the surface of the first semiconductor substrate via a first insulating film, and a step of forming a mask on the surface of the second semiconductor substrate, Etching the second semiconductor substrate using the mask to form an isolation trench reaching the first insulating film; and subsequently using the mask to etch the first insulating film in the isolation trench. Etching until reaching the first semiconductor substrate, subsequently etching the first semiconductor substrate in the separation groove using the mask, and the second semiconductor in the separation groove by thermal oxidation. The side wall surface of the substrate and the surface of the first semiconductor substrate are oxidized to form a second insulating film in contact with the first insulating film on the inner wall portion of the separation groove, and the separation is performed on the second semiconductor substrate. Isolated by the groove The method of manufacturing a semiconductor device characterized by a step of forming an element formation region. 2. A step of joining a second semiconductor substrate on the surface of the first semiconductor substrate via a first insulating film, and a step of forming a mask on the surface of the second semiconductor substrate. Etching the second semiconductor substrate using the mask to form an isolation trench reaching the first insulating film; and subsequently using the mask to etch the first insulating film in the isolation trench. Etching until reaching the first semiconductor substrate, and oxidizing the side wall surface of the second semiconductor substrate and the surface of the first semiconductor substrate in the separation groove by a thermal oxidation method to form an inner wall portion of the separation groove. A second insulating film in contact with the first insulating film, and forming an element formation region that is insulated and separated by the separation groove in the second semiconductor substrate. Manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the mask is composed of a plurality of mask layers so as to be different masks in the plurality of etching steps. 4. A step of joining a second semiconductor substrate on the surface of the first semiconductor substrate via a first insulating film; and a step of joining the second semiconductor substrate and the second semiconductor substrate from the surface of the second semiconductor substrate. Forming a separation groove at least through the first insulating film to reach the first semiconductor substrate; and a side wall surface of the second semiconductor substrate in the separation groove and the first groove in the separation groove by a thermal oxidation method. A surface of a semiconductor substrate is oxidized to form a second insulating film in contact with the first insulating film on an inner wall portion of the isolation groove, and an element formation region is isolated and isolated by the isolation groove on the second semiconductor substrate. And a step of forming a semiconductor device. 5. A first semiconductor substrate and a second semiconductor substrate are bonded together via a first insulating film, and the second semiconductor substrate is formed.
A separating groove is formed from the surface of the semiconductor substrate to at least the first insulating film, and a second insulating film is formed on the side wall surface of the second semiconductor substrate in the separating groove, A step of preparing a semiconductor substrate having an edge portion formed between the first insulating film, a step of increasing the radius of curvature of the edge portion, and a state of increasing the radius of curvature of the edge portion by this step And a step of filling a filling member in the separation groove. 6. The step of preparing the semiconductor substrate, the step of joining a second semiconductor substrate on the surface of the first semiconductor substrate via a first insulating film, and the step of preparing the second semiconductor substrate. Forming a separation groove from the surface to reach the second semiconductor substrate and at least the first insulating film; and a sidewall surface of the second semiconductor substrate in the separation groove by the thermal oxidation method and the first insulation film. 5. The step of oxidizing the surface of the semiconductor substrate to form the second insulating film in contact with the first insulating film on the inner wall portion of the separation groove. Manufacturing method. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the step of increasing the radius of curvature of the edge portion is a step of etching the isolation trench. 8. The semiconductor according to claim 5, wherein the step of increasing the radius of curvature of the edge portion is a step of depositing polycrystalline silicon in the isolation trench and oxidizing it. Device manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the polycrystalline silicon in the isolation trench is oxidized only partially. 10. The method of manufacturing a semiconductor device according to claim 5, wherein the step of increasing the radius of curvature of the edge portion is a step of forming a nitride film in the isolation trench.