JPH07334987A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress the leakage current at the time of a bit line precharging (at the time of a standby) due to the short circuit between a bit line and a word line in a semiconductor storage device. CONSTITUTION:A pull-down transistor TWD121 becomes into on state when a corresponding word line WL11 is not selected and connects the corresponding word line WL11 with a common power source line VSX. An impedance changing means 31 changing the impedance of a path at the time of the standby from the impedance at the time when either of word lines is selected and making the impedance at the time of the standby higher than that at the time of an operation is provided in the path through which the common power source line VSX is grounded. Thus, even in the case where the short circuit between the bit line and the word line is present, although the bit line is precharged to a prescribed potential, the leakage current (a standby current) heading to the ground through the faulty bit line-word line can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor memory device represented by a DRAM (Dynamic Random Access Memory), and more specifically, an increase in leak current due to a short circuit between a bit line and a word line during standby,
That is, the present invention relates to a device that suppresses an increase in power consumption during standby.

[0002]

2. Description of the Related Art Generally, a semiconductor memory device is provided with a large number of precharge circuits for precharging a large number of bit line pairs to an intermediate potential between a power supply potential and a ground potential.
During standby, which is the precharge period of the bit line pair, the precharge circuit precharges each bit line pair to an intermediate potential and grounds the word line. When any one of the bit lines and the word line are short-circuited during the standby, a large leak current flows from the shorted bit line to the ground potential via the word line. This leakage current is called a standby current, and not only greatly reduces the yield of the semiconductor memory device, but also in a semiconductor memory device driven by a battery, this leakage current causes the battery life to be shortened.

Therefore, in order to reduce the standby current,
For example, if a fuse is arranged in each of a number of precharge circuits and the word line and the bit line are short-circuited, the fuse of the precharge circuit corresponding to the defective bit line is blown to set the defective bit line pair to the intermediate potential. It is conceivable not to precharge. However, the precharge circuit is arranged between two bit lines forming a pair of bit lines, and a sense amplifier circuit and the like are arranged around the precharge circuit. Therefore, a fuse is provided inside or around each precharge circuit. Is spatially difficult to place.

Therefore, there is a conventional one in which a plurality of precharge power supply lines are provided, one for each of the plurality of precharge circuits, and fuses are arranged on the respective precharge power supply lines. As a technique for reducing the leakage current during standby in the DRAM by such a method,
I S S C C Digest Of
Technical Papers 93 (1993) pp. 48-49 (ISSCCDIGEST OF TECHN
ICAL PAPERS 93 (1993) P. 48-
49).

In this conventional example, as shown in FIGS. 11 and 12, one memory cell array is divided into a plurality of memory cell blocks 500, 500 ... (Only one is shown in FIG. 12), and the memory cell block is also shown. Sense amplifier blocks 700, 700 are arranged on the sides of 500, 500.
Each of the sense amplifier blocks 700, 700, ... Is provided with a precharge circuit of a number equal to the number of pairs of bit lines in the corresponding memory cell block 500 in the direction in which the bit lines are arranged. Precharge the line pair to a predetermined potential. Further, as shown in FIG. 12, a redundant memory cell block 600 and a sense amplifier block 800 are provided on the side of the redundant memory cell block 600 (1 in FIG. 12) for redundancy relief for a short circuit between a bit line and a word line.
Only shown). The regular sense amplifier block 700
... and each of the sense amplifier blocks 800 for redundancy relief, precharge power supply lines 650 a and 650 s are provided, and a precharge potential supply line 670 that supplies a potential to these power supply lines 650 a and 650 s is provided. Charge power supply line 650a ...
, 660 s are respectively provided between the precharge potential supply line 670 and the precharge potential supply line 670. When one bit line in any memory cell block 500 is short-circuited with a word line, the defective bit is cut by cutting off the power switch 660a corresponding to the memory cell block 500 including the defective bit line. The precharge to the memory cell block 500 including the line is prevented to prevent the leakage current from flowing, and the power switch 660 s corresponding to the redundant memory cell block 600 is closed to precharge the redundant memory cell block 600. If possible, the memory cell block 500 including the defective bit line
Is replaced with the redundant memory cell block 600.

[0006]

However, the above-mentioned conventional techniques have the following drawbacks. That is, when one bit line and one word line are short-circuited in one memory cell block 500, the power switch 660a of the precharge power supply line 650a corresponding to the memory cell block 500 is opened. Therefore, the precharge potential is not supplied to the sense amplifier block 700 corresponding to the precharge power supply line 650a, and therefore, in the memory cell block 500 including the defective bit line, a large number of normal bit line pairs and word lines are provided. Cannot be used, and the entire memory cell block 500 must be replaced with the memory cell block 600 for redundancy repair, and as a result, the memory cell block 60 for redundancy repair must be replaced.
It is necessary to set 0 to the same size as the regular memory cell block 500, which has a drawback of increasing the chip area.

The present inventors have also found that even if the precharge power supply line 650a is opened by the power switch 660a, a standby current flows from another power supply line to the ground line via the defective bit line and word line. discovered. This state is shown in FIG.
Shown in.

In FIG. 13, BL and / BL are two bit lines that form a bit line pair, WL is a word line, and 800 is a pre-transistor consisting of three transistors that connect the two bit lines BL and / BL. Charge circuit, 810 is this precharge circuit 800
820 is a precharge power supply line for supplying a predetermined potential to the precharge circuit 800 and an equalize signal line 820 for turning on the three transistors of the precharge circuit 800. Reference numeral 850 denotes a sense amplifier, which includes two P-channel type transistors TP and TP connected in series for connecting the bit line pair BL and / BL, and the bit line pair BL and
/ BL is connected in series with two N-channel type transistors TN and TN, and a common source line SP is connected to the two N-channel type transistors TP and TP. Another common source line SN is connected to the connection point of the channel transistors TN, TN. Further, 860 is a common source line equalizing circuit composed of three transistors which connect the two common source lines SP and SN to equalize the potential of the power source of 1 / 2.Vcc, and 870 is a common source line SP power source. This is a potential supply circuit that brings the other common source line SN to the ground potential Vss to the potential Vcc. eq is a common source line equalizer circuit 86
Equalize signal output to 0, / eq is potential supply circuit 87
The signal output to 0 is a signal obtained by inverting the equalize signal eq.

The operation of the configuration shown in FIG. 13 will be described based on the signal waveforms shown in FIG.

In the precharge period of the bit line pair, the signal EQ of the equalize signal line 820 is raised and the bit line pair B
Precharge L and / BL to a predetermined potential (1/2 · Vcc) and raise the equalize signal eq to common source line SP,
SN is equalized to a predetermined potential (1/2 · Vcc), and the sense amplifier circuit 850 is placed in a standby state. Bit line pair BL. During the amplification period of / BL, when the signal EQ and the equalization signal eq of the equalization signal line 820 are lowered and the inverted signal / eq of the equalization signal eq is raised, the bit line pair BL, / BL is selected by the selected word line WL. The minute potential difference generated in the sense amplifier is detected and amplified by the sense amplifier circuit 850.

However, in the conventional technique shown in FIG. 13, for example, when there is a short between one bit line BL and word line WL (indicated by "R" in FIG. 13), the bit line pair During the precharge period, the potential of the defective bit line BL becomes lower than the precharge potential 1 / 2.Vcc. Along with this, a minute potential difference is generated between the bit line pair BL, / BL, and the gate potential of the P channel transistor TP located below the sense amplifier circuit 850 is the precharge potential.
When the voltage becomes lower than 1/2 Vcc and the gate-source voltage of the P-channel transistor TP exceeds a threshold value, the P-channel transistor TP is turned on and the common source line SP is turned on. Flow to the other bit line / BL through the lower transistor TP which has become the result, and as a result, the upper NP channel transistor TN is turned on, from the power source of 1 / 2.Vcc to the common source line equalizing circuit 860 and the above-mentioned. Upper transistor turned on
A standby current flows toward the ground via the defective bit line BL and the word line WL via TN.

The present invention has been made in view of the above problems. An object of the present invention is to reduce the standby current while limiting the redundancy relief memory cell block to a small area. In order to eliminate the standby current caused by the malfunction of the sense amplifier circuit during the precharge period of the bit line pair, thirdly, from the point that the word line is short-circuited with the bit line, measures are taken in the word line. , To reduce or eliminate the standby current.

[0013]

In order to achieve the above object, according to the present invention, a part of a large number of bit line pairs in one memory cell block can be redundantly replaced in units of some bit line pairs. By adopting the above, other normal bit line pairs except for one defective bit line pair are used as they are in one memory cell block to suppress the increase of the chip area.

Further, according to the present invention, the plurality of transistors forming the sense amplifier circuit are further turned off during the precharge period of the bit line pair to eliminate the standby current flowing through the sense amplifier circuit.

Further, according to the present invention, the impedance between the word line and the ground line is adjusted to be high during the precharge period of the bit line pair to reduce the value of the standby current.

That is, in the semiconductor memory device according to the first aspect of the present invention, a plurality of cell arrays composed of a plurality of word lines and a plurality of pairs of bit lines intersecting with the word lines are divided into a plurality in the direction in which the word lines are arranged. Memory cell blocks, a plurality of sense amplifier blocks arranged in the same number as the plurality of memory cell blocks, and arranged on the side of the corresponding memory cell blocks on which the word lines are arranged, and between the memory cell blocks. Each of the sense amplifier blocks includes a plurality of shared column selection signal lines, precharge power supply lines provided in the same number as the column selection signal lines, and disconnecting means arranged in each of the precharge power supply lines. , A plurality of precharge circuits for precharging a plurality of pairs of bit lines in a corresponding memory cell block to a predetermined potential, respectively, One line is provided for a plurality of pairs of bit lines of each memory cell block as a unit, and one pair of bit lines is simultaneously selected for each memory cell block. A predetermined potential is supplied to the precharge circuits of a plurality of pairs of bit lines selectable by the column selection signal line, and the one column selection signal line and each memory cell block corresponding to this column selection signal line A plurality of pairs of bit lines, a plurality of precharge circuits of each sense amplifier block, and one precharge power supply line as one unit, and a redundant replacement unit at the time of shorting the word line-bit line is configured. Characterize.

According to a second aspect of the invention, in the semiconductor memory device according to the first aspect, there is provided a precharge potential supply circuit for supplying a precharge potential to each precharge power supply line, and each disconnecting means includes: It is characterized in that it is arranged in the vicinity of a connection point between the precharge potential supply circuit and each precharge power supply line.

Further, the invention according to claim 3 is characterized in that, in the semiconductor memory device according to claim 1 or 2, the cutting means comprises a fuse element.

In addition, in the semiconductor memory device of the present invention as defined in claim 4, a memory cell including a capacitor and a transistor, a pair of bit lines from which a signal is read from the memory cell, and a conductivity type of the transistor of the memory cell. A flip-flop type sense amplifier for amplifying the signal read to the pair of bit lines, and a first transistor of the opposite conductivity type and a second transistor of the same conductivity type. What is claimed is: 1. A semiconductor memory device, comprising: a common source line connected to a first transistor and a second transistor and supplying a predetermined potential to a corresponding transistor, wherein:
A common source line connected to a first transistor of a conductivity type opposite to that of the transistor of the memory cell,
A potential supply means is provided for supplying a potential on a side at which the first transistor is cut off from a potential half the potential of the power supply of the semiconductor memory device during a period in which the sense amplifier is inactive. Characterize.

Further, in the invention according to claim 5, in the semiconductor memory device according to claim 4, a second conductivity type of a plurality of common source lines is the same as a conductivity type of a transistor of a memory cell. To the common source line connected to the transistor, the potential on the side where the second transistor is cut off from the potential which is ½ of the potential of the power supply of the semiconductor memory device is cut off during the period when the sense amplifier is inactive. It is characterized in that it is provided with another potential supply means for supplying.

According to another aspect of the semiconductor memory device of the present invention, a plurality of memory cells each of which includes a capacitor and a transistor, a plurality of word lines each controlling a transistor of the plurality of memory cells, and a plurality of the plurality of word lines. A plurality of pairs of bit lines from which the information stored in the capacitors of the individual memory cells are respectively read; and a plurality of sense amplifiers that amplify the information read to the plurality of pairs of bit lines, respectively.
A pull-down transistor, which is provided in the same number as the plurality of word lines and which grounds the corresponding word line when the corresponding word line is not selected, and the plurality of pairs of bit lines, are connected to the plurality of pairs of bit lines during standby when all the word lines are not selected. A precharge circuit for precharging to a predetermined potential is provided, and a current limiting unit for limiting a current flowing from each word line to the ground via the pull-down transistor in the standby mode is provided.

According to a seventh aspect of the invention, in the semiconductor memory device according to the sixth aspect, the current limiting means is:
A common power supply line to which the source of each pull-down transistor is connected and a path for grounding the common power supply line are arranged, and the impedance of this path is changed at the time of standby and the operation when any word line is selected, It is characterized by comprising impedance changing means for making the impedance higher during standby than during operation.

Further, in the invention according to claim 8, in the semiconductor memory device according to claim 7, the impedance changing means includes a transistor arranged in a path for grounding the common power supply line, and the transistor is precharged. The precharge circuit activation signal is controlled based on a circuit activation signal, and the potential of the activation signal of the precharge circuit is different between standby and operation, and the transistor is in a higher impedance state in standby than in operation. To do.

In addition, in the invention according to claim 9, in the semiconductor memory device according to claim 7, the impedance changing means includes a transistor arranged in a path for grounding the common power supply line, and the transistor is a sense circuit. The sense amplifier activation signal is controlled by an amplifier activation signal, and the potential of the sense amplifier activation signal is different between the standby state and the operating state, and the transistor has a higher impedance state in the standby state than in the operating state.

Further, in the invention according to claim 10,
10. The semiconductor memory device according to claim 9, wherein the transistor is an N-type transistor, the activation signal of the sense amplifier is a potential of a common source line of P-type transistors forming the sense amplifier, and the common of the P-type transistors. The source line has a potential half the potential of the power supply of the semiconductor memory circuit during standby, and has the potential of the power supply during operation.

According to the invention of claim 11, the invention according to claim 6
In the semiconductor memory device described above, the current limiting means changes the common power supply line to which the source of each pull-down transistor is connected and the potential of the common power supply line during standby and during operation when any one of the word lines is selected. However, it is characterized in that it comprises a potential changing means for making the potential higher during standby than during operation.

According to the twelfth aspect of the invention, in the semiconductor memory device according to the eleventh aspect, the potential changing means sets the potential of the common power supply line to a potential equal to the precharge potential of the bit line during standby. It is characterized by

Further, in the invention according to claim 13, in the semiconductor memory device according to claim 12, the potential changing means is a common source line for driving an N-type transistor which constitutes a sense amplifier, and the common source. The line is connected to the common power supply line, and is controlled to the precharge potential of the bit line during standby and to the ground potential during operation.

In addition, in the fourteenth aspect of the present invention, in the semiconductor memory device according to the eleventh aspect, the potential changing means comprises a clamp circuit that clamps the potential of the common power supply line to a higher level during standby than during operation. It is characterized by

In addition, according to the invention of claim 15,
15. The semiconductor memory device according to claim 14, wherein the clamp circuit is arranged between a common power supply line and ground and has an N-type transistor having a predetermined threshold voltage and a gate electrode of the transistor, and the common power supply is in standby. And a control circuit which supplies the potential of the line and supplies the potential of the power source of the semiconductor memory circuit during operation.

According to a sixteenth aspect of the present invention, the first aspect
5. The semiconductor memory device according to 5, wherein the control circuit includes an N-type transistor and a P-type transistor connected in series, the source of the N-type transistor is a common power supply line, and the source of the P-type transistor is a power supply of the semiconductor memory circuit. The drains of the both transistors are commonly connected to the gates of N-type transistors having a predetermined threshold voltage, and the gates of the both transistors are commonly provided with the activation signal of the precharge circuit. The supplied activation signal has the potential of the power supply of the semiconductor memory circuit in the standby mode, the ground potential in the operation mode, and the potential of the common power supply line in the standby mode of the N-type transistor connected in parallel to the control circuit. It is characterized by being clamped to a threshold voltage.

According to a seventeenth aspect of the present invention, in the semiconductor memory device according to the seventh aspect, the impedance changing means includes a pull-down transistor and a control circuit for controlling the pull-down transistor, and the control circuit includes: The pull-down transistor is cut off when a corresponding word line is requested to be selected, is controlled to a low impedance state when another word line is requested to be selected, and is controlled to a high impedance state when it is on standby. .

Further, in the invention according to claim 18, in the semiconductor memory device according to claim 17, the pull-down transistor comprises an N-type transistor, the control circuit comprises a logic circuit, and the logic circuit has a corresponding word. A word line selection signal for requesting line selection is input, and a common source line of a P-type transistor forming a sense amplifier is connected as a power source. Any one of the word lines is a common source line of the sense amplifier. The logic circuit is controlled to have a high potential in a selected operation and a low potential in a standby state. The logic circuit inputs a ground potential to the gate electrode of the pull-down transistor when the word line selection signal is input, and does not input the word line selection signal. At times, the potential of the common source line of the sense amplifier is supplied respectively.

In addition, in the invention according to claim 19, in the semiconductor memory device according to claim 18, the logic circuit includes an inverter circuit, and the inverter circuit includes a P-type transistor and an N-type transistor connected in series. The common source line of the sense amplifier is connected to the source electrodes of the P-type transistors, the power source of the semiconductor memory circuit is connected to the source electrodes of the N-type transistors, and the word line selection is performed to the gate electrodes of the both transistors. A signal is input, and the drains of the both transistors are commonly connected to the gate electrode of the pull-down transistor.

[0035]

With the above structure, in the semiconductor memory device according to the present invention as claimed in any one of claims 1 to 3, when one bit line belonging to any of the memory cell blocks is short-circuited with the word line to cause a defect. Is a column selection signal line for selecting the defective bit line, a plurality of bit lines (including defective bit lines) corresponding to the column selection signal line, and a plurality of precharge circuits corresponding to the column selection signal line. And one precharge power supply line as a unit for redundant replacement.

Here, since the redundant replacement unit uses a plurality of pairs of bit lines that can select one column selection signal line as a unit, bit failure (connection failure between memory cell, bit line and word line). The unit of the redundant replacement can be limited to a small area as compared with the case where the entire one memory cell block is redundantly replaced as in the conventional case.

In particular, in the semiconductor memory device according to the second aspect of the invention, each cutting means can be arranged in the peripheral circuit on the side of the cell array having a sufficient arrangement space, so that the arrangement is easy.

Further, in the semiconductor memory device according to the third aspect of the invention, the cutting means is composed of a fuse element, and this fuse element having a small size can be adopted.
This is advantageous for downsizing the semiconductor memory device.

In addition, in the semiconductor memory device according to the present invention as defined in claims 4 and 5, when there is a short circuit between the bit line and the word line, the memory cell among the plurality of transistors forming the sense amplifier is selected. The transistor of the conductivity type opposite to the conductivity type of the transistor is prone to malfunction,
Since the malfunction of the transistor is reliably prevented by the potential supply means, it is possible to reliably prevent the standby current from flowing from the sense amplifier to the ground via the defective bit line and the word line by using the common source line of the sense amplifier as a power source.

Particularly, in the fifth aspect of the invention, among the plurality of transistors forming the sense amplifier, even if the transistor of the conductivity type opposite to the conductivity type of the transistor of the memory cell malfunctions, the memory Since the malfunction of the transistor of the same conductivity type as the transistor of the cell is reliably prevented by the potential supply means, the standby current is further reliably prevented from flowing.

Further, in the semiconductor memory device according to any one of claims 6 to 10 and 17 to 19, the impedance between the word line and the ground is variably adjusted by the impedance changing means, and the standby state is achieved. When (during the precharge operation of the bit line pair), the word line
-Since the impedance between the ground is adjusted to a high value,
The standby current flowing from the defective bit line to the ground via the word line is reduced.

Further, in the semiconductor memory device according to the sixth aspect, the eleventh aspect to the sixteenth aspect of the invention, the bit line is precharged to a predetermined potential during standby (during the bit line precharge operation period). Since the potential of the word line is higher than that during operation and the potential difference between the bit line and the word line is reduced, the standby current flowing from the bit line to the ground via the word line is effectively reduced.

[0043]

Embodiments of the semiconductor memory device of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIGS. 1 to 3 are circuit diagrams in which a semiconductor memory device according to a first embodiment of the present invention is applied to a 16 Mbit DRAM.

FIGS. 1 to 3 are circuit diagrams of one section when a 16 Mbit cell array is divided into two in the row direction and the column direction to make a total of four divisions. The circuit for one partition is further divided into 16 in the column direction. The circuit for one partition when divided into 16 has 512 pairs of normal bit lines in the row direction and a plurality of pairs of bit lines for redundancy relief for bit defects, and 256 normal word lines in the column direction. It has a plurality of redundant relief word lines for bit defects.

In FIGS. 1 to 3, reference numeral 1 is a cell array, and the cell array 1 includes a plurality of pairs of bit lines BL.
, / BL1 ... And a large number of word lines WL1 ...

MB1 to MB16 are a plurality of memory cell blocks formed by dividing the cell array 1 into 16 in the direction in which the word lines WL1 are arranged. SA1 to SA16 are the same number of sense amplifier blocks as the plurality of memory cell blocks. That is, it is arranged laterally on the side where the word lines are lined up in the corresponding memory cell block.

Further, B1, Bn ... Are column replacement units partitioned for every two pairs of bit line pairs of each memory cell block MB1 .. BS1 is a redundancy partitioned into the same size as each column replacement unit B1. It is a substitution unit. Each column replacement unit B1
... and the redundant replacement unit BS1 have the same configuration. The column replacement unit B1 will be described below. In the column replacement unit B1, MC11, MC21 ... Are memory cells, each of which includes a capacitor C and an N-type transistor T.

Y1 ... Yn ... And Ys are a plurality of column selection signal lines shared between the memory cell blocks MB1 .. The column selection signal lines Y1. Are arranged in the extending direction of / BL1 ... And one for each column replacement unit B1, Bn ... and redundant replacement unit BS1.

Further, each of the sense amplifier blocks SA1
... are four bit lines BL1, / BL extending in the column direction
1, BL2, / BL2 is a reference potential (for example, 1 / 2.V
CC) to precharge a plurality of precharge circuits 41
a, an equalize signal line 51, a plurality of sense amplifiers 101a, two common source lines SN11 and SP11 connected to each sense amplifier, and a corresponding column selection signal line Y1 ... Column selection circuits Ysa, Ys
and a.

Therefore, as surrounded by a broken line in FIG. 2, each of the column replacement units B1 ... And the redundant replacement unit BS1 has a plurality of sets (32) extending in the column direction with four bit lines continuous in the column direction as row units. The memory cell block of (set) serves as a replacement unit when the bit line is short-circuited.

In addition, 11a ... 11n ... And 11s
Are precharge power supply lines provided in the same number as the column selection signal lines Y1 ...
Extend in parallel with the column selection signal lines Y1 ...

In FIGS. 1 and 2, 3 is a precharge potential generation circuit (precharge potential supply circuit) for generating the precharge potential of the bit line pair, and 2 is connected to the precharge potential generation circuit 3. The precharge potential supply line 2 is connected to the precharge power supply lines 11a ... 11n ..., 11s. Each of the precharge power supply lines 11a ... 11
, 11s, fuse elements (cutting means) 50a ... 50n near the connection point with the precharge potential supply line 2.
..., 50s are arranged. Each fuse element 50a ...
The size of 50n ..., 50s is 1 μm to 20 μm.

Further, in FIG. 3, reference numeral 70 designates column selection signal lines Y1 ... Yn, Ym ..., Ys corresponding to the received column address.
After replacing the defective replacement unit B1 ... With the redundant replacement unit BS1, if the replacement unit corresponding to the received column address is the redundantly replaced defective column, the received column address is selected. Is a redundancy judgment circuit for converting the address into a redundant column address.

Therefore, in this embodiment, as shown in FIG. 3, for example, the bit line BL1 and the word line WL11.
When a short circuit with (indicated by the resistance component R) occurs,
Fuse element 5 connected to precharge power supply line 11a
Since 0a is cut off, the precharge potential is not supplied from the precharge potential generation circuit 3 to the precharge circuit 41a. Therefore, the defective bit line pair [BL1,
/ BL1] is not precharged, the standby current does not flow to the ground via the defective bit line-word line during the precharge period of the bit line pair (during standby).

In this case, the column recorder 70 receives the redundant column address from the redundancy judgment circuit 71 and receives the column selection signal line Y.
Since the column selection signal line Ys of the redundancy destination is selected instead of selecting 1, the redundancy bit line SBL of the redundancy replacement unit BS1 is selected.
Data is read from and written to the redundant memory cell through 1, / SBL1 or SBL2, / SBL2.

Here, redundant replacement unit BS1 has a total of 32 sense amplifiers 101a, 16 in the extending direction of the bit lines and 2 in the extending direction of the word lines. Therefore,
In this embodiment, the area of the redundant replacement unit is approximately 1 in comparison with the case where the replacement unit is a circuit unit having 512 sense amplifiers in the direction in which the word lines extend in the circuit of the 4 Mbit portion (circuit of FIG. 2). It can be reduced to / 16.

Moreover, since the size of the fuse elements 50a ... Is 1 μm to 20 μm, the fuse elements 50a
.. is provided in the peripheral circuit outside the memory cell array, the size of the DRAM chip having a side length of 1.5 cm is negligible, and the miniaturization of the chip can be favorably ensured. Further, since the fuse elements 50a ... Are arranged on the side of the cell array which has a sufficient space for arrangement, the fuse elements 50a ... Can be easily arranged.

Although only one redundant column is provided in the present embodiment, it goes without saying that a plurality of redundant columns may be provided.

Although the fuse element 50a is used as the cutting means in this embodiment, a switching circuit may be used. In this case, if the precharge power supply line 11s is disconnected from the precharge potential generation circuit 3 so as not to precharge the redundant bit line pair that is not yet subjected to the redundant relief,
Furthermore, low power consumption can be achieved.

In the above embodiment, the redundant replacement unit BS1 is replaced when the bit line-word line is short-circuited. However, if the redundant replacement unit BS1 is replaced even in other defective modes, the area of the redundant replacement unit is reduced and the chip is made smaller. Is possible.

(Embodiment 2) FIG. 4 shows the essential structure of a semiconductor memory device according to a second embodiment of the present invention. The present embodiment is an embodiment in which the defective operation of the sense amplifier is prevented and the standby current caused by the defective bit line-word line is reduced.
The basic structure of the memory cell and the like is the same as that shown in FIGS. 2 and 3, and therefore the illustration and description thereof will be omitted.

In FIG. 4, 101a is a flip-flop type sense amplifier, which is the sense amplifier 101a.
Is a pair of P-channel transistors (first transistors) T that connect a pair of bit lines BL and / BL to each other.
P, TP, and two N-channel transistors (second
Transistor) TN, TN.

Further, SP is a common source line for the two P-channel transistors TP, SN is a common source line for the two N-channel transistors TN,
28 is a control circuit for controlling the potentials of the two common source lines SP and SN.

As can be seen from the precharge operation waveform diagram of the bit line pair shown in FIG. 5, the control circuit 28 is in the precharge operation period of the bit line pair [BL, / BL] (in other words, the sense amplifier is In the inactive state, that is, in the standby state in which all word lines are not selected, the conductivity type (P type) opposite to the conductivity type (N type) of the memory cell transistor (transistor T in FIG. 2). Of the potential VSP of the common source line SP for the first transistor TP of the first transistor TP on the side where the first transistor TP is cut off from the precharge potential (1/2 · VCC) of the bit line (that is, 1).
Potential lower than / 2 · VCC), for example, “L” level (ground potential VSS). The control circuit 28 constitutes a potential supply means 29.

Further, the control circuit 28 sets the potential VSP of the common source line SP for the first transistor TP to "L".
At the same time as the level (ground potential VSS), the second transistor TN cuts off the potential VSN of the other common source line SN from the precharge potential (1/2 · VCC) of the bit line. Side potential (ie 1 /
The potential is higher than 2 · VCC), for example, “H” level (power supply potential VCC). This control circuit 28
Thus, another potential supply means 30 is configured.

Therefore, this embodiment has the following functions and effects.

That is, in this embodiment, the potential VSN of the sense amplifier common source line SN is set to "H" level (VCC) during the precharge operation of the bit line pair (during standby).
At the same time, the potential VSP of the sense amplifier common source line SP is set to "L" level (VSS) to perform the precharge operation of the bit line pair according to the operation waveform shown in FIG.
Both the channel transistors TP and TP and the N channel transistors TN and TN are completely cut off. Therefore, the sense amplifier operation can be completely stopped and the standby current can be eliminated.

In the operation for selecting the word line, the potentials of the common source lines SN and SP of the sense amplifier 101a are the potentials obtained by inverting the potentials during the precharge operation period, but the operating current is greatly increased. There is no need to increase it.

(Embodiment 3) A third embodiment of the present invention will be described. In the second embodiment, the countermeasure for reducing the standby current is taken on the bit line side, but in the present embodiment, the countermeasure is taken on the word line side.

FIG. 6A is a circuit diagram showing a semiconductor memory device according to the third embodiment of the present invention and showing only one memory cell block. In this embodiment, only the configuration for driving the word line is shown, and the divided memory cell block, the plurality of memory cells, the plurality of pairs of bit lines, the plurality of sense amplifiers, and the plurality of precharge circuits are not shown. Since the configuration is the same as that shown in FIGS. 1 to 3, its illustration and description will be omitted.

Each memory cell block (not shown in the figure, but corresponds to the memory cell block MB1 ... In FIG. 2)
.. are connected to word line drive circuits WD11, WD12, .. Word line selection signal lines WS11, WS12 ... And word line signal lines W11, W12 ... Are inputted to the word line drive circuits WD11, WD12.

Each word line drive circuit WD11, WD12 ...
Have the same configuration as each other, only the word line drive circuit WD11 will be described below. Word line drive circuit WD
11 is an N-type transistor TWD11 connected in series
1 and N-type pull-down transistor TWD121,
An inverter IWD11 for signal inversion is provided. The word line signal line W11 is connected to the transistor TWD111, the source of the pull-down transistor TWD121 is connected to the common power supply line (pseudo ground line) VSX, and the word line WL11 is connected to the connection point of the both transistors TWD111 and TWD121. . Word line selection signal line W
S11 is directly connected to the gate of the transistor TWD111, and is also connected to the gate of the pull-down transistor TWD121 via the inverter IWD11. The potential of the word line signal line W11 is the power supply potential VC.
It is a second potential VPP different from C.

In the word line drive circuit WD11,
At the time of requesting selection of the word line WL11 (word line selection signal W
When S11 is at H level), the transistor TWD1
11 is turned on, and the potential of the word line signal line W11 is supplied to the word line WL11. On the other hand, when the word line WL11 is not selected (when the word line selection signal WS11 is at L level)
The pull-down transistor TWD121 is turned on, and the word line WL11 is the common power line (pseudo ground line).
Connected to VSX.

Next, the features of the present invention will be described. The common power supply line VSX is commonly used in each memory cell block. Two N-type transistors T1 and T2 are arranged in parallel between the common power supply line VSX and the ground VSS. The gate of the one transistor T1 is connected to the power supply potential VCC. The other transistor T2
An inverted signal XEQ obtained by inverting the equalize signal (activation signal) EQ of the precharge circuit by the inverter I1 is input to the gate of the.

Equalize signal E of the precharge circuit
As shown in the signal waveform of FIG. 6B, Q is at the “H” level (power supply potential VCC) during the precharge operation period of the bit line pair (that is, during standby), and during other operations. Becomes "L" level (ground potential VSS). Here, "operation time" and "standby time" are expressions for one memory cell block, which means a time when any word line in its own memory cell block is selected. In this case, all the word lines in the memory cell block are not selected.

With the above structure, the transistor T1 is always in the ON state, while the transistor T2 is in the ON state only when the equalizing signal EQ is at the "L" level, that is, during the operation.

With the above configuration, the impedance changing means 31 for changing the impedance between the common power supply line VSX and the ground to a high value is constituted by turning off the transistor T2 during standby. Also, this changing means 3
1 constitutes a current limiting means 32 for limiting the standby current flowing between the common power supply line VSX and the ground.

Therefore, this embodiment has the following actions and effects. That is, conventionally, each word line (word line WL11 ... In FIG. 2, hereinafter, the configuration omitted in the description of this embodiment will be described using the reference numerals in FIGS. 2 and 3) is connected to the pull-down transistor TWD121. Since it is directly connected to the ground potential VSS via
If there is a short between L1 and word line WL11,
During precharge operation of bit line pair (during standby)
A leak current flows to the ground VSS and causes a standby failure.

On the other hand, in the present embodiment, during the precharge operation period of the bit line pair (during standby), the transistor T2 is turned off and only the transistor T1 is turned on. As a result, the common power supply line is turned on. VSX and ground V
Since the impedance between SS becomes high, it is possible to suppress the standby current due to the short circuit between the bit line and the word line.

In the standby mode, since the impedance between the common power supply line VSX and the ground VSS becomes high, the potential of the word lines WL11 ...
If the potential of the word lines WL11 ... Is in the range of 0 to the bit line precharge potential (1/2 · VCC) V, the memory cell transistor is off, and therefore no information leaks from the memory cell. .

On the other hand, one of the word lines (for example, WL1
1) is selected and the transistor T2 is also in the ON state during the period when the corresponding bit line pair is being amplified by the sense amplifier (in operation), so that the impedance between the common power supply line VSX and the ground VSS is low. As a result, the unselected word line (non-selected word line) becomes almost at the ground potential, and the transistor of the corresponding memory cell is surely turned off.

Further, in this embodiment, since the transistor T2 is controlled by the equalizing signal EQ of the precharge circuit in each sense amplifier block and the inverter I1 for signal inversion, a circuit for control signal is newly added. Therefore, it is possible to prevent the DRAM chip area from increasing.

(Modification of Embodiment 3) In the third embodiment, the equalizing signal EQ of the precharge circuit is used and the transistor T2 is controlled by the signal XEQ which is the inverted signal EQ. However, in the modification, Instead of the inversion signal EQ, the potential VSP of the common source line SP of the sense amplifier shown in FIG. 6C is used as it is for the transistor T of FIG.
Input to the gate of 2 to control this transistor T2. The configuration is the same as that of FIG. 6A except for the signal that controls the transistor T2.

This modification has the same effects as those of the third embodiment, and in addition to this, the following effects are newly produced.

Potential V of the common source line SP of the sense amplifier
As shown in FIG. 14, the SP receives the rising edge of the equalize signal EQ of the precharge circuit and changes from the “H” level (eg, the power supply potential VCC) to the reference potential VSA (eg, the precharge reference potential 1/2 of the bit line. VCC) and each sense amplifier circuit becomes inactive, and then the reference potential VSA changes to the “H” level (VCC) in response to the fall of the equalize signal EQ of the precharge circuit. As a result, each sense amplifier circuit becomes active. (Hereinafter, this signal will be referred to as a sense amplifier activation signal SPA.) Here, strictly speaking, the timing at which the non-selected word line starts to be connected to the ground potential at a low impedance is the timing at which the bit line begins to change in amplitude, In other words, it is the timing when the sense amplifier starts its operation, and it is not necessary to connect the non-selected word line to the ground potential with low impedance until then. Therefore, in comparison with the third embodiment in which the impedance is controlled by the inversion signal XEQ of the equalize signal EQ of the precharge circuit, in the present modification, it changes after about 10 ns from the equalize signal EQ. Since the sense amplifier activation signal SPA for
The period in which the non-selected word line has the low impedance is short, and the period during which a large amount of current flows between the bit line and the word line can be further shortened.

(Fourth Embodiment) A fourth embodiment of the present invention will be described below.

FIG. 7A is a circuit diagram showing a semiconductor memory device according to the fourth embodiment of the present invention.

Each word line drive circuit WD11, WD12 ...
Each source S of the pull-down transistor TWD121 ...
.. are connected to the common power supply line VSX, which is the same as the third embodiment shown in FIG. 6A.

The semiconductor memory device of the fourth embodiment shown in FIG. 7A differs from the semiconductor memory device of the third embodiment shown in FIG.
An N-channel transistor T3 is provided between the SS and the common power supply line VSX, and the gate of the transistor T3 is
The point is that the potential VSP of the common source line SP of the P-channel transistor of the sense amplifier (hereinafter, this signal is referred to as a P-sense amplifier control signal) is input.

As shown in FIG. 7B, the P sense amplifier control signal VSP has a reference potential VSA (for example, during the precharge operation period of each bit line pair (during standby)).
(Precharge reference potential of each bit line pair 1/2 VCC)
Therefore, while the bit line pair is being amplified by the sense amplifier, it is at "H" level (for example, the potential VC of the power supply).
C). The impedance changing means 31 'is configured by the above configuration.

Therefore, according to the present embodiment, during the precharge operation period of each bit line pair (during standby), the gate potential of the transistor T3 is the reference potential VS.
Since it is A (1/2 · VCC), it is in a high impedance state, the impedance between the common power supply line VSX and the ground VSS is high impedance, and the bit line −
The standby current due to the short circuit between the word lines can be suppressed to a small level, and the gate potential of the transistor T3 becomes "H" level (VCC) while the bit line pair is being amplified by the sense amplifier (in operation). Therefore, the transistor T3 is in a low impedance state, the impedance between the common power supply line VSX and the ground VSS has a low value, and the non-selected word line is grounded to the VSS.
Can be grounded with low impedance.

Further, also in this embodiment, the potential VS of the common source line SP of the P channel transistor of the sense amplifier is used.
Since the transistor T3 is controlled by P, it is not necessary to newly add a circuit for a control signal, and it is possible to prevent the chip area of the DRAM from increasing.

(Fifth Embodiment) The fifth embodiment of the present invention will be described below.

FIG. 8A is a circuit diagram showing a semiconductor memory device according to the fifth embodiment of the present invention.

Each word line drive circuit WD11, WD12 ...
Are connected to the common power supply line VSX in common in each memory cell block as in the third embodiment of FIG. 6A.

The semiconductor memory device of this embodiment is different from the third embodiment of FIG. 6 in that the common power supply line VSX is the potential VSN of the common source line SN of the sense amplifier (hereinafter referred to as N sense amplifier control signal). ) Is the point connected to.

As shown in FIG. 8B, the N sense amplifier control signal VSN has a reference potential VSA (for example, a precharge voltage for each bit line pair during the precharge operation period (standby)). Charge reference potential 1/2 ・ VC
C), which is at the “L” level (for example, power supply potential VSS) during the period (during operation) during which the bit line pair is being amplified by the sense amplifier.

With the above configuration, during the precharge operation period of each bit line pair (during standby), that is, the word line WL.
When the WLs 11, WL12 ... Are connected to the common power supply line VSX via the pull-down transistors TWD121 ... In the ON state, the potential of the common power supply line VSX is changed to the reference potential VSA.
(1/2 · VCC), the potential changing means 5 is set to the same potential as the precharge potential (1/2 · VCC) of the bit line pair.
Make up one. This potential changing means constitutes a current limiting means 32 'for reducing the potential difference between the shorted bit line-word line and preferably setting it to zero to limit the standby current.

Therefore, in the present embodiment, during the precharge operation period of the bit line pair (during standby), each word line selection signal line WS11, WS12 ... Transistor TW
Since D121 ... is turned on, each word line WL1
1, WL12 ... Are connected to the common power supply line VSX. At this time, the potential of the common power supply line VSX is equal to the reference potential VSA (1
/ 2 · VCC) and has the same potential as the bit line short-circuited to the word line, it is possible to suppress the standby current due to the short circuit between the bit line and the word line.

On the other hand, during the operation period of the sense amplifier (during operation)
Then, since the common power supply line VSX becomes the ground potential VSS,
An unselected word line can be pulled down to the ground potential VSS with low impedance.

Further, in the present invention, since the common source line of the sense amplifier of each sense amplifier block is directly connected to the common power supply line VSX, it is not necessary to newly add a circuit for control signal, and the chip area of the DRAM can be reduced. The increase can be prevented.

(Sixth Embodiment) The sixth embodiment of the present invention will be described below.

FIG. 9A is a circuit diagram showing a semiconductor memory device according to the sixth embodiment of the present invention.

Each word line drive circuit WD11, WD12 ...
The sources S1, S2, ... Of are connected to the common power supply line VSX in common in each memory cell block, which is the same as the third embodiment of FIG. 6A.

The semiconductor memory device of this embodiment is the same as the semiconductor memory device shown in FIG.
9A, the N-type MOS transistor T4 is arranged between the common power supply line VSX and the ground VSS and the N-type M-type transistors connected in series are provided as shown in FIG. 9A.
OS transistor T5 and P-type MOS transistor T6
A control circuit 61 is provided. N connected in series
The type MOS transistor T5 and the P type MOS transistor T6 are connected in parallel with the transistor T4. The drains of the transistors T5 and T6 are the transistors T
4 and the source of the transistor T5 is connected to the common power supply line VSX and the transistor T6.
Source is connected to the power supply VCC. Further, both transistors T5 and T6 connected in series are controlled by the activation signal (equalization signal) EQ of the precharge circuit shown in FIG. Therefore, in the control circuit 61, during the bit line precharge d operation period (during standby), the transistor T5 is turned on to supply the potential of the common power supply line VSX to the gate of the transistor T4, and during operation, the transistor T5 is turned on. T6 is turned on to supply the power supply potential VCC to the gate of the transistor T4. Transistor T4
Has a predetermined threshold voltage VT4.

With the above structure, if the common power supply line VSX becomes higher than the threshold voltage VT4 of the transistor T4 when the equalize signal EQ is at the "H" level (power supply potential VCC) (during standby), the transistor T4 is activated. Is turned on and a current flows from the common power supply line VSX to the ground VSS via the transistor T4, thereby limiting the potential of the common power supply line VSX to the threshold voltage VT4 of the transistor T4. I am configuring. With this clamp circuit 60, the common power supply line VS
A potential changing unit 51 ′ that changes the potential of X is configured.

Now, during the bit line precharge operation period (during standby), each word line drive circuit WD11,
Pull-down transistor TWD121 of WD12 ...
Is turned on and each word line WL11, WL12 ...
Are connected to the common power supply line VSX. At this time, the control circuit 6
Since the first transistor T5 is turned on and the potential of the common power supply line VSX is applied to the gate of the transistor T4, the potential of the common power supply line VSX is clamped to the threshold voltage VT4 of the transistor T4. As a result, even if there is a short circuit between the bit line and the word line, it is possible to suppress the standby current flowing to the ground via the shorted bit line-word line.

On the other hand, during the word line selection operation which is the operation time, the pull-down transistor of each non-selected word line drive circuit is in the ON state, and each non-selected word line is connected to the common power supply line VSX. At this time, in the control circuit 61, N
Since the N-type MOS transistor T5 is turned off and the P-type MOS transistor T6 is turned on, the N-type MOS transistor T5
4 has a gate connected to the power supply potential VC via the transistor T6.
Connected to C. As a result, the N-type MOS transistor T4
Is always on and is in a low impedance state, so that the impedance between the common power supply line VSX and the ground VSS has a low value, and the non-selected word line can be grounded with low impedance.

(Embodiment 7) Hereinafter, a seventh embodiment of the present invention will be described.

FIG. 10 is a circuit diagram showing a semiconductor memory device according to the seventh embodiment of the present invention.

In the figure, WL11 and WL12 are word lines, WD11 and WD12 are word line drive circuits, and IWD11 and IWD12 are inverter circuits (logic circuits). Since each word line drive circuit and the inverter circuit have the same configuration, the internal configuration of the word line drive circuit WD11 and the inverter circuit IWD11 will be described below.

The word line WL11 is a word line drive circuit W.
The word line drive circuit W is connected to the word line signal W11 via the N-type transistor TWD111 of D11.
It is connected to the ground VSS via the N-type pull-down transistor TWD121 of D11. Transistor TWD11
The word line selection signal WS11 is directly input to the first gate electrode. The word line selection signal WS11 becomes "H" level when the selection of its own word line is requested, and becomes "L" level when the selection of its own word line is not requested.

The inverter circuit IWD11 is a control circuit for controlling the pull-down transistor TWD121 and comprises a P-type transistor ITp and an N-type transistor ITn connected in series. The inverter circuit I
The power source of the WD 11 is the potential VSP of the common source line SP for the P-channel transistor of the sense amplifier, and this common source line SP is connected to the source of the P-type transistor ITp. Common source line SP of the sense amplifier path
As shown in FIG. 7B, the potential VSP of the intermediate potential VSP of the intermediate potential VSA (for example, 1/2.
VCC), which is the power supply potential VCC during the selection operation of any word line. The source of the N-type transistor ITn is connected to the ground VSS. Both transistors ITp, I
Tn has a pull-down transistor TWD at its drain
The gate of 121 is connected, and the word line selection signal WS11 is input to the gate.

Therefore, in the inverter circuit IWD11, during the operation in which its own word line is selected, that is, when its own word line selection signal WS11 is at "H" level, the N-type transistor ITn is turned on, The ground potential VSS is output to the gate of the N-type pull-down transistor TWD121, while the P-type transistor ITp is turned on in the non-selected state of its own word line, that is, when the word line selection signal WS11 is at "L" level. Then, the potential VSP of the common source line SP of the sense amplifier is output to the gate of the pull-down transistor TWD121.

Therefore, in the operation in which the self word line is selected, the pull-down transistor TWD121 is completely turned off, the word line WL11 and the ground VSS are completely cut off, and the transistor TWD111 is turned on, and the word line WL11 is turned on. The signal W11 is output to the word line WL11.

On the other hand, when the self word line is not selected, the transistor TWD111 is turned off and the potential VSP of the common source line SP of the sense amplifier is output to the gate of the pull-down transistor TWD121. Here, during the operation in which another word line is selected, the potential VSP of the common source line SP of the sense amplifier becomes the power supply potential VCC, so the N-type pull-down transistor T
While the WD 121 is completely turned on and its word line WL11 is surely set to the ground potential VSS, while the other word lines are not selected, the potential VSP of the common source line SP of the sense amplifier is set to the intermediate potential VSA during standby. (1 /
2 ・ VCC) and N-type pull-down transistor T
Since the WD 121 is in a high impedance state, the standby current flowing from the pull-down transistor TWD 121 to the ground VSS can be limited.

Therefore, the impedance between the word line and the ground potential VSS is changed by the potential VSP of the common source line SP of the sense amplifier between the standby state and the operation in which a word line other than itself is selected. Therefore, during the precharge operation period (during standby), the word line can be grounded with high impedance to limit the standby current to a small level, and at the time of operation when another word line is selected, its own word line is Since it can be grounded with low impedance, the same effect as the third embodiment of the present invention can be obtained.

In the seventh embodiment of the present invention, not only the inverter circuit IWD11 for signal inversion but also NA
When a logic circuit such as an ND circuit or NOR circuit is provided,
Needless to say, the same can be applied to these.

[0120]

As described above, according to the semiconductor memory device of the first to third aspects of the present invention, the same number of precharge power supply lines as the column selection signal lines are provided, and the precharge power supply lines are provided between the word line and the bit line. Since the redundant replacement unit due to the short circuit is a unit of a plurality of pairs of bit lines corresponding to one column selection signal line, it corresponds to the replacement unit when there is a bit defect, and one memory cell Compared to the case where the entire block is redundantly replaced, the unit of redundant replacement is limited to a small area, and the standby current can be reduced without increasing the chip area. Therefore, in a battery-operable semiconductor memory device, It is extremely effective.

Particularly, in the semiconductor memory device according to the second aspect of the present invention, each cutting means is arranged in the peripheral circuit on the side of the cell array having a sufficient arrangement space, so that the arrangement is easy.

Furthermore, in the semiconductor memory device according to the third aspect of the present invention, the cutting means is constituted by the small fuse element, which is advantageous for downsizing the semiconductor memory device.

In addition, in the semiconductor memory device according to the fourth and fifth aspects of the present invention, when there is a short circuit between the bit line and the word line, the memory cell among the plurality of transistors forming the sense amplifier is selected. Since the malfunction of the transistor of the conductivity type opposite to that of the transistor is reliably prevented, it is ensured that the standby current flows from the sense amplifier to the ground via the defective bit line and word line using the common source line of the sense amplifier as the power source. Can be prevented.

Particularly, in the fifth aspect of the invention, among the plurality of transistors forming the sense amplifier, even if the transistor of the conductivity type opposite to the conductivity type of the transistor of the memory cell malfunctions, the memory Since the malfunction of the transistor of the same conductivity type as that of the cell transistor is reliably prevented, the standby current can be more reliably prevented from flowing.

Further, in the semiconductor memory device according to the present invention of claim 6 to claim 10 and claim 17 to claim 19, the impedance between the word line and ground is set to the standby state (precharge operation of the bit line pair). Since it is adjusted to a high value during the period, the standby current flowing from the defective bit line to the ground via the word line can be reduced.

Particularly, in the inventions according to claims 8 to 10 and claims 18 and 19, the existing signal is used to change the impedance between the word line and the ground during standby and during operation. Therefore, it is not necessary to newly add a circuit for the control signal, and the standby current can be reduced while simplifying the circuit configuration.

Further, in the semiconductor memory device according to the sixth aspect, the eleventh aspect to the sixteenth aspect of the invention, the potential of the word line is made higher during standby (during the precharge operation of the bit line) than during operation. Since the potential difference between the bit line and the word line is reduced, the standby current flowing from the bit line to the ground via the word line can be effectively reduced.

In particular, according to the thirteenth and sixteenth aspects of the present invention, since the existing signal is used to reduce the potential difference between the word line and the bit line during standby, it is necessary to newly add a circuit for the control signal. Therefore, the standby current can be reduced while simplifying the circuit configuration.

[Brief description of drawings]

FIG. 1 is a diagram showing an overall configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a main part of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a schematic configuration of a memory cell array according to a first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. .

FIG. 5 is a signal waveform diagram showing a precharge operation of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a word line drive circuit and its control signal in a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a word line drive circuit and its control signal in a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a word line drive circuit and its control signal in a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 9 is a circuit diagram showing a word line drive circuit and its control signal in a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a word line drive circuit in a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 11 is a diagram showing an overall configuration of a conventional semiconductor memory device.

FIG. 12 is a diagram showing a main configuration of a conventional semiconductor memory device.

FIG. 13 is a diagram showing another main configuration of a conventional semiconductor memory device.

FIG. 14 is a signal waveform diagram showing a precharge operation of a conventional example.

[Explanation of symbols]

MB1, MB16 Memory cell block SA1, SA16 Sense amplifier block Y1, Yn, Ys Column selection signal line 11a, 11n, 11s Precharge power supply line 50a, 50n, 50s Fuse element (cutting means) 41a Precharge circuit BS1 Redundant replacement unit MC11 Memory cell BL1, / BL1 bit line SP common source line SN common source line TWD121 pull-down transistor VSX common power supply line T2, T3 T4, T5, T6 transistor ITp P-type transistor ITn N-type transistor IWD11 inverter circuit (logic circuit) (control circuit) ) 1 cell array 2 precharge potential generation circuit (precharge potential supply circuit) 28 control circuit 29 potential supply means 30 other potential supply means 31, 31 'impedance changing means 32, 32 ′ Current limiting means 51, 51 ′ Potential changing means 60 Clamp circuit 61 Control circuit 101a Sense amplifier

Claims (19)

[Claims] 1. A plurality of memory cell blocks, each of which is formed by partitioning a cell array including a plurality of word lines and a plurality of pairs of bit lines intersecting the word lines into a plurality of memory cell blocks in the direction in which the word lines are arranged, and the plurality of memory cell blocks. A plurality of sense amplifier blocks, which are provided in the same number as and on the side where the word lines are arranged on the side of the corresponding memory cell block, and a plurality of column selection signal lines shared between the memory cell blocks, The precharge power supply lines are provided in the same number as the column selection signal lines, and the disconnection unit is arranged in each of the precharge power supply lines. Each sense amplifier block includes a plurality of pairs of bits in a corresponding memory cell block. Each column select signal line includes a plurality of pairs of bit lines of each memory cell block. For each memory cell block, a pair of bit lines are simultaneously selected, and each of the precharge power supply lines has a plurality of pairs of bits selectable by a corresponding column selection signal line. A predetermined potential is supplied to a line precharge circuit, and one column selection signal line, a plurality of pairs of bit lines in each memory cell block corresponding to the column selection signal line, and a plurality of sense amplifier blocks are provided. One precharge circuit and one precharge power supply line as one unit
A semiconductor memory device comprising a redundant replacement unit at the time of bit line short circuit. 2. A precharge potential supply circuit for supplying a precharge potential to each precharge power supply line, wherein each disconnecting means is arranged near a connection point between the precharge potential supply circuit and each precharge power supply line. The semiconductor memory device according to claim 1, wherein 3. The semiconductor memory device according to claim 1, wherein the cutting means is a fuse element. 4. A memory cell including a capacitor and a transistor, a pair of bit lines from which a signal is read from the memory cell, a first transistor having a conductivity type opposite to that of the transistor of the memory cell, and the same transistor. A flip-flop type sense amplifier, which comprises a conductive second transistor and amplifies the signal read to the pair of bit lines, and is connected to the first transistor and the second transistor of the sense amplifier, respectively. A semiconductor memory device having a common source line for supplying a predetermined potential to a corresponding transistor, the first source having a conductivity type opposite to a conductivity type of the transistor of the memory cell among the plurality of common source lines. The common source line connected to the transistor is connected to the power supply of the semiconductor memory device while the sense amplifier is inactive. Position of the 1 /
A semiconductor memory device, comprising: a potential supply means for supplying a potential on a side where the first transistor is cut off rather than a binary potential. 5. A common source line connected to a second transistor of the same conductivity type as the conductivity type of the transistor of the memory cell among the plurality of common source lines, in a period in which the sense amplifier is inactive, 1 of the potential of the power supply of the semiconductor memory device
5. The semiconductor memory device according to claim 4, further comprising another potential supply unit that supplies a potential on the side where the second transistor cuts off with respect to a binary potential. 6. A plurality of memory cells each comprising a capacitor and a transistor, a plurality of word lines each controlling a transistor of the plurality of memory cells, and a plurality of memory cells stored in the capacitors of the plurality of memory cells. A plurality of pairs of bit lines from which information is read, a plurality of sense amplifiers that respectively amplify the information read to the plurality of pairs of bit lines, and the same number of word lines as the plurality of word lines are provided. And a precharge circuit that precharges the plurality of pairs of bit lines to a predetermined potential during standby when all the word lines are not selected, and In standby mode, current limiting means is provided to limit the current that flows from each word line to the ground via the pull-down transistor. A semiconductor memory device provided with. 7. The current limiting means is arranged in a common power supply line to which the source of each pull-down transistor is connected, and a path for grounding the common power supply line. 7. The semiconductor memory device according to claim 6, further comprising impedance changing means for changing the selected operation time and the standby time to make the impedance higher than that during the operation. 8. The impedance changing means includes a transistor arranged in a path for grounding the common power supply line, the transistor being controlled based on an activation signal of a precharge circuit, and an activation signal of the precharge circuit. 8. The semiconductor memory device according to claim 7, wherein the transistor has a different potential between a standby state and an operating state, and the transistor has a higher impedance state in the standby state than in the operating state. 9. The impedance changing means includes a transistor arranged in a path for grounding the common power supply line, the transistor being controlled by an activation signal of a sense amplifier, and the activation signal of the sense amplifier is in a standby state. 8. The semiconductor memory device according to claim 7, wherein the electric potential is different between when operating and when operating, and the transistor has a higher impedance state during standby than when operating. 10. The transistor is an N-type transistor, the activation signal of the sense amplifier is a potential of a common source line of a P-type transistor forming the sense amplifier, and the common source line of the P-type transistor is in a standby state. 10. The semiconductor memory device according to claim 9, wherein the potential of the semiconductor memory circuit is half the potential of the power source, and the potential of the power source is in operation. 11. The current limiting means changes a common power supply line to which a source of each pull-down transistor is connected and a potential of the common power supply line in a standby state and an operation in which one of the word lines is selected, 7. The semiconductor memory device according to claim 6, further comprising potential changing means for increasing the potential in the standby state as compared with that in the operating state. 12. The potential changing means, when in standby,
The semiconductor memory device according to claim 11, wherein the potential of the common power supply line is set to a potential equal to the precharge potential of the bit line. 13. The potential changing means is a common source line for driving an N-type transistor forming a sense amplifier, the common source line being connected to a common power supply line, and precharging the bit line in standby. 13. The semiconductor memory device according to claim 12, wherein the semiconductor memory device is controlled to a potential and is controlled to a ground potential during operation. 14. The semiconductor memory device according to claim 11, wherein the potential changing means is composed of a clamp circuit that clamps the potential of the common power supply line to a higher level during standby than during operation. 15. The clamp circuit supplies an electric potential of the common power supply line to an N-type transistor having a predetermined threshold voltage, which is arranged between the common power supply line and the ground, and a gate electrode of the transistor during standby. 15. The semiconductor memory device according to claim 14, further comprising a control circuit that supplies a potential of a power source of the semiconductor memory circuit during operation. 16. The control circuit comprises an N-type transistor and a P-type transistor connected in series, the source of the N-type transistor being a common power supply line, and the P-type transistor being the P-type transistor.
The sources of the N-type transistors are connected to the power supplies of the semiconductor memory circuits, the drains of the two transistors are commonly connected to the gates of N-type transistors having a predetermined threshold voltage, and the gates of the two transistors are commonly connected. Then, the activation signal of the precharge circuit is supplied, and the activation signal becomes the potential of the power supply of the semiconductor memory circuit in the standby mode, the ground potential in the operation mode, and the potential of the common power line to the control circuit in the standby mode. 16. The semiconductor memory device according to claim 15, wherein the N-type transistors connected in parallel are clamped to a predetermined threshold voltage. 17. The impedance changing means comprises a pull-down transistor and a control circuit for controlling the pull-down transistor, the control circuit cuts off the pull-down transistor when a request for selecting a corresponding word line is made, and another 8. The semiconductor memory device according to claim 7, wherein a low impedance state is controlled when a word line is selected, and a high impedance state is controlled during standby. 18. The pull-down transistor is composed of an N-type transistor, the control circuit is composed of a logic circuit, and a word line selection signal for requesting selection of a corresponding word line is inputted to the logic circuit, and a power supply is provided. A common source line of a P-type transistor that constitutes a sense amplifier is connected, and the common source line of the sense amplifier is controlled to a high potential during an operation in which any word line is selected, and is controlled to a low potential during standby. The circuit supplies to the gate electrode of the pull-down transistor a ground potential when the word line selection signal is input and a common source line potential of the sense amplifier when the word line selection signal is not input. 18. The semiconductor memory device according to claim 17, which is characterized in that. 19. The logic circuit comprises an inverter circuit, the inverter circuit comprises a P-type transistor and an N-type transistor connected in series, and a common source line of a sense amplifier is connected to a source electrode of the P-type transistor. A source of the semiconductor memory circuit is connected to the source electrode of the N-type transistor, a word line selection signal is input to the gate electrodes of both transistors, and the drains of both transistors are commonly connected to the gate electrode of the pull-down transistor. 19. The semiconductor memory device according to claim 18, wherein the semiconductor memory device is connected.