JPH07334421A - Cache memory controller - Google Patents

Abstract

PURPOSE:To avoid access competition between an address array and a TLB by a small physical quantity in pipeline processing. CONSTITUTION:A stage control part 100 for managing the stage control of a pipeline equally sets up the stages of respective requests for accessing the address array 2 and the TLB 3. When a storage request is generated, the array 2 and the TLB 3 are referred to on a stage C e.g. and request information, a logical address, an address array reference result, and a real address found by the TLB 3 are registered in one of plural storage fetching queues 9. Then, a cache memory 1 is accessed based upon the registered contents of the queue 9 on a stage F, e.g. and data are written. Also, at the time of generating a fetch request, the array 2 and the TLB 3 are referred to on the stage C, and when a hit is detected, data are read out from the memory 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory control device in an information processing device.

[0002]

2. Description of the Related Art Generally, an information processing apparatus is provided with a small capacity, high speed access cache memory (buffer memory) for high speed memory access. This cache memory is divided into blocks of a fixed size or an arbitrary size, and holds a part of the data in the main storage device. There is an address array corresponding to this cache memory, and the real address on the main memory of the data held by the block of the cache memory is registered.

Further, the data processing device adopting the virtual address system is provided with an address translation buffer (hereinafter referred to as TLB) which holds a translation pair of a logical address and a real address for the logical address.

When there is an access request by a logical address, the cache memory control unit obtains a real address from the TLB and accesses the address array to detect whether or not the main memory address of the corresponding data block is registered and register it. If so, the cache memory is accessed.

On the other hand, one of the methods for improving the processing speed of the data processing apparatus by the control method is the pipeline method. The pipeline method realizes parallel processing of a plurality of instructions by dividing a processing sequence of instructions into a plurality of stages and overlapping each stage in each instruction for processing. When the cache memory is accessed by a store request and a fetch request, the stages of accessing the cache memory are the same in the pipeline operation of the store and fetch requests, in other words, the stages of referring to the address array and TLB of this cache memory are the same. If two or more instructions are not decoded in one cycle, the store request and the fetch request do not simultaneously access the cache memory, that is, the address array at a certain time. However, if the stages for accessing the cache memory of the store request and the fetch request are different, the two requests may simultaneously access the cache memory, the address array, and the TLB at a certain time.

An example of this case is shown in FIG. That is,
Address array of fetch request, TLB reference to C
At stage, address array of store request, TL
Assuming that the B reference is performed in the F stage, as shown in FIG. 3, the reference of the address array and the TLB conflict between the preceding store request and the subsequent fetch request in the pipeline process.

Thus, the cache memory for the store request and the fetch request, the address array, the T
When the LB access conflict occurs, either access must be made to wait. On the other hand, conventionally, as shown in, for example, Japanese Patent Laid-Open No. 59-048879, by having a dedicated address array for store requests and fetch requests, and a TLB, an address array for store requests and fetch requests is provided. , T
Some avoid LB competition.

[0008]

In the above-mentioned prior art, since the dedicated address array and TLB for the store request and the fetch request are provided, the address array of the store request and the fetch request, the TLB.
However, there is a problem in that the quantity increases.

An object of the present invention is to provide a dedicated address array for store requests and fetch requests,
An object of the present invention is to provide a cache memory control device capable of avoiding access conflict of an address array.

[0010]

According to the present invention, when a memory request occurs, several queues (hereinafter referred to as a store fetch queue) that register the address of the request, the reference result of the address array, and the information indicating the attribute of the request. Is provided, and the cache memory is accessed based on the information registered in the queue in accordance with the actual cache memory access stage of the request.

[0011]

With respect to all the requests that refer to the address array for accessing the cache memory, the address array reference stage is adapted to the one performed at the earliest pipeline stage. For example, in a store request and a fetch request, the address array reference stage of the fetch request is generally faster, so the address array reference stage of the store request is also adjusted to this stage. Then, when a store request occurs, information such as the address of the store request and the address array reference result is registered in the store fetch queue, and the cache memory is based on the information of the queue according to the cache memory access stage of the original store request. To access. As a result, access conflicts of the address array such as a store request and a fetch request can be avoided, and the cache memory such as the store request can be accessed several stages after the address array reference.

Further, the store fetch queue need only have at most several faces, and compared with the case where a dedicated address array for store requests and fetch requests, TLB, etc. are provided, the address of store requests and fetch requests, etc. can be reduced with a smaller quantity. It is possible to avoid access conflict between the array and TLB.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 1 is a cache memory that holds a part of the data blocks of the main memory, 2 is an address array that registers the real addresses of the data blocks held by the cache memory in the main memory, and 3 is a logical An address translation buffer (TLB) 4 which holds a translation pair of an address and a real address for the address is a hit detection circuit of the cache memory 1. Below the cache memory 1, there is a two-level cache memory (intermediate buffer) or main storage device that refers by physical address, but it is omitted in FIG.

5 is a register for holding request information,
A register 6 generally holds a request logical address and exceptionally holds a block purge address.
Reference numeral 7 is an address register of the cache memory 1, and 8 is a store data register of the cache memory.

Reference numeral 9 is a store fetch queue of n-side (n is an arbitrary integer of 2 or more), and the address array 2 and TBL
The reference result of 3 and the like are retained. Reference numeral 10 is a comparison circuit for comparing the enqueue logical address in the store fetch queue 9 with the request logical address of the register 6. Reference numeral 11 denotes a selector / adder circuit for selecting a logical address or a real address in the store fetch queue 9, and for performing address addition when the access of the store request crosses the write unit of the cache memory. is there. Reference numeral 12 is a selector for selecting either the output logical address of the selector / adder circuit 11 or the request logical address, and 13 is a selector for selecting either the request logical address or the block purge address.

A stage control unit 100 controls the stage of pipeline processing. The operation timing of each unit in FIG. 1 is controlled by the pipeline stage control signal of the stage control unit 100.

The details of the contents of the store fetch queue 9 are described in FIG. That is, in the store fetch queue 9, the logical address 101 of the store request for accessing the cache memory 1, the real address 102 obtained by referring to the TLB 3, the reference result of the address array 2, that is, the detection result 103 of the hit detection circuit 4, and the request information ( In this embodiment, the store request) 104 and the valid bit 105 of the store fetch queue are held.

In this embodiment, the basic pipeline stage progresses in the order of A → B → C → D → E → F, the fetch request reads the data of the cache memory 1 in the C stage, and the store request F. It is assumed that data is written in the cache memory 1 at the stage. To access the cache memory 1, the register 6
Request logical address of address array 2, TLB
3 should be referred to, but this address array 2
And the reference stage of TLB3 for both fetch requests and store requests (generally address array,
Suppose that it is performed in the C stage (for all requests that refer to TLB). An example of pipeline processing of this embodiment is shown in FIG.
Shown in. The operation of FIG. 1 will be described below with reference to FIG.

The preceding store request is set in the register 5 and 6 of request information and request address (request logical address) in stage B, and in stage C the address array 2 is set by the logical address of register 6.
After referring to TLB3, the logical address of this store request, request information, the real address obtained by referring to TLB3, and the address array reference result of the hit detection circuit 4 are registered in one of the n-side store fetch queues 9. After that, in the F stage, the preceding store request shows that the memory array accessed by the preceding store request exists in the block in the cache memory in the address array reference result (H) 103 of the registered contents of the store fetch queue 9. If it is indicated (for example, H = 1), the logical address (LA) 101 of the contents registered in the store fetch queue is set to the selector / adder circuit 11
And the cache memory 1 is accessed by setting it in the register 7 via the selector 12.
The data of the register 8 is written in. In addition, the address array reference result (H) 10 of the contents registered in the store fetch queue
3 shows that the memory area accessed by the store request does not exist in the block in the cache memory 1 (for example, H = 0), or the cache memory 1 uses the store-through method. If it is present, the selector / adder circuit 1 is added to the lower memory device (main memory device or 2-level cache memory device).
1 is the real address (P
A) 102 and request information (C) 104 are transmitted.

Subsequent fetch request, but
Request information and request address (request logical address) registers 5 and 6 are set up to stage B, respectively, and address array 2 and TLB 3 are set at stage C.
Refer to. When the data is present in the cache memory 1, that is, when the hit detection circuit 4 detects a hit (H = 1), the request address is set in the register 7 via the selector 12 at the C stage. To access the cache memory 1 and read data from the cache memory 1. If the data does not exist in the cache memory 1, the data is read from the main storage device or the two-level cache memory. The operation of this fetch request is the same as the conventional one.

In this embodiment, as shown in FIG. 4, the address array of the store request whose reference stage of the cache memory is late, and the TLB reference is set to the same C stage as the fetch request, so that the addresses of the fetch request and the store request are Array and TLB reference conflicts can be avoided.

Next, the guarantee of the order of memory access in the event of a data access conflict will be described. Among these data access conflicts, the data conflict between the preceding store request and the subsequent operand fetch request is OSC.
(Operand store conflict), the data conflict between the preceding store request and the subsequent instruction fetch request is P
It is called SC (Program Store Conflict).

In FIG. 4, it is assumed that the subsequent fetch request refers to the address array 2 and TLB 3 at the C stage. At this time, in order to detect whether there is a conflict between the preceding store request and data access,
The comparison circuit 10 compares the fet request logical address of the register 6 with the registered content of the store fetch queue 9. If there is a data access conflict between the preceding store request and the subsequent fetch request, the subsequent fetch is performed until the preceding store request finishes writing the data in the cache memory 1 (until the end of T5 cycle in FIG. 4). Suppress the request. As a result, the order guarantee of memory access is maintained. If the data access conflict with the preceding store request does not occur and the data exists in the cache memory 1, the data is read from the cache memory 1 in the C stage (T3 cycle) for the fetch request. Become.

Next, in the multiprocessor configuration, while the store request refers to the address array 2 and the TLB 3 and then writes to the cache memory 1, the instruction to the own instruction processing device generated by the main memory access from another instruction processing device is sent. A case where a cache memory block purge request occurs will be described. At this time, if the store request and the purge area of the cache memory 1 are the same, if this cache memory purge request is made before writing the cache memory of the store request, the write area to the cache memory registered in the store fetch queue 9 becomes It no longer exists in the cache memory.
Therefore, in the store request, data is written even though the memory area to be written does not exist in the cache memory 1, causing improper data writing and disappearance of written data. Therefore, the comparison circuit 10 compares the purge request address of the cache memory, which is set in the register 6 via the selector 13, with the store request in the store fetch queue 9 which is not yet written in the cache memory to access the data. When a conflict is detected, the address array reference result (H) 103 of the corresponding registered contents of the store fetch queue 9 is changed to a state that does not exist in the cache memory 1 (for example, H = 0). As a result, it is possible to prevent improper writing to the cache memory.

In this way, the store fetch queue 9 is
In addition to avoiding access conflict between the store request and the fetch request in the address array 2 and the TLB 3, subsequent fetch requests and other instructions are executed after the store request information is registered until the write processing to the cache memory 1 is completed. By detecting data conflicts with all cache memory accesses including cache memory purge from the processing device, it is possible to guarantee data matching.

Next, when the access of the store request crosses the write unit of the cache memory 1 and the write area of the store request is within the block unit of the cache memory 1 and within the page, the cache memory 1 is accessed. The case where it is necessary to supply two accesses, that is, two addresses for each write unit will be described. In this embodiment, the selector / adder circuit 11 adds the address of each write unit to the address (logical address (LA) 101) registered in the store fetch queue 9 by the write unit of the cache memory 1. , The address for each write unit can be supplied to the cache memory 1 via the selector 12 and the register 7 without referring to the address array 2 twice.

As described above, in the embodiment, it is assumed that the cache memory is referred to by the logical address on the assumption that the data processing device adopts the virtual address method. , And the TLB may not be present. That is, TLB
Even when there is no, there is a possible access conflict in the address array between the store request and the fetch request. In the present invention, by having the store fetch queue, access conflict of this address array can be avoided.

In the embodiment, the address array of the store request and the fet request and the access conflict of the TLB are assumed, and the address of the store request, the reference result of the address array, etc. are registered in the store fetch queue. The occurrence of access conflict between the address array and the TLB is not limited to the store request and the fetch request. Therefore, registration in the store fetch queue is generally performed for a desired request based on the type of request, the state of pipeline stage control (for example, waiting occurrence, etc.).

[0030]

As described above, according to the present invention,
Contention by address array reference such as a store request and a fetch request can be achieved by providing several queues with a small physical quantity without providing a dedicated address array for store requests and fetch requests. This queue also stacks the information of the request until the access to the cache memory is completed, so it is possible to detect the conflict between the preceding request and the subsequent request or the request from another instruction processor. It is possible to guarantee the agreement.

[Brief description of drawings]

FIG. 1 is a block diagram of a cache memory control device showing an embodiment of the present invention.

FIG. 2 is a diagram showing registered contents of a store fetch queue in the embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation example of conventional pipeline processing.

FIG. 4 is a diagram showing an operation example of pipeline processing in the present invention.

[Explanation of symbols]

 1 cache memory 2 address array 3 address conversion buffer 4 hit detection circuit 5, 6, 7, 8 register 9 store fetch queue 100 stage control unit

Claims (1)

[Claims] 1. A cache memory for holding a partial data block of a main memory device, and an address array for registering an address of the main memory device of the data block held in the cache memory are provided. If so, the address is referred to, and if the corresponding address is registered, the cache memory controller that accesses the cache memory registers the address of the memory request, the address array reference result of the request, and information indicating the attribute of the request. A cache memory control device comprising queuing means, wherein the cache memory is accessed based on information registered in the queuing means in accordance with a cache memory access stage of a memory request.