JPH07333652A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To decrease shorting defects between gates and drains and between the gates and pixel electrodes by arranging silicon layers and gate insulating films separately from the silicon layers constituting holding capacitors and arranging these layers and films so as to bring the layers and films into contact with an insulating substrate. CONSTITUTION:The gate electrodes 2 are arranged and formed in prescribed patterns on a glass substrate 1. In succession, the gate insulating film 3, amorphous silicon layer 4 and high-concn. n type silicon layer 5 are formed and are then etched at the same photoresist patterns. At this time, the parts to form the TFTs, the lower layers of the signal wirings 6 and patterns (s) 3, 4 to cover the gate electrodes 2 separately from the patterns are arranged and formed. In succession, the source and drain electrodes 6, 6' and the signal lines 6 and further, the pixel electrodes 6' are arranged in the prescribed patterns. Finally, the high-concn. (n) type silicon layers 5 right above the channels are removed and a protective film 7 is formed over the entire surface in order to form the source drain regions. As a result, the exposed parts of the gate electrodes 2 are extremely decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a liquid crystal display device having a thin film transistor as a switching element, and more particularly, to relieving a disconnection of a signal wiring or a gate / drain short circuit defect and a gate / drain or a gate / drain.
The present invention relates to a structure of a liquid crystal display device which is effective in reducing short circuit defects between pixel electrodes.

[0002]

2. Description of the Related Art A liquid crystal display device of an active matrix type (hereinafter abbreviated as TFT-LCD) having a thin film transistor (hereinafter abbreviated as TFT) as a switching element has a feature of thinness, light weight and low power consumption, and C
It is regarded as a favorite of flat panel displays because it can achieve high image quality comparable to RT. TFT-LCD
One of the problems is to simplify the process, improve the manufacturing throughput, and realize the cost reduction of the TFT-LCD panel.

The most effective means of simplifying the process is to reduce the photo process. Photo process cleaning,
Many steps such as resist coating, exposure, and development are necessary, and the number of steps can be significantly reduced by reducing one photoprocess step. One of the means for reducing the photo process is a device structure and a manufacturing method described in JP-A-62-32651. FIG. 7 shows a conventional planar structure, and FIG. 8 shows a sectional structure taken along the line AA 'in FIG. A gate electrode, a gate wiring (hereinafter referred to as a scanning wiring), and a pixel electrode are formed on a glass substrate, and a semiconductor layer is formed in the same plane pattern on the gate electrode via an insulating layer. A source electrode and a drain electrode are provided at both ends of the semiconductor layer, the drain electrode is connected to a drain wiring (hereinafter, signal wiring), and the source electrode is connected to a pixel electrode. As described above, the insulating layer and the semiconductor layer are simultaneously patterned in the same pattern to form the insulating layer to be the gate insulating film of the TFT and the TF.
By forming a semiconductor layer to be a T channel region, one photo process is reduced.

[0004]

However, in the prior art, since the insulating layer and the semiconductor layer are processed in the same pattern,
The scanning wiring is exposed except at the TFT formation location and the gate / drain intersection. Therefore, if etching residue occurs when processing the source / drain electrodes and signal wiring,
A gate / drain short circuit defect (hereinafter abbreviated as G / D short circuit) is likely to occur. Further, when the pixel electrode is formed, since the scanning wiring is exposed, a short circuit defect between the gate and the pixel electrode due to the etching residue is likely to occur as well as between the gate and the drain.

Another problem of the prior art is that there is no route for forming a repair wiring in the case of disconnection of signal wiring (hereinafter abbreviated as D disconnection) or G / D short. Line defects are formed by forming a repair wiring so as to bypass the occurrence point in the case of D disconnection, and to cut off the signal wiring on both sides of the shorting point in the case of G / D short circuit and bypass it. It can be a point defect. However, in the conventional technique, since the scanning wiring is exposed, there is no place to form the repair wiring, and the line defect cannot be repaired.

As described above, the conventional techniques have the problems that short-circuit defects increase and line defects cannot be repaired.

The present invention is intended to improve such problems, and one of the objects thereof is to reduce G / D shorts and gate / pixel electrode shorts and improve the yield of liquid crystal display devices.

Another object of the present invention is to provide a path for forming a repair wiring and repair a line defect in consideration of the occurrence of a D disconnection or a G / D short circuit.

[0009]

In order to achieve the above object, in the present invention, a silicon layer and a gate insulating film are arranged on a scanning wiring without being directly laminated with a signal wiring and a source / drain electrode, and The gate insulating film is arranged so as to be in contact with the insulating substrate. Further, at this time, preferably, the silicon layer and the gate insulating film are made larger than the width of the scanning wiring. By the above means, the silicon wiring and the gate insulating film cover the scanning wiring in a floating state. In addition, the silicon layer and the gate insulating film forming the TFT, and the silicon layer and the gate insulating film existing under the signal wiring are arranged apart from each other by the minimum processing dimension value in the process, so that the scanning wiring The exposed area can be minimized.

Another means for achieving the above object is to directly stack a silicon layer and a gate insulating film on signal wirings and source / drain electrodes when a storage capacitor is arranged in each pixel of a liquid crystal display device. Without being disposed on the scanning wiring, the silicon layer and the gate insulating film are separated from the silicon layer forming the storage capacitor, and the gate insulating film is in contact with the insulating substrate. Further, at this time, preferably, the silicon layer and the gate insulating film are made larger than the width of the scanning wiring. Further, it is desirable that the distance between adjacent silicon layer patterns is set to the minimum processing dimension in the process as in the first means.

In the above means, an insulating substrate is described, but
This is in addition to glass and plastic substrates, for example,
It also includes a glass substrate on which SOG (Spin On Glass) is formed.

[0012]

According to the first means, even when the silicon layer and the gate insulating film are processed in the same photo process step, the exposed portion of the gate wiring can be remarkably reduced, and the gate wiring can be formed at the time of patterning the pixel electrode. Since it can be covered as much as possible, the following effects can be obtained.

The first effect is that since a silicon layer and a gate insulating film are newly arranged on the scan wiring which has been exposed in the past, the area where a G / D short circuit may occur can be significantly reduced. As a result, in the case of manufacturing a liquid crystal display device, even if the electrode material remains at the originally etched off portion due to poor development or etching during processing of the source / drain electrodes, G / D-short yield is improved (reduction of line defects).

The second effect is that, like the first effect, the scanning wiring can be covered with the silicon layer and the gate insulating film as much as possible at the time of patterning the pixel electrode, so that a short circuit can occur between the scanning wiring and the pixel electrode. It is possible to significantly reduce the area having properties. Therefore, when a liquid crystal display device is manufactured, the short-circuit yield between the gate and the pixel electrode is improved (point defects are reduced).

A third effect is that when the source / drain electrodes and the silicon layer below the signal line and the silicon layer formed separately from the gate insulating film are made larger than the width of the scanning line, the D disconnection occurs. On the silicon layer and the gate insulating film so that the D wiring is bypassed and the signal wiring is cut off on both sides of the location where the G / D short circuit occurs and the wiring is bypassed. The line defect due to the D disconnection and the G / D short circuit can be turned into a point defect by forming the film.

Further, in the case of a liquid crystal display device having a storage capacitor in each pixel, the silicon layer and the gate insulating film formed separately from the silicon layer and the gate insulating film for forming the storage capacitor are used as the second means. By arranging as shown in
The same effect as the first means can be obtained.

[0017]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIGS. 1, 2 and 3 are explanatory views showing an embodiment of the present invention. FIG. 1 is a plan view of a layout of a pixel portion of an active matrix substrate which constitutes a liquid crystal display device. 3 and 4 are sectional views taken along the lines AA 'and BB' in FIG. FIG. 2 shows a layered structure on the gate wiring, and FIG. 3 shows a cross-sectional structure of a TFT serving as a switching element. The structure and manufacturing procedure of the embodiment are shown below.

In FIGS. 1, 2 and 3, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an amorphous silicon layer, and 5 is an ohmic contact layer.
Type silicon layer, 6 and 6'are drain electrodes, signal wiring,
A second conductive film 7 serving as a source electrode and a pixel electrode is a protective film. Here, regarding the second conductive film, for example,
There is no problem even if the pixel electrode and the source / drain electrodes are made of different conductive films. Further, at that time, the second conductive film forming the source / drain electrodes may have a structure in which a plurality of kinds of conductive films are laminated without any problem.

The gate electrode 2 is arranged and formed on the glass substrate 1 in a predetermined pattern. For example, a Cr film having a film thickness of 120 nm is formed by a sputtering method and processed by a photoetching process. Ta, Mo, A instead of Cr film
A conductive film such as l, Ti, or ITO, a laminated film of conductive films, or an alloy thereof may be used. The gate electrode 2 is a TFT
It works to supply voltage to turn on and off.

Subsequently, after forming the gate insulating film 3, the amorphous silicon layer 4, and the high-concentration n-type silicon layer 5, etching processing is performed with the same photoresist pattern. At this time, as shown in FIG. 1, the patterns (S) 3 and 4 are arranged and formed so as to cover the portion where the TFT is formed, the lower layer of the signal wiring 6, and the gate electrode 2 separately from the pattern. At this time, as the gate insulating film 3, a silicon nitride film (SiN), a silicon oxide film (SiO), a laminated film of both, or a laminated film of an anodic oxide film of a gate electrode material and SiN, SiO is used. In this embodiment, the gate insulating film 3, the amorphous silicon 4, and the high concentration n are formed on the entire lower layer of the signal wiring 6.
Although the type silicon layer 5 is arranged, it may be arranged only at the intersection of the gate and the drain. The pattern of the gate insulating film 3 and the silicon layer 4 in the lower layer (gate / drain intersection) of the TFT forming portion and the signal wiring 6 and the gate insulating film and the silicon layer formed so as to cover the gate wiring separately from the pattern ( S) Regarding the spacing between the patterns 3 and 4, the smaller the spacing, the greater the effect, and preferably the minimum processing size in the process is adopted. Further, regarding the processed shapes of the silicon layer and the gate insulating film, the end portions can be forward taper processed by dry etching using SF ₆ based gas.

Subsequently, the source / drain electrodes 6 and 6 ', the signal wiring 6, and further the pixel electrode 6'are formed in a predetermined pattern. In this embodiment, ITO is formed into a film having a thickness of 280 nm by a sputtering method and processed by a photoetching process. At this time, the source / drain electrodes 6, 6 '
The signal line 6 and the pixel electrode 6'may be made of different materials. For example, the source / drain electrodes and the signal wiring may be made of a laminated film of Mo and Al, and the pixel electrodes may be made of ITO. The reason is,
This is because when the same material as the scanning wiring is used, the gate material also disappears when the source / drain is etched. Although the pixel electrode side is used as the source in this embodiment, this is determined by the polarity of the bias potential applied between the source and drain electrodes, and here the source and drain are not particularly distinguished.

Finally, in order to form the source / drain regions, the high-concentration n-type silicon layer directly above the channel is removed, and the protective film 7 is formed on the entire surface. The protective film on the terminal portion is selectively removed by a photoetching process. The protective film uses, for example, SiN.

With the structure of this embodiment, the exposed portion of the gate electrode 2 can be significantly reduced even when the silicon layer and the gate insulating film are etched by the same resist. On the other hand, there is also a process of covering the entire gate electrode 2 with a gate insulating film, but this requires a photo process for forming a TFT and a photo process for removing the gate insulating film on the gate terminal. The number of steps increases.

The patterns (S) 3 and 4 of the silicon layer and the gate insulating film newly arranged on the gate electrode 2 must be separated from the silicon layer forming the TFT and the silicon layer arranged below the signal wiring. is there. If either of them is connected, the scanning wiring capacitance or the signal wiring capacitance increases, and the desired image quality cannot be obtained. As a means for avoiding this, it is conceivable to lower the wiring resistance, but if the film thickness is made thicker, there is a possibility that a step difference becomes large and a breakdown voltage defect may occur, and if the wiring width is widened, there is a problem that the aperture ratio is lowered.

The silicon layer and the gate insulating films (S) 3 and 4 arranged on the gate electrode 2 separately from the TFT portion and the silicon layer under the signal wiring are made larger than the scanning wiring width. Accordingly, even if the pixel electrode material remains in a region overlapping with the gate electrode 2 due to defective etching, a short circuit between the gate and the pixel electrode can be prevented. As a result, point defects in the liquid crystal display device can be reduced. Further, even when pattern defects occur due to etching defects in the signal wiring 6 and the source / drain electrodes 6 and 6 ′, the silicon layers and the gate insulating films (S) 3 and 4 which are separately arranged.
If left over, it will not be a G / D short. Therefore,
The frequency of occurrence of G / D shorts is also reduced, and the yield is improved.

Next, an embodiment of a liquid crystal display device in which each pixel has a storage capacitor will be described. FIG. 4 shows a plan view of the pixel layout of this embodiment. Each component such as a scanning line is the same as that in FIG. TFTs and storage capacitors (C) 3 and 4 are formed on the scanning lines, and a silicon layer and gate insulating film patterns (S) 3 and 4 are arranged separately from the TFTs. The exposed portion of the scanning wiring can be minimized by setting the interval between the silicon layer and the gate insulating film pattern, which are separately formed, to the minimum processing dimension in the process.

The manufacturing procedure is the same as that of the above-mentioned embodiment, although it has a storage capacitor.

By arranging a new silicon layer and gate insulating films (S) 3 and 4 separated from other silicon layers, even if an etching residue of the source / drain electrode material or the pixel electrode material occurs, G / It is possible to reduce the D short circuit and the gate / pixel electrode short circuit. Here, a case where a short circuit occurs and a case where the short circuit can be avoided by this structure will be shown. If this structure cannot be avoided, a- in FIG.
This is the case where etching residues occur in a ', bb', and cc '. However, d-d ', e-e', f in FIG.
If an etching residue occurs at -f ', a short circuit failure does not occur. As described above, by arranging the silicon layer and the gate insulating films (S) 3 and 4 newly, it is possible to make some places which are conventionally short-circuited defective.

FIG. 5 shows the T shown in FIGS. 1, 2 and 3.
FIG. 3 is a cross-sectional view showing an example of the configuration of a liquid crystal display device incorporating an FT substrate, showing one pixel forming portion in the above-described configuration. In FIG. 5, 8 is the first alignment film, and 9 is
Is a second alignment film, 10 is a counter substrate ITO, 11 is a color filter element, 12 is a light-shielding black matrix, 1
3 is a counter substrate, 14 is a first polarizing plate, 15 is a second polarizing plate, and 16 is a liquid crystal.

The glass substrate 1 serving as an active matrix substrate has one surface on which the TF shown in FIG. 1 is formed.
T and pixel electrodes are arranged and formed, a first alignment film 8 is formed and formed on them, and the first polarizing plate 1 is formed on the other surface.
4 is attached. Further, the counter substrate 13 has, on one surface thereof, a black matrix 12 for light shielding, a color filter element 11, a counter substrate ITO 10, and a second alignment film 9.
Are sequentially formed, and the second polarizing plate 15 is attached to the other surface. Liquid crystal 16 is sealed between the active matrix substrate and the counter substrate 13.

The operation of the liquid crystal display device of the present example having this configuration is substantially the same as the operation of the known liquid crystal display device, and the operation description of the liquid crystal display device of the present example is omitted.

The liquid crystal display device of this example is superior to the known liquid crystal display device in the following points. The structure of the active matrix substrate used in the known liquid crystal display device,
There are two types: (1) the silicon layer and the gate insulating film are individually photo-processed, and (2) the silicon layer and the gate insulating film are processed with the same photoresist. In (1),
Since the scanning wiring can be covered with a gate insulating film, G / D
It has the advantage of fewer shorts, but has the disadvantage of having more photo processes and more steps than (2). On the other hand, (2) has the advantage that the process is simplified because the silicon layer and the gate insulating film are processed with the same photoresist, but the scanning wiring is exposed during the processing of the signal wiring, and short-circuit defects increase. There are challenges.

In order to solve the above problems, in this example, the silicon layer and the gate insulating film are processed by the same resist to reduce the number of steps, and the silicon layer and the gate insulating film (S) 3 shown in FIG. 1 are newly added. , 4 are placed on the scanning wiring,
The exposed portion of the scanning wiring can be significantly reduced. Therefore, the G / D short circuit and the gate / pixel electrode short circuit can be reduced. Furthermore, when the D disconnection occurs, it is circumvented, and when the G / D short circuit occurs, the signal line is cut off on both sides of the defective portion and the repaired interconnection is circumvented. By forming on the layer and the gate insulating films (S) 3 and 4, line defects can be converted into point defects. Therefore, the manufacturing yield of the liquid crystal display device is improved by the structure of the present invention.

Next, an example of a repair method when D disconnection or G / D short circuit occurs will be shown. FIG. 6 shows a plan view of an active matrix substrate to which the present invention is applied. In this embodiment, Ta is used as the gate material, Cr is used for the source / drain electrodes and the signal wiring, and the pixel electrode is made of ITO. Hereinafter, an example of a repair method when a G / D short circuit occurs will be shown. It is assumed that an etching residue exists in the portion (A) in FIG. 6 and a G / D short circuit occurs. in this case,
Both sides of the location where G / D short occurred ((B) in Fig. 6)
Section) disconnect the signal wiring. Subsequently, Pt is formed as a repair wiring so as to bypass the portion of FIG. At that time, the repair wiring is the TFT
And a silicon layer and a gate insulating film (S) 3 and 4 formed separately from the silicon layer and the gate insulating film under the signal wiring.
Formed on top of. As a result, line defects due to G / D shorts, which could not be repaired conventionally, can be converted into point defects. Regarding the D disconnection, by forming the repair wiring so as to bypass the occurrence location, the line defect can be turned into a point defect like the G / D short. Thus, by newly disposing the silicon layer and the gate insulating films (S) 3 and 4, the effect of relieving the line defect can be obtained.

[0036]

According to the present invention, the following effects are achieved.

(1) By separating the silicon layer and the gate insulating film below the TFT section and the signal wiring and disposing the silicon layer and the gate insulating film on the scanning wiring, the exposed portion of the scanning wiring is significantly reduced. You can Therefore, even if the signal wirings and the pixel electrodes remain in places where they should be removed due to etching defects, the probability of occurrence of G / D short-circuiting and scanning wiring / pixel electrode short-circuiting is reduced.

(2) By making the silicon layer and the gate insulating film newly formed on the scan line larger than the width of the scan line, the repair line for repairing G / D short and D disconnection is formed of silicon. By forming on the layer and the gate insulating film, a line defect can be changed into a point defect.

[Brief description of drawings]

FIG. 1 is a plan view of a pixel portion of an active matrix substrate to which the present invention is applied.

FIG. 2 is a cross-sectional view taken along the line AA ′ of the pixel unit shown in FIG.

3 is a cross-sectional view of a BB 'portion of the pixel portion shown in FIG.

FIG. 4 is a plan view when the present invention is applied to an active matrix substrate having a storage capacitor in each pixel.

5 is a sectional view showing an example of the configuration of a liquid crystal display incorporating the active matrix substrate shown in FIG.

FIG. 6 is a plan view showing an example of a G / D short relief method.

FIG. 7 is a plan view showing the configuration of a conventional active matrix substrate.

8 is a cross-sectional view of the AA ′ portion of the active matrix substrate shown in FIG.

[Explanation of symbols]

2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Amorphous silicon layer, 6 ... Drain electrode, 6 '... Signal wiring, 7 ... Protective film.

Claims (4)

[Claims] 1. An inverted staggered thin film transistor comprising a gate electrode, a gate insulating film, a silicon layer, a source / drain electrode, and a protective film, which are sequentially arranged on an insulating substrate, as a switching element, and is provided in an image display area. In a liquid crystal display device having a structure in which a part of a gate electrode wiring and the protective film are directly laminated, the silicon layer and the gate insulating film are provided with a signal wiring for supplying a video signal to a drain electrode and the source / drain electrodes. A liquid crystal display device, wherein the liquid crystal display device is arranged on the gate electrode wiring without being directly laminated, and the gate insulating film is in contact with the insulating substrate. 2. The liquid crystal display device according to claim 1, wherein the silicon layer and the gate insulating film are larger than the width of the gate electrode wiring. 3. An inverted staggered thin film transistor, in which a gate electrode, a gate insulating film, a silicon layer, a source / drain electrode, and a protective film are sequentially arranged on an insulating substrate, is provided as a switching element, and is held for each pixel. In a liquid crystal display device having a capacitance and having a structure in which a part of gate electrode wiring and the protective film are directly laminated in an image display region, in the liquid crystal display device, the silicon layer and the gate insulating film are connected to a drain electrode as a video signal. The gate insulating film is formed on the gate electrode wiring without being directly laminated with the signal wiring for supplying the voltage and the source / drain electrodes, and the silicon layer is formed separately from the silicon layer constituting the storage capacitor. Is in contact with the insulating substrate. 4. The liquid crystal display device according to claim 3, wherein the silicon layer and the gate insulating film are larger than the width of the gate electrode wiring.