JPH07327234A - Digital convergence circuit - Google Patents

Abstract

PURPOSE:To reduce the capacity of an interpolation coefficient ROM of a digital convergence circuit used in display devices corresponding to plural horizontal scanning frequencies. CONSTITUTION:A system discriminating circuit 5 to which both of frequencies fV and fH obtains the number of scanning lines in one field and gives a quotient (p), which is obtained by dividing it by the number of adjustment points in the vertical direction, to a vertical-direction adjustment point interval setting circuit 7, and a read signal based on the quotient (p) is outputted and is given to an interpolation operation coefficient ROM 10. A correction coefficient circuit 9 divides a maximum value (m) of the quotient (p) by (p) to obtain a quotient m/p and gives it to a first multiplication circuit 11. Values 0/m, 1/m,... (m-1)/m are stored in the interpolation operation coefficient ROM 10, and values 0/m, 1/m,... (p-1)/m are read out in accordance with the read signal and are given to the first multiplication circuit 11 and are multiplied by m/p to obtain values 0/p, 1/p,... (p-1)/p as interpolation coefficients.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence circuit used in a display device such as a color television receiver.

[0002]

2. Description of the Related Art In a shadow mask type color television picture tube, three electron beams corresponding to RGB three colors are correctly concentrated at the center of the screen, but since the deflection magnetic field enters at different angles, they are displaced at the periphery. Each of the three electron beams emits a distant point. This is called convergence deviation. A digital convergence circuit that adjusts this convergence deviation by a digital method is disclosed
It is proposed in Japanese Patent No. 61-10386.

This is to set an adjustment point on the display screen as a base point for correcting the convergence deviation, to obtain correction data for correcting the convergence deviation at each adjustment point for each adjustment point, and on the screen based on the obtained correction data. The convergence deviation at each point is corrected by the linear interpolation method.

FIG. 4 is a block diagram of a conventional digital convergence circuit for obtaining a value for correcting the convergence of the screen of a display device corresponding to a plurality of types of horizontal scanning frequencies. The horizontal scanning frequency differs depending on the television signal system. In the figure, 1 is a terminal to which a horizontal synchronizing signal of frequency f _H is input, and the horizontal synchronizing signal input to this terminal excites a clock generation circuit 2 to generate a clock of frequency f _C and adjust in the horizontal direction. It is given to the point setting circuit 3 to divide the frequency. The divided clock becomes a signal of frequency f _{H on} the one hand, and is given to the horizontal address generation circuit 4, the method switching circuit 18, the vertical adjustment point interval setting circuit 7 and the adjustment signal generation circuit 17, and on the other hand the frequency 5 ×. It becomes a signal of f _H and is given to the horizontal address generation circuit 4 and the adjustment signal generation circuit 17. The vertical synchronizing signal of frequency f _V input to the terminal 6 is given to the system switching circuit 18, the vertical adjustment point interval setting circuit 7, the vertical address generation circuit 8 and the adjustment signal generation circuit 17.

The adjusting signal generating circuit 17 generates a signal for displaying straight lines horizontally and vertically on the screen at equal intervals on the basis of the given three kinds of signals, and supplies it to a color picture tube not shown. The intersection of the horizontal and vertical straight lines displayed on the screen becomes the adjustment point for obtaining the correction data for correcting the convergence.

FIG. 5 is a schematic diagram of five evenly-spaced horizontal straight lines and five equally-spaced vertical straight lines displayed on the screen of the color picture tube by the adjusting signal generating circuit 17 of FIG. In the figure, a ₀ , a ₁ and a ₂ are the first horizontal straight lines,
It is the intersection of the second horizontal line from the top and the third horizontal line from the top and the vertical line at the left end, and both are adjustment points for obtaining correction data. Other intersections on the screen are also adjustment points.

The adjuster who obtains the correction data by adjusting the digital convergence circuit makes an adjustment so that the color of the adjustment point a ₀ on the screen of the color picture tube becomes white, and the correction data A
_{Get 0} . The correction data A ₀ is obtained for each of the three colors R, G, and B, but for convenience of explanation, one color will be described by returning to FIG. The obtained correction data A ₀ is written to the address (horizontal, vertical) on the correction data memory 12b corresponding to the coordinate position (horizontal, vertical) of the adjustment point a ₀ . Similarly, the correction data A ₁ , A ₂ ... Of the other adjustment points a ₁ , a ₂ ... Are obtained and written in the correction data memory 12b.

When the correction data A ₀ , A ₁ , A ₂ ... Are written in the correction data memory 12b, a CPU (not shown)
Difference data A ₀ -A ₁ , A ₁ -A corresponding to the correction data
₂ is obtained and written to the address (horizontal, vertical) on the difference data memory 12a corresponding to the coordinate position (horizontal, vertical) of the adjustment points a ₀ , a ₁ . Adjustment ... k from a _{0 in} the vertical direction
The correction data at the intersection of the second scanning line and a straight line passing through a ₀ and perpendicular to this scanning line is given by A ₀ + (A ₀ −A ₁ ) × k / p. Here, k / p is called an interpolation coefficient. k is 0
It is a natural number given by ≦ k ≦ p−1.

[0009] Methods Method of switching circuit 18 is a television signal received, i.e. a circuit for determining the number of scan lines between vertical adjacent adjustment points in response to the horizontal scanning frequency, the signal and the frequency of the frequency f _H defining a number of adjacent scanning lines between adjustment points _{p = f H / f V /} (5-1) on the basis of the vertical synchronizing signal of the f _V, vertical adjustment point interval setting circuit at the predetermined value p 2 binary value 7 and selector 19.

The vertical adjustment point interval setting circuit 7 receives the given signal of frequency f _H , vertical synchronizing signal of frequency f _V and p
Based on the binary number indicating, the timing at which each scanning line between adjacent adjustment points in the vertical direction scans the screen becomes a binary number and is sequentially given to the interpolation coefficient ROM 22. Similarly, the scanning line between adjacent adjustment points changes the screen. The scanning timing is given to the vertical address generation circuit 8.

The interpolation coefficient k / p is 1 / for one value of p.
A set of p, 2 / p ... (p-1) / p is a set, and the configuration of the set is different for each different number of scanning lines. Therefore, the interpolation coefficient ROM 22 includes i kinds of ROM-1, ROM-2, ... ROM-i in order to correspond to i kinds of different scanning lines. Then, according to the timing at which the p scanning lines (the 0th scanning line, the 1st scanning line, the (p-1) th scanning line) scan the screen, the binary number given from the vertical adjustment point interval setting circuit 7 is set. Depending on 0 / p, 1
The values of / p, 2 / p ... (p-1) / p are sequentially read from the respective ROMs and given to the selector 19. The selector 19 determines the interpolation coefficient RO according to the binary value p given by the method switching circuit 18.
Select the ROM corresponding to the value of p from the i types of ROM of M 22 and multiply the interpolation coefficient k / p output by the selected ROM.
Give to 13.

The horizontal address generation circuit 4 has a frequency f
At time to read the correction data and the difference data on the basis of both signals _H and frequency h × f _H, the memories 12a generates a horizontal address of a correction data memory 12b and the difference data memory 12a, gives to 12b. The vertical address generation circuit 8 is configured to detect the correction data memory 12b and the difference data at the time when the correction data and the difference data should be read based on the vertical synchronizing signal given from the terminal 6 and the timing at which the scanning line between the adjacent adjustment points scans the screen. The vertical address of the memory 12a is generated and given to both memories 12a and 12b.

The difference data memory 12a (or the correction data memory 12b) reads difference data (or correction data) based on the given horizontal address and vertical address and supplies it to the multiplication circuit 13 (or addition circuit 14). This difference data is multiplied by the interpolation coefficient k / p in the multiplication circuit, added with the correction data in the addition circuit 14 to become a value for correcting the convergence, converted into an analog signal in the D / A conversion circuit 15, and output in the output circuit 16. It becomes the convergence correction current and is supplied to the correction coil 20. Then, the convergence deviation is corrected.
Such convergence correction is performed for each scanning line.

[0014]

Since the conventional digital convergence circuit is constructed as described above, the interpolation coefficient ROM 22 needs a storage capacity capable of accommodating different numbers of scanning lines depending on the television signal system. is there. Therefore,
There is a problem that the interpolation coefficient ROM 21 of the digital convergence circuit used in an auto scan type display device capable of accepting an image receiving signal of any system requires a large memory capacity.

The present invention has been made in order to solve such a problem, and is provided with a calculation ROM for calculating an interpolation coefficient when the number of scanning lines is maximum, and the number of scanning lines is less than the maximum value. In this case, an object of the present invention is to provide a digital convergence circuit which can be applied to an auto-scan type display device by calculating an interpolation coefficient by the number of scanning lines and a required value in a calculation ROM.

[0016]

A digital convergence circuit according to a first aspect of the present invention corrects the convergence at predetermined n adjustment points in a vertical direction on a screen of a display device corresponding to a plurality of horizontal scanning frequencies. In the digital convergence circuit that stores the correction value,
First dividing means for obtaining a quotient p obtained by dividing the number of scanning lines for scanning the screen by n-1, and a quotient m / obtained by dividing a predetermined value m (m is a natural number p <m) by the quotient p. second dividing means for obtaining p, and storage means for storing a quotient j / m obtained by dividing m natural numbers j obtained by 0 ≦ j ≦ m−1 by the predetermined value m, respectively.
From the m quotients j / m to p values k / m (k is 0 ≦ k ≦
and a multiplying unit for multiplying the value k / m read by the reading unit by the quotient m / p to obtain a product k / p. k /
A value for correcting the convergence between the adjustment points is generated based on the correction value in which p is stored as an interpolation coefficient.

A digital convergence circuit according to a second aspect of the present invention is a digital convergence circuit that stores correction values for correcting convergence at predetermined n adjustment points in a vertical direction on a screen of a display device corresponding to a plurality of horizontal scanning frequencies. In the convergence circuit, a dividing means for obtaining a quotient p by dividing the number of scanning lines for scanning the screen by n-1 and a quotient obtained by dividing a predetermined value m (m is a natural number p <m) by the quotient p. First storage means for obtaining and storing m / p, and a value m / p corresponding to the quotient p from the value stored in the first storage means
first reading means for reading p, second storage means for storing a quotient j / m obtained by dividing m natural numbers j obtained by 0 ≦ j ≦ m−1 by the predetermined value m, and the m quotients. Second reading means for sequentially reading p values k / m from j / m (k is a natural number within the range of 0 ≦ k ≦ p−1) and a value k / m read by the second reading means. Multiplying the value m / p to obtain a product k / p, and generating a value for correcting the convergence between the adjustment points based on the correction value in which the product k / p is stored as an interpolation coefficient. Characterize.

A digital convergence circuit according to a third aspect of the present invention is a digital convergence circuit which stores correction values for correcting convergence at predetermined n adjustment points in a vertical direction on a screen of a display device corresponding to a plurality of horizontal scanning frequencies. In the convergence circuit, first dividing means for obtaining a quotient p by dividing the number of scanning lines for scanning the screen by n-1 and a predetermined value r (r is a natural number r <p) are divided by the quotient p. Second division means for obtaining the quotient r / p, and 0 ≦ j
Storage means for storing a quotient j / r obtained by dividing m natural numbers j obtained by ≦ m−1 (m is a natural number predetermined as the maximum value of the quotient p) by the predetermined value r, and the m quotients. Reading means for sequentially reading p values k / r (k is a natural number within the range of 0 ≦ k ≦ p−1) from j / r, and the quotient r / for the value k / r read by the reading means. and a multiplying unit that obtains a product k / p by multiplying p by generating a value for correcting the convergence between the adjustment points based on the correction value that stores the product k / p as an interpolation coefficient.

A digital convergence circuit according to a fourth aspect of the present invention is a digital convergence circuit that stores correction values for correcting convergence at predetermined n adjustment points in a vertical direction on a screen of a display device corresponding to a plurality of horizontal scanning frequencies. In the convergence circuit, dividing means for obtaining a quotient p by dividing the number of scanning lines for scanning the screen by n-1 and a quotient obtained by dividing a predetermined value r (r is a natural number r <p) by the quotient p. first storage means for obtaining and storing r / p in advance;
First reading means for reading the value r / p corresponding to the quotient p from the value stored in the first storage means, and 0 ≦ j ≦ m−1 (m
Is a second storage means for storing a quotient j / r obtained by dividing m natural numbers j obtained by a predetermined natural number) as the maximum value of the quotient p by the predetermined value r, and the m quotients j / r. To p values k / r (k is a natural number within the range of 0 ≦ k ≦ p−1) are sequentially read, and the value r / p is added to the value read by the second reading device. And a multiplying unit for obtaining a product k / p by which the product is multiplied, and a value for correcting the convergence between the adjustment points is generated based on the correction value stored as the interpolation coefficient of the product k / p.

[0020]

In the digital convergence circuit according to the first aspect of the present invention, the number of scanning lines by which the first dividing means scans the screen is divided by a value obtained by subtracting 1 from the number n of preset adjustment points in the vertical direction of the screen. The quotient p is obtained, the second dividing means obtains a value m / p obtained by dividing a predetermined natural number m as the maximum value of the quotient p by the quotient p, and the storage means obtains m number of m A quotient j / m obtained by dividing the natural number j by the m is stored, the reading means sequentially reads the values from 0 / m to (p−1) / m from the stored value, and the multiplication means multiplies the read value. By multiplying by m / p, an interpolation coefficient for obtaining correction data for correcting the convergence deviation is obtained. Therefore, the storage means is j /
It is only necessary to store the m values indicated by m.

In the digital convergence circuit according to the second aspect of the present invention, the quotient p is obtained by dividing the number of scanning lines by which the dividing means scans the screen by a value obtained by subtracting 1 from the number n of adjustment points which is predetermined in the vertical direction of the screen. The first storage means obtains and stores a quotient m / p obtained by dividing a natural number m determined in advance as the maximum value of the quotient p by the quotient p according to the method, and stores the quotient m / p. A value corresponding to the value of the quotient p is read out, and the second storage means stores the quotient j / m obtained by dividing the m natural numbers j obtained by 0 ≦ j ≦ m−1 by the m, and stores the quotient j / m from the stored value. 2 The reading means sequentially reads the values from 0 / m to (p-1) / m,
The multiplication means multiplies the read value by m / p to obtain an interpolation coefficient for obtaining correction data for correcting the convergence deviation. Therefore, the first storage means only needs to store a certain value m / p corresponding to the number of schemes, and the second storage means only needs to store m values shown by j / m.

In the digital convergence circuit according to the third aspect of the invention, the number of scanning lines by which the first dividing means scans the screen is
The quotient p obtained by dividing the number n of preset adjustment points in the vertical direction of the screen by 1 is obtained, and the second dividing means divides the preset natural number r as the minimum value of the quotient p by the quotient p. r / p is obtained, and the storage means stores the quotient j / m obtained by dividing m natural numbers j obtained by 0 ≦ j ≦ m−1 (m is a natural number predetermined as the maximum value of p) by m. The correction data for correcting the convergence deviation by the reading means sequentially reading the values from 0 / r to (p-1) / r from the stored values and multiplying the read values by r / p. Obtain an interpolation coefficient for obtaining Therefore, the storage means only needs to store m values represented by j / r.

In the digital convergence circuit according to the fourth aspect of the present invention, the quotient p is obtained by dividing the number of scanning lines by which the dividing means scans the screen by a value obtained by subtracting 1 from the number n of adjustment points which is predetermined in the vertical direction of the screen. The first storage means obtains and stores in advance a quotient r / p obtained by dividing a natural number r predetermined as the minimum value of the quotient p by the quotient p in accordance with the method. A value corresponding to the value of p is read out, and the second storage means divides m natural numbers j obtained by 0 ≦ j ≦ m−1 (m is a natural number predetermined as the maximum value of the quotient p) by the r. j
/ R is stored, and the second reading means stores 0 / based on the stored value.
The values from r to (p-1) / r are sequentially read, and the multiplication means multiplies the read value by r / p to obtain an interpolation coefficient for obtaining correction data for correcting the convergence deviation. Therefore, the first storage means only needs to store a certain value r / p corresponding to the number of methods, and the second storage means only needs to store m values shown by j / r.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. First Embodiment FIG. 1 is a block diagram of a digital convergence circuit according to the first embodiment, and is for obtaining a value for correcting the convergence of the screen of a display device corresponding to a plurality of horizontal scanning frequencies. In the figure, 1 is a terminal to which a horizontal synchronizing signal of frequency f _H is input, and the horizontal synchronizing signal input to this terminal 1 is a clock generation circuit 2
Is excited to become a signal of frequency f _C , which is given to the horizontal adjustment point number setting circuit 3 and divided to become a signal of frequency f _{H and} a signal of frequency h × f _H. h is the number of vertical adjustment points on the screen (not shown).

The signal of frequency f _H is given to the horizontal address generation circuit 4, the system identification circuit 5, the vertical adjustment point interval setting circuit 7 and the adjustment signal generation circuit 17, and the signal of frequency h × f _H is supplied to the horizontal address. It is given to the generation circuit 4 and the adjustment signal generation circuit 17. The vertical synchronizing signal of frequency f _V input to the terminal 6 is given to the system identifying circuit 5, the vertical adjustment point interval setting circuit 7, the vertical address generating circuit 8 and the adjusting signal generating circuit 17.

The adjusting signal generating circuit 17 generates a signal for displaying straight lines horizontally and vertically on the screen at equal intervals on the basis of the given three kinds of signals, and gives it to a color picture tube not shown. The intersection of the horizontal and vertical straight lines displayed on the screen becomes the adjustment point for obtaining the correction data for correcting the convergence.

FIG. 2 shows that the adjustment signal generating circuit 17 of FIG.
ー Horizontally-spaced n straight lines displayed on the screen of the picture tube
It is a schematic diagram of a line and a vertical straight line of h equal intervals. In the figure
The rectangle A indicated by the dotted line is the maximum image that can be displayed by the video signal.
A rectangular area B, which is a surface area and is indicated by a thick solid line, is a color picture tube.
This is the maximum screen area that can be displayed. Of general color picture tubes
The size of the display screen is the maximum of the maximum screen that can display video signals.
Less than size The adjustment signal generation circuit 17 displays the video signal.
(N + 2) equal intervals that can be displayed on the maximum screen that can be displayed
Of horizontal lines and (h + 2) evenly spaced vertical lines
Frequency f _HSignal, frequency h × f_HSignal and lap
Wave number f_VIt is generated based on the vertical synchronizing signal of. And water
The correction data is obtained at the intersection of the flat and vertical straight lines.
This is the adjustment point.

In the area A, the intersection of the uppermost horizontal straight line and the second vertical straight line from the left is the virtual adjustment point a ₀₁ , and the second horizontal straight line from the top and the leftmost vertical straight line. The intersection with and is the virtual adjustment point a ₁₀ . The intersections on the top and bottom horizontal straight lines and the intersections on the leftmost and rightmost vertical straight lines include both adjustment points a ₀₁ and a ₁₀ , and both are on the display screen of the color picture tube. It is a virtual adjustment point that is not displayed in.

In the region B, the intersections of the first horizontal line, the second horizontal line from the top, and the third horizontal line from the top and the leftmost vertical line are the adjustment points a ₁₁ , a ₂₁ , and a ₃₁ . The intersection of the uppermost horizontal line and the second vertical line from the left is the adjustment point a ₁₂ . An adjuster who adjusts the digital convergence circuit makes an adjustment so that the color of the adjustment point a ₁₁ on the screen of the color picture tube becomes white, and obtains the correction data A ₁₁ .
The correction data A ₁₁ is obtained for each of the three colors R, G, B, but for convenience of explanation, one color will be described with reference to FIG.

The obtained correction data A ₁₁ is the correction data memory 12b corresponding to the coordinate position (horizontal, vertical) of the adjustment point a _11.
Written to the above address. Similarly, other adjustment points a ₂₁ ,
a ₃₁ ... of the correction data A _21, A ₃₁ ... is obtained, is written into the correction data memory 12b. If the correction data is written into the correction data memory 12b, the difference data A ₁₁ -A ₂₁ a not-shown CPU corresponding to the correction data, A ₂₁ -A ₃₁ ...
Is calculated, and the coordinate position of the adjustment points a ₁₁ , a ₂₁ ... (Horizontal, vertical)
Address on the difference data memory 12a (horizontal,
(Vertical).

The correction data A ₀₁ of the virtual adjustment point a ₀₁ is obtained based on the correction data A ₁₁ and A ₂₁ , and the virtual adjustment point a _{10 is obtained.}
The correction data A ₁₀ is calculated based on the correction data A ₁₁ and A ₁₂ . Correction data for other virtual adjustment points are also obtained in the same manner. The difference data at the virtual adjustment point is also obtained in the same manner as the difference data at the adjustment point. The correction data (or difference data) of each virtual adjustment point thus obtained is written in the correction data memory 12b (or difference data memory 12a) at the address corresponding to the coordinate position.

From the adjustment point a _{11 in the} vertical direction from 0 to a number k
The correction data at the intersection of the th scanning line and the straight line perpendicular to this scanning line through the point a ₁₁ is expressed by the following equation: A ₁₁ + (A ₁₁ −A ₂₁ ) × k / p (1) Given in. Here, k / p is called an interpolation coefficient. k is 0
It is a natural number given by ≦ k ≦ p−1. The correction data at the intersection of the scanning line between the adjustment points and the straight line passing through the adjustment point and perpendicular to the scanning line is given according to the equation (1). This also applies to the virtual adjustment points. Therefore area B
The correction data for all scanning lines in is given according to Eq. (1).

Based on the given signal of the frequency f _H and the vertical synchronizing signal of the frequency f _V , the system identification circuit 5 outputs f _H / f
By finding the number of scanning lines in one field by _V ,
The video signal system is identified, the quotient obtained by dividing the number of scanning lines by n-1, that is, the number of scanning lines p between vertically adjacent adjustment points, is obtained, and is made a digital value to adjust the vertical adjustment point interval setting circuit. 7 and the correction coefficient circuit 9.

The vertical adjustment point interval setting circuit 7 requires the correction data at the time when the correction data is required based on the given signal of the frequency f _H , the vertical synchronizing signal of the frequency f _V and the digital signal indicating the quotient p. The value indicating the scanning line to be set as a digital value is given to the interpolation calculation coefficient ROM 10,
Similarly, the vertical address generation circuit 8 is notified of the time when the correction data is needed.

The maximum value of the horizontal scanning frequency of the signal received by the display device having the digital convergence circuit is divided by the frequency f _V of the vertical synchronizing signal to obtain the number of scanning lines in one field, and the number of scanning lines is further determined. Let m be a value obtained by dividing by n-1. The correction coefficient circuit 9 stores this value m. The correction coefficient circuit 9 is supplied with the binary value p from the system identification circuit 5 and is stored with the stored value m.
Then, the quotient m / p is obtained to obtain a digital value, which is given to the first multiplication circuit 11.

The interpolation calculation coefficient ROM 10 is j / m (j is 0 ≦ j
(M natural number given by ≦ m−1) is stored, and the value corresponding to the scanning line indicated by the vertical adjustment point interval setting circuit 7, that is, 0 / m, 1 / m ... (p-1) /
The value of m is sequentially read and given to the first multiplication circuit 11. p /
The values of m, (p + 1) / m ... (m-1) / m are not read. The first multiplication circuit 11 multiplies the value given from the interpolation calculation coefficient ROM 10 by the value m / p given from the correction coefficient circuit k.
/ P (k is a natural number given by 0 ≦ k ≦ p−1) is given to the second multiplication circuit 13.

The horizontal address generating circuit 4 forms a point of intersection when a straight line passing through the adjustment point on the screen and perpendicular to the scanning line intersects with the scanning line based on both the signals of the frequency f _H and the frequency h × f _H. Of the correction data memory 12b and the difference data memory 12a, and the obtained values are given to the corresponding memories. Vertical address generation circuit 8
At the time when the correction data given from the vertical adjustment point interval setting circuit 7 is needed, the vertical address of the adjustment point corresponding to that time is given to the correction data memory 12b based on the vertical synchronizing signal given from the terminal 6. Each of the difference data memories 12a is obtained, and the obtained value is given to the corresponding memory.

The difference data memory 12a (or the correction data memory 12b) reads difference data (or correction data) based on the given horizontal address and vertical address and supplies it to the second multiplication circuit 13 (or addition circuit 14). . This difference data is multiplied by k / p in the second multiplication circuit 13 and added to the addition circuit.
The correction data is added at 14 and becomes a value for correcting the convergence, which is converted to an analog signal at the D / A conversion circuit 15, and becomes the convergence correction current at the output circuit 16, and the correction coil
Supplied to 20. Then, the convergence deviation is corrected. Such convergence correction is performed for each scanning line.

Next, in the case where the field frequency is 60 Hz, and the number of vertical adjustment points is 17 in the digital convergence circuit of the color television receiver which receives the signals whose horizontal scanning frequency is from 15.36 kHz to 61.44 kHz. The operation will be described. Since the field frequency is 60Hz, the number of scanning lines in one field is 256 (15360/60)
Up to 1024 (61440/60). Since the number of adjustment points in the vertical direction is 17, the screen is horizontally divided into 16, and the number of scanning lines p between adjacent adjustment points is 16 (256/16) to 64 (1024/16). This value is obtained by the system identification circuit 5. The maximum value of p, m, is 64 and is constant.

The correction coefficient circuit 9 is a value m / p (64/16, 64/17, 64 /) corresponding to the value of p given from the system identification circuit 5.
18 ... 64/64) and one value out of 49 types is given to the first multiplication circuit 11. The interpolation calculation coefficient ROM 10 is 0 /
64, 1/64, 2/64 ... 63/64 values are stored. When the value of p is 16, 0/64, 1/6
16 values of 4, 2/64 ... 15/64 are sequentially read according to the timing given from the vertical adjustment point interval setting circuit 7 and given to the first multiplication circuit 11, where 4 (64/16) )
And the interpolation coefficient k / p is 0/16, 1/16, 2
/16...15/16 is obtained. Then, a value for correcting the convergence is obtained based on the interpolation coefficient.

As described above, based on the number of scanning lines m between adjacent adjustment points at the maximum horizontal scanning frequency, 0 / m, 1 / m ...
The value of (m-1) / m is stored in the interpolation calculation coefficient ROM 10, and when the scanning line between adjacent adjustment points is p, the p values k / m are sequentially read from the interpolation calculation coefficient ROM 10. By multiplying the difference data with m / p, the interpolation coefficient k / p to be multiplied by the difference data is obtained. Therefore, only one interpolation calculation coefficient ROM 10 is required.

The means for calculating the interpolation coefficient corresponding to different variables as shown in the present embodiment is not limited to the digital convergence circuit, but also the image distortion correction circuit, the dynamic focus correction circuit, and the digital vertical deflection. It is needless to say that the present invention can be applied to a circuit or a circuit that digitally adjusts the amplitude of a video signal to correct the brightness difference between the top, bottom, left and right of the screen or the uniformity of the screen.

Embodiment 2. FIG. 3 is a block diagram of a digital convergence circuit according to the second embodiment, in which a value for correcting the convergence of the screen of the display device corresponding to a plurality of horizontal scanning frequencies is obtained. In the figure, reference numeral 21 denotes a correction coefficient ROM, which stores in advance a value m / p corresponding to the number p of scanning lines between adjacent adjustment points in the vertical direction, and which corresponds to the value p given from the system identification circuit 5. m / p
To the first multiplication circuit 11. Other configurations are the same as those in FIG. 1, and the same portions are denoted by the same reference numerals and the description thereof is omitted.

Next, in the case where the field frequency is 60 Hz and the number of adjustment points in the vertical direction is 17 in the digital convergence circuit of the color television receiver which receives signals with the horizontal scanning frequency from 15.36 kHz to 61.44 kHz. The operation will be described.

Since the number of adjustment points in the vertical direction is 17, the screen is divided into 16 horizontally, the number of scanning lines p between adjacent adjustment points is 16 to 64, and the maximum value m is 64. Correction coefficient RO
M 21 stores 49 kinds of values of 64/16, 64/17, 64/18 ... 64/64, and when the value of p is 16, 4 (64/16) is read and the first multiplication is performed. It is given to the circuit 11 and multiplied by 16 values of 0/64, 1/64, 2/64 ... 15/64 read from the interpolation calculation coefficient ROM 10, respectively. Then, 0/16, 1/16, 2/16 ... 15/16 are obtained as the interpolation coefficient k / p. Then, a value for correcting the convergence is obtained based on the interpolation coefficient. Correction coefficient ROM that stores m / p values in this way
It is read out from 21 and calculated, and the calculation is not performed, so the time to calculate m / p is short. The storage means is an interpolation calculation coefficient ROM 10
And the correction coefficient ROM 21 does not increase the storage capacity.

Embodiment 3. Horizontal scanning frequency f of a signal received by a display device corresponding to a plurality of horizontal scanning frequencies
The minimum value of _H is divided by the frequency f _V of the vertical synchronizing signal to obtain the number of scanning lines in one field, and the number of scanning lines is n
The value divided by -1 is r. Therefore, r ≦ p ≦ m.
The digital convergence circuit of this embodiment divides the value r built in the correction coefficient circuit 9 in FIG. 1 by the given value p to obtain the value r / p and gives it to the first multiplication circuit 11. Then, the built-in arithmetic coefficient ROM 10 stores the value of j / r, sequentially reads the stored value of j / r according to the binary number given from the vertical adjustment point interval circuit 7, and then the first multiplication circuit 11
Other configurations are similar to those of FIG.

Next, in the case where the field frequency is 60 Hz and the number of adjustment points in the vertical direction is 17 in the digital convergence circuit of the color television receiver which receives signals with the horizontal scanning frequency from 15.36 kHz to 16.44 kHz. The operation will be described. Since the number of adjustment points in the vertical direction is 17, the screen is horizontally divided into 16, the number of scanning lines p between adjacent adjustment points is 16 to 64, and the minimum value r is 16 and the maximum value m. Is 64. The correction coefficient circuit 9 divides the built-in value r by the value p given from the system identification circuit 5,
The value r / p is obtained and given to the first multiplication circuit 11.

The interpolation calculation coefficient ROM 10 has 0/16, 1/16,
2/16 ... 63/16 values of 64 types are stored. And p
When the value of 16 is 0/16, 1/16, 2/16… 15/16
16 values are sequentially read according to the timing given from the vertical adjustment point interval setting circuit 7, and the first multiplication circuit
Is given to 11, where it is multiplied by 1 (16/16) and 0/1
6, 1/16, 2/16 ... 15/16 interpolation coefficients are obtained. Then, a value for correcting the convergence is obtained based on the interpolation coefficient.

In this way, 0 / r, 1 / r ... (m−) based on the number r of scanning lines between adjacent adjustment points at the minimum horizontal scanning frequency.
1) / r value is stored in the interpolation calculation coefficient ROM 10, and when the scanning line between adjacent adjustment points is p, the p values k / r are sequentially read from the interpolation calculation coefficient ROM 10 and r By multiplying by / p, the interpolation coefficient k / p to be multiplied by the difference data is obtained. The value of the interpolation calculation coefficient ROM 10 is j / r, so j / r
Since the value is larger than m, the accuracy of the interpolation coefficient k / p is improved, and the interpolation calculation coefficient ROM 10 may be one kind.

Embodiment 4. Scanning one field by dividing the minimum value of the horizontal scanning frequency f _H of the signal received by the display device corresponding to a plurality of types of horizontal scanning frequencies by the frequency f _V of the vertical synchronizing signal. The number of lines is obtained, and the value obtained by dividing the number of scanning lines by n-1 is r. Therefore, r ≦ p ≦ m. In the digital convergence circuit of this embodiment, the correction coefficient ROM 21 in FIG. 3 stores in advance a value r / p corresponding to the number p of scanning lines between adjacent adjustment points in the vertical direction,
The r / p corresponding to the value p given from the system identification circuit 5 is given to the first multiplication circuit 11. Then, the interpolation calculation coefficient ROM 10 stores the value j / r, and sequentially reads the stored value of j / r according to the binary number given from the vertical adjustment point interval setting circuit 7, and the first multiplication circuit 11 Give to. Other configurations are the same as those in FIG.

Next, when the field frequency is 60 Hz,
The operation when the number of adjustment points in the vertical direction is 17 in the digital convergence circuit of the color television receiver which receives the signals with the horizontal scanning frequency from 15.36 kHz to 16.44 kHz will be described. Since the number of adjustment points in the vertical direction is 17, the screen is divided into 16, the number of scanning lines p between adjacent adjustment points is 16 to 64, the minimum value r is 16 and the maximum value m is 64. is there. The correction coefficient ROM 21 is 16/16, 16/17,
16/18 ... Stores 49 values of 16/64, and the value of p is 16
If it is, 1 (16/16) is read and the first multiplication circuit 11
Give to.

The interpolation calculation coefficient ROM 10 has 0/16, 1/16,
2/16 ... 63/16 values of 64 types are stored. And p
If the value of is 16, then 0/16, 1/16, 2/16… 15 /
16 values of 16 are sequentially read according to the timing given from the vertical adjustment point interval setting circuit 7 and given to the first multiplication circuit 11, where they are multiplied by 1 (16/16) and 0 /
16, 16/16, 2/16 ... 15/16 interpolation coefficients k / p are obtained. Then, a value for correcting the convergence is obtained based on the interpolation coefficient.

Since the r / p value is read out from the correction coefficient ROM 21 in which the value is stored in this way, the time required to obtain r / p is short, and the value of the interpolation calculation coefficient ROM 10 is j / r. , J / m, and therefore the interpolation coefficient k
The accuracy of / p is improved, and the storage means may be two types of interpolation calculation coefficient ROM 10 and correction coefficient ROM 21, and the storage capacity does not increase.

[0054]

As described above, according to the first or third invention, the maximum value of the number of scanning lines p between adjacent adjustment points in the vertical direction is m and the minimum value thereof is r, and 0, 1, If each term of the arithmetic series of 2 ... m-1 is j, and each term of the arithmetic series of 0,1,2 ... p-1 is k, then m terms of j / m (or j / r) The values are stored, p values are sequentially read from the stored values according to the value of p, and the interpolation coefficient k / p is obtained by multiplying by m / p (or r / p) calculated. The correction data for correcting the convergence is required. Therefore, it is not necessary to store the interpolation coefficient k / p for each different horizontal scanning frequency,
Only the seed storage means is required. Therefore, the digital convergence circuit used in the auto-scan display device does not have a large storage capacity for obtaining the interpolation coefficient.

According to the second or fourth invention, the first
M / p (or r obtained by calculation in the invention or the third invention)
By previously calculating and storing / p), there are two types of storage means, but the storage capacity does not become large and the time for obtaining the interpolation coefficient becomes short.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital convergence circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram of adjustment points displayed on the screen by the adjustment signal generation circuit 17 shown in FIG.

FIG. 3 is a block diagram of a digital convergence circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional digital convergence circuit.

5 is a schematic diagram of adjustment points displayed on the screen by the adjustment signal generation circuit 17 shown in FIG.

[Explanation of symbols]

5 system identification circuit, 9 correction coefficient circuit, 10 interpolation calculation coefficient ROM, 11 first multiplication circuit, 21 correction coefficient ROM.

Claims (4)

[Claims] 1. A scan for scanning a screen in a digital convergence circuit that stores correction values for correcting convergence at predetermined n adjustment points in the vertical direction on the screen of a display device corresponding to a plurality of horizontal scanning frequencies. First dividing means for obtaining a quotient p obtained by dividing the number of lines by n-1, and a predetermined value m (m is a natural number p <m) for the quotient p
Second dividing means for obtaining a quotient m / p divided by, storage means for storing a quotient j / m obtained by dividing m natural numbers j obtained by 0 ≦ j ≦ m−1 by the predetermined value m, respectively. From m quotients j / m to p values k / m (k is 0 ≦ k ≦
and a multiplying unit for multiplying the value k / m read by the reading unit by the quotient m / p to obtain a product k / p. A digital convergence circuit, which generates a value for correcting convergence between adjustment points based on the correction value in which k / p is stored as an interpolation coefficient. 2. A scan for scanning a screen in a digital convergence circuit that stores correction values for correcting convergence at predetermined n adjustment points in the vertical direction on the screen of a display device corresponding to a plurality of horizontal scanning frequencies. Dividing means for obtaining a quotient p by dividing the number of lines by n-1, and a predetermined value m (m is a natural number p <m) for the quotient p
First storage means for obtaining and storing the quotient m / p divided by, first reading means for reading the value m / p corresponding to the quotient p from the value stored in the first storage means, and 0 ≦ j ≦ Second storage means for storing a quotient j / m obtained by dividing m natural numbers j obtained by m-1 by the predetermined value m, and p values k / m (k) from the m quotients j / m. Is 0 ≦ k ≦
second reading means for sequentially reading out a natural number within the range of p−1 and multiplying means for obtaining a product k / p obtained by multiplying the value k / m read by the second reading means by the value m / p. A digital convergence circuit comprising: a value for correcting the convergence between the adjustment points based on the correction value in which the product k / p is stored as an interpolation coefficient. 3. A scan for scanning a screen in a digital convergence circuit that stores correction values for correcting convergence at predetermined n adjustment points in the vertical direction on the screen of a display device corresponding to a plurality of horizontal scanning frequencies. First dividing means for obtaining a quotient p by dividing the number of lines by n-1, and a predetermined value r (r is a natural number r <p) for the quotient p
Second dividing means for obtaining the quotient r / p divided by, and m natural numbers j obtained by 0 ≦ j ≦ m−1 (m is a natural number predetermined as the maximum value of the quotient p) by the predetermined value r Storage means for storing the divided quotient j / r, and p values k / r (k is 0 ≦ k ≦) from the m quotients j / r
read-out means for sequentially reading out a natural number within the range of p-1 and multiplication means for obtaining a product k / p by multiplying the value k / r read out by the read-out means by the quotient r / p; A digital convergence circuit, which generates a value for correcting convergence between adjustment points based on the correction value in which k / p is stored as an interpolation coefficient. 4. A scan for scanning a screen in a digital convergence circuit which stores correction values for correcting convergence at predetermined n adjustment points in the vertical direction on the screen of a display device corresponding to a plurality of horizontal scanning frequencies. Dividing means for obtaining a quotient p by dividing the number of lines by n-1, and a predetermined value r (r is a natural number r <p) for the quotient p
First storage means for previously obtaining and storing the quotient r / p divided by, first reading means for reading the value r / p corresponding to the quotient p from the value stored in the first storage means, and 0 ≦ j ≦ m−1 (m is a natural number predetermined as the maximum value of the quotient p), and the m natural numbers j are respectively determined by the predetermined value r.
Second storage means for storing the quotient j / r divided by, and p values k / r (k is 0 ≦ k ≦) from the m quotients j / r.
second reading means for sequentially reading out a natural number within the range of p−1 and multiplying means for obtaining a product k / p by multiplying the value read by the second reading means by the value r / p, A digital convergence circuit, which generates a value for correcting convergence between adjustment points based on the correction value in which the product k / p is stored as an interpolation coefficient.