JPH07327178A - Video signal processing unit - Google Patents

Abstract

PURPOSE:To display required data in a reception signal on a screen accurately by writing data of a desired area in which caption production is estimated to an image memory and displaying memory content on a desired position of the display screen. CONSTITUTION:A TV signal from an input terminal 10 is stored in an image memory 2 for a period corresponding to a display area on a screen in which caption production is estimated. Furthermore, a vertical synchronizing signal V and a horizontal synchronizing signal H separated are applied to a display position setting circuit 4. The circuit 4 generates timing signals (1st to 3rd) displaying a storage content of the memory 2 to a position on the screen based on the two synchronizing signals. The 1st signal decides read of the memory 2 and the 2nd and 3rd signals decide the display quantity and display area of an image. A read circuit 5 starts reading depending on the 1st signal. Longitudinal and lateral display area setting circuits 6, 7 generate vertical and horizontal switch changeover signals based on the 2nd and 3rd signals. Thus, a switch circuit 9 is thrown to the position of (b) and the synthesized image signal is generated at an output terminal 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus suitable for performing subtitle moving processing for TV (television) broadcasting having different aspect ratios.

[0002]

2. Description of the Related Art At present, in NTSC TV broadcasting currently being broadcast in Japan, the aspect ratio is 4: 3 (horizontal 4 vertical 3), so that the TV receiver side also has a screen size. Is set to 4: 3. However, recently
Some TV sets have a screen size set to 16: 9. Since the aspect ratios of the two do not have a similar relationship, a display problem occurs.

For example, as shown in FIG. 2 (a), a Western picture screen with subtitles of 4: 3 is being sent, and if it is displayed at 16: 9 as shown in FIG. 2 (b), the original screen is displayed. 100% is displayed in the horizontal direction, but in the vertical direction, a dropout occurs in the upper and lower parts. Then, generally, the subtitles existing at the bottom or the top of the screen are not displayed. Therefore, FIG. 2 (c)
There is a need to move subtitles like this. For this method,
In the area where subtitles are expected to occur in advance in FIG. 2 (a), among the incoming luminance signals, a level equal to or higher than a preset level is regarded as a subtitle signal, and the data is once written in the memory and the desired position is displayed. I read it at and superimposed.

[0004]

However, in the case where the caption signal is discriminated by the comparator as described above,
When the luminance signal level of the background is high, there is a problem that the background is erroneously discriminated as a caption and the caption display becomes difficult to see.

[0005]

The present invention has been made in view of the above points, and a writing circuit for writing a television signal in an image memory and a vertical synchronizing signal and a horizontal synchronizing signal are separated from the television signal. A sync separation circuit, a display position setting circuit for generating a timing signal for setting a display position in response to the vertical synchronization signal and the horizontal synchronization signal, and the image in response to a first timing signal from the display position setting circuit. A read circuit for reading a television signal from the memory, a vertical display area setting circuit for setting a vertical display area of the screen according to a second timing signal from the display position setting circuit, and the display position setting circuit. A horizontal display area setting circuit for setting a horizontal display area of the screen in accordance with the third timing signal of A combining circuit for combining the output signal of the output signal and the lateral display area setting circuit Teikairo,
A switch circuit for switching and outputting a television signal before being written in the image memory and a television signal read from the image memory according to an output signal of the synthesizing circuit.

[0006]

According to the present invention, the entire screen or a desired area where subtitles are expected to be generated on the screen is written in the image memory, and the contents of the image memory are displayed at a desired position on the display screen. Therefore, it is not necessary to detect the caption signal, and the caption can be displayed.

[0007]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.
(1) is a writing circuit for writing a television signal in the image memory (2), (3) is a sync separating circuit for separating a vertical synchronizing signal and a horizontal synchronizing signal from the television signal,
(4) is a display position setting circuit that generates a timing signal for setting a display position according to the vertical synchronizing signal and the horizontal synchronizing signal, and (5) is a first timing signal from the display position setting circuit (4). A readout circuit for reading out a television signal from the image memory in accordance with the above, and (6) vertical display for setting a vertical display area of the screen in response to a second timing signal from the display position setting circuit (4). An area setting circuit, (7) a horizontal display area setting circuit for setting a horizontal display area of the screen in accordance with the third timing signal from the display position setting circuit (4), and (8) a vertical direction. A synthesizing circuit for synthesizing the output signal of the display area setting circuit (6) and the output signal of the lateral display area setting circuit (7), and (9) is a television set before being written in the image memory (2). A switch for switching between a signal and a television signal read from the image memory (2) according to the output signals of the vertical display area setting circuit (6) and the horizontal display area setting circuit (7). Circuit.

The TV signal from the input terminal (10) of FIG. 1 has a writing circuit () during a period corresponding to a display area (a lower part of the screen, for example, ¼) where subtitles are expected to be generated on the screen. It is stored in the image memory (2) via 1). It should be noted that all of one screen may be stored. Further, the TV signal is subjected to sync separation in a sync separation circuit (3) and a vertical sync signal V and a horizontal sync signal H are applied to a display position setting circuit (4). The display position setting circuit (4) generates a timing signal for displaying the content stored in the image memory (2) at a certain position on the screen based on the two synchronization signals. The first timing signal determines the timing of reading the image (caption) stored in the image memory (2). Second
Timing signal (V-ST) and third timing signal (H
-ST) is a signal (switching signal of the switch circuit (9)) that determines the vertical and horizontal display areas for displaying the entire read image (caption) or partially displaying the image. .

The reading circuit (5) starts reading in response to the first timing signal. The reading speed may be arbitrary. For example, in the vertical direction, the number of scanning lines may be thinned out to one out of two lines, and in the horizontal direction, the read and written areas may be compressed to 1/4 and generated. Vertical and horizontal display area setting circuit (6)
3 and (7), when displaying an image (caption) as shown in FIG. 3, the vertical switch change signal (V-E) shown in FIG.
(NA) and horizontal switch change signal (H-ENA)
To occur.

Therefore, the switch circuit (9) is switched to the b side, and the combined image signal is generated at the output terminal (11). FIG. 4 shows a specific circuit example of the vertical and horizontal display area setting circuits (6) and (7) and the synthesizing circuit (8) of FIG. 1, and FIG. 5A to FIG. While explaining. Now, assume that the image of FIG. 5E is stored in the image memory (2) of FIG. It is assumed that only the lower half of the image in FIG. 5 (e) is to be displayed as in FIG. 5 (a). In this case, the value of the register (12) is set so that the signal V-EQ whose rising occurs occurs at the position just half of the screen of FIG. 5 (a). Further, the terminal TOP is set to H level and the terminal BOT is set to L level. The second timing signal (V-ST) shown in FIG. 5A corresponds to the input terminal (1
When applied to 3), the vertical counter (14) is released from reset and starts counting. In addition, OR gate (1
RS-FF (16) is reset via 5). In addition, the second timing signal (V-ST) is a delay D-F.
It is applied to the AND gate (18) via F (17). Therefore, the RS-FF (16) maintains the reset state for a while. After that, when the count of the vertical counter (14) advances and the value of the register (12) matches, the match detection circuit (19) generates a match detection signal V-EQ, and the AND gate (20) and the OR gate (21). Via RS-
Set the FF (16). Then, RS-FF (1
The Q output (V-ENA) of 6) is as shown in FIG. 5A, and the AND gate (2) that operates as the synthesizing circuit (8).
A signal of "H" level (defining a display area in the vertical direction) for switching the switch circuit (9) of FIG. 1 to the b side is applied to 2). At this time, RS is added to the AND gate (22) in FIG.
-"H" that defines the horizontal display area from FF (23)
It is necessary that the level switch switching signal (H-ENA) has arrived.

In order to end the signal (V-ENA) of FIG. 5A, it is necessary to separately apply a vertical end signal to the OR gate (15) of FIG. FIG. 5B is the same as FIG.
It is an example in which the upper half of the screen of (e) is displayed. In this case, the value of the register (12) is made the same as that of FIG. 5 (a) and the terminal TOP = L level and the terminal BOT = H level. Then, the vertical switch changeover signal (V-ENA) shown in FIG. 5B is obtained.

As shown in FIGS. 5 (a) and 5 (b), if the resist value of the register (12) is changed, the coincidence detection signal V-EQ can be generated at any position, and the vertical display area can be generated. Can be freely set. 5C and 5D are for changing the display area in the horizontal direction, which is achieved by the lower block in FIG. This block is the same as that in the vertical direction, and the description thereof is omitted.

Various display areas can be created by combining the display areas of FIGS. 5A to 5D. Figure 5
To display the entire area shown in (e), the terminals TOP and BOT are set to the L level and the terminal RIGH in FIG. 4 is displayed.
It is sufficient to set T and the terminal LEFT to the L level.

Therefore, according to the apparatus of FIG. 4, an image (caption) can be generated at an optimum position by adjusting the value of the register.

[0015]

According to the present invention, even when the aspect ratio of the received signal and the screen size are different, the necessary data (subtitles, etc.) in the received signal can be displayed on the screen. In particular, according to the present invention, not only the data is received from the received signal, but also all the signals including the background signal are captured and the captured data is displayed as it is, so that it is possible to stably display without data loss. Become.

[Brief description of drawings]

FIG. 1 is a block diagram showing a video signal processing device of the present invention.

FIG. 2 is a diagram illustrating an operation of a conventional video signal processing device.

FIG. 3 is a diagram for explaining the operation of the video signal processing device of the present invention.

FIG. 4 is a block diagram showing a specific example of FIG.

5 is a block diagram illustrating the operation of FIG. 4. FIG.

[Explanation of symbols]

 (1) Write circuit (2) Image memory (3) Sync separation circuit (4) Display position setting circuit (5) Read circuit (6) Vertical display area setting circuit (7) Horizontal display area setting circuit (8) Switch circuit

Claims (2)

[Claims] 1. A writing circuit for writing a television signal in an image memory, a sync separating circuit for separating a vertical synchronizing signal and a horizontal synchronizing signal from the television signal, and a display according to the vertical synchronizing signal and the horizontal synchronizing signal. A display position setting circuit that generates a timing signal for position setting; a read circuit that reads a television signal from the image memory in response to a first timing signal from the display position setting circuit; A vertical display area setting circuit that sets a vertical display area of the screen according to a second timing signal, and sets a horizontal display area of the screen according to a third timing signal from the display position setting circuit. A horizontal display area setting circuit, an output signal of the vertical display area setting circuit, and a horizontal display area setting circuit A synthesizing circuit for synthesizing the output signal, and a switch circuit for switching and outputting the television signal before being written in the image memory and the television signal read from the image memory in accordance with the output signal of the synthesizing circuit. A video signal processing device comprising: 2. The vertical display area setting circuit includes a vertical counter that counts according to a second timing signal, a register that holds data indicating a desired vertical position, and a count value of the vertical counter. 2. The video signal processing device according to claim 1, further comprising: a coincidence detection circuit for detecting coincidence between the data of the register and the data of the register.