JPH07326973A - Methods for coding and decoding error detection and devices for coding and decoding error detection - Google Patents

Abstract

PURPOSE:To execute the error detection of byte unit data as it is through the use of an error detection code for binary data by providing a byte data input, an EXOR block, plural latch circuits with SR, an error judging circuit and an output circuit. CONSTITUTION:An m-bit latch 43 is initialized and next, one-byte unit data is inputted from an input terminal 41. Each bit of input data and each output of the m-bit latch are inputted to the latch 43 by composing an EXOR circuit 42 by a relation obtained by the result of 8-bit shift by means of the cyclic code error detecting and coding device of a binary data processing type. Data is shifted by a portion of one clock by a clock synchronizing with data from a clock terminal 44 in this state and when next one-byte data is inputted the latch circuit 43 is shifted once by a byte unit clock. Thereafter, the similar processing is repeated for the portion of input data and parity data and after final shift, whether the outputs of the latch 43 are all zero or not is inspected by an error judging circuit 71. Then, the result of entirely being zero is judged to be no error but the results excepting for it are judged to have an error and are outputted from an output terminal 72.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detecting method and apparatus when recording or communication data is reproduced or received in a recording medium or transmission communication.

[0002]

2. Description of the Related Art Conventionally, in a recording medium or transmission communication, a (shortened) cyclic code is used as an encoding method and a decoding method for detecting an error in reproduction or reception data. This is general, and an example of the apparatus is shown in FIG. For simplification of description, a 16-bit cyclic redundancy check code of generator polynomial G (X) = X ¹⁶ + X ¹² + X ⁵ +1 which is commonly used will be taken as an example. In FIG. 17, 170 is an input terminal for binary data, 171 is an exclusive OR gate, 17
2 is a latch, 173 is an initial value setting terminal, 174 is a clock input terminal, 175, 176 and 177 are switches, 17
Reference numeral 8 is an output terminal, 179 is an error determination circuit, and 180 is an error determination output terminal. The principle of error detection is well known and will be briefly described. At the time of recording or transmission communication, first, the switches 1, 2, and 3 are connected to the B side to set initial values. Next, the switches 1 and 2 are connected to the A side, and the information data to be recorded or transmitted is inputted as serial binary data to the input terminal 170, and the bit number of the input data is inputted in the internal circuit. It is shifted in synchronization with the clock. This corresponds to dividing the input data by the generator polynomial. At this time, the data finally obtained by the circuit of FIG. 17 and obtained at each latch output corresponds to the remainder obtained by the division. This is generally called parity. The input data is taken out from the output terminal 178 through the B terminal of the switch 3. On the other hand, this parity is recorded or transmitted continuously after the information data by connecting the switches 1 and 2 to the B terminal again and the switch 3 to the A terminal. During reproduction or reception, this information data and parity data are input to the input terminal 170 of FIG.
Are input in the order of reproduction or reception, and are shifted by the number of bits of information data and parity data. At this time, as a result of the final shift, if the outputs of the latches are all 0 in the error determination circuit 179 of FIG. 17, that is, if the result of division is divisible,
It is determined that there is no error, and if a non-zero value is obtained in any latch output, it is determined that an error exists. This error determination result is taken out from the error determination output terminal 180.
As a result, the presence or absence of an error is detected during reproduction or reception.

[0003]

As described above, the prior art is as follows.
Error detection was performed as binary data, but recently, data is often processed in byte units, and it is necessary to convert binary data to byte data and vice versa each time. However, there is a problem in that an extra circuit is required for that, and the timing is shifted each time conversion is performed.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and encoding is performed by a byte data input means, an exclusive OR circuit block means, and a plurality of sets with a set or reset. It is provided with a latch circuit means, a selection circuit means, and a parity data output means.

Decoding is performed by input means of byte data,
An exclusive OR circuit block means, a plurality of latch circuit means with set or reset, an error judgment circuit means, and an error judgment output means are provided.

[0006]

According to the present invention, by adopting the above-mentioned configuration, it is possible to detect an error in the byte unit data without using serial / parallel conversion or parallel / serial conversion while using the error detection code for binary data. There is an effect that can provide the method and the device.

Further, by using both the binary error detection code and the byte data error detection code,
There is also an effect that error detection can be performed with the binary data or the byte data. Further, by using both of them together, there is an effect of improving the reliability of error determination.

[0008]

EXAMPLES Specific examples will be described in detail below.

First, the first embodiment will be described. This embodiment relates to an encoding method of an error detecting method using an error detecting code of a generator polynomial in binary format.

FIG. 1 is an explanatory view of the principle of an error detection coding / decoding apparatus using a (shortened) cyclic code according to the present invention, and FIG. 2 is an operation state diagram of the error detection coding / decoding apparatus of FIG. ,
FIG. 3 is an operation state diagram of the special case of FIG. In Figure 1,
Reference numeral 1 is a data input terminal, 2, 3, 4 are switches, 5 is a coefficient unit, 6 is a latch, 7 is an exclusive OR circuit, 8 is an initial value setting terminal, 9 is a clock input terminal, and 10 is an error judgment. circuit,
Reference numeral 11 is an error determination output terminal, and 12 is a data output terminal.

First, a method of generating parity data for error detection during recording on a recording medium or during transmission communication during transmission communication will be described. Next, a parity generation method for binary data will be described as byte data. The principle for converting to a parity generation method for the following will be described. Prior to explanation, each data is polynomialized and defined as follows.

Information polynomial: D (X) = d _n X ⁿ + d _n-1
X ^n-1 + d _n-2 X ^n-2 + ... + d ₂ X ² + d ₁ X + d ₀ Generator polynomial: G (X) = X ^m + g _m-1 X ^m-1 + g _m-2 X
^m-2 + ...- + g ₂ X ² + g ₁ X + g ₀ quotient polynomial: Q (X) remainder polynomial: R (X) = r _m-1 X ^m-1 + r _m-2 X ^m-2 + ・
・ ・ ・ + R ₂ X ² + r ₁ X + r ₀ Transmission polynomial: U (X) = x ^m · D (x) + R (X) where n and m are integer multiples of 8 and n> m for binary data input. Previously, switch 1, switch 2 and switch 3 are connected to the B side. In that state, the initial value of each latch 6 is set to 0 or 1 by the initial value setting terminal 8. next. The switch 1 and the switch 2 are connected to the A side. In this state, the information data is input from the data input terminal 1 to the error detection encoding / decoding device, that is, the parity generating device as binary data, and is synchronized with the data of the clock input terminal 9. The data is shifted by the number of bits of the information data by the clock, and finally the data obtained at each latch output is used as the parity. During this time, the information data is taken out from the data output terminal 12 through B of the switch 3 and recorded or transmitted for communication. On the other hand, with respect to the parity data, when the shift is completed, the switch 1 and the switch 2 are switched to the B side, the switch 3 is switched to the A side, and the clock corresponding to the number of bits of the parity data is passed through the A of the switch 3. The data is taken out from the data output terminal 12 and recorded or transmitted for communication.

In the present invention, in order to capture the information data as byte-unit data, first, the result of inputting 8 bits of binary data is obtained. In FIG. 1, 8 bits from the upper bit of the information polynomial, that is, d _{n to} d _n-7 are sequentially input to the data input terminal 1, and the result of shifting 8 times is obtained. Therefore, as shown in FIG. 2, the latch outputs for each shift are transferred from the upper side from R _m-1 (i) to R ₀ (i).
And Further, each latch can be preset to 0 or 1 by the initial value setting terminal 8 before the calculation is started, and its initial value is set to N _{n-1 to} N ₀ from the higher order side. Also,
In FIG. 1, the exclusive OR output of the highest-order latch output and the input data is Y (i). Here, i represents the number of shifts. FIG. 2 is a table showing each latch output for each shift. The result of shifting 8 times is shown in Fig. 2.
It is obtained by successively substituting the result of each shift number into each latch output of the eighth time. Thereafter, when the next 1-byte data is input as the information data, each of the above R _m-1 (8) to R ₀ (8) is initialized to the initial value N _{m-1 to} N _0.
Then, the same calculation may be performed. Hereafter, input data
If the data is L bytes, it is sufficient to repeat the calculation. Finally, R _m-1 (8) to R ₀ (8) obtained at each latch output is the remainder and becomes the parity.

Next, the explanation will be made simpler and more concrete.
To generate G (X) = X¹⁶+ X¹²+ X^Five+
1, 1 byte of information polynomial, that is, D (X) = d₇Xⁿ+
d₆X ^n-1+ D_FiveX^n-2+ D_FourX^Four+ D₃X³+ D₂X²+ D₁X
+ D₀ And the output of each latch is shown in Fig. 3.
It From Fig. 3, each latch output is calculated as follows.
It

R15 (8) = R14 (7) = R13 (6) = R12 (5) = R11 (4) + R16 (5) = R10 (3) + R15 (4) + d3 = R9 (2) + R14 (3) + D3 = R8 (1) + R13 (2) + d3 = R7 (0) + R12 (1) + d3 = N7 + R11 (0) + R16 (1) + N11 + R15
(0) + d7 + d3 = d7 + d3 + N15 + N11 + N7 R14 (8) = d6 + d2 + N14 + N10 + N6 R13 (8) = d5 + d1 + N13 + N9 + N5 R12 (8) = d7 + d4 + d0 + N15 + N12 + N
8 + N4 R11 (8) = d6 + N14 + N3 R10 (8) = d5 + N13 + N6 R9 (8) = d4 + N12 + N1 R8 (8) = d7 + d3 + N15 + N11 + N0 R7 (8) = d7 + d6 + d2 + N15 + N14 + N
10 R6 (8) = d6 + d5 + d1 + N14 + N13 + N
9 R5 (8) = d5 + d4 + d0 + N13 + N12 + N
8 R4 (8) = d4 + N12 R3 (8) = d7 + d3 + N15 + N11 R2 (8) = d6 + d2 + N14 + N10 R1 (8) = d5 + d1 + N13 + N9 R0 (8) = d4 + d0 + N12 + N8 In the case of inputting the next data byte, the next 1 byte is used as the next data byte. The above respective R ₁₅ (8) to R ₀ (8) may be given as initial initial values N _{15 to} N ₀ and the same calculation may be performed. Hereinafter, if the input data is L bytes, the calculation may be repeated for that amount. Finally, R ₁₅ (8) to R obtained at each latch output
₀ (8) is the remainder and is the parity.

Next, a second embodiment will be described. The second embodiment relates to a decoding method for checking whether or not there is an error at the time of reproduction from a recording medium or at the time of reception in transmission communication, using an error detection code of a binary-type generator polynomial.

In this embodiment, the basic calculation method is the same as in the first embodiment. The switch 1 and the switch 2 are connected to the B side before the initial value is set, and the initial value is set in this state. After that, it is connected to the A side. In this state, the parity data as well as the information data is inputted from the data input terminal 1 as binary data to the error detection coding / decoding apparatus, that is, the apparatus shown in FIG. It is shifted by the number of bits of information data and parity data by a clock synchronized with the data, and finally the data obtained at each latch output is input to the error detection judgment circuit 10 and the result is erroneous. Output from the judgment output terminal 11.

In the present invention, the information data and the parity data are
In order to capture the data as byte-unit data, the result of inputting 8 bits of binary data is obtained as in the first embodiment. Further, thereafter, information data and parity data
Repeat operation for the number of bytes of data. When the following 1-byte data is input as information data, each of the above R _m-1 (8) to R ₀ (8) is given as the initial value N _{m-1 to} N ₀ , The same calculation is performed as in the first embodiment. If all the error detection determination data is 0, it is determined that there is no error, and if it is non-zero, it is determined that there is an error.

Next, a third embodiment will be described. The third embodiment relates to an example of the encoding device of the first embodiment. FIG. 4 shows an example of the apparatus of this embodiment, and the operation will be described below with reference to FIG. In FIG. 4, 41 is a data input signal terminal, 42 is an exclusive OR circuit block, 43 is a latch, 44 is a clock input terminal, 45 is an initial value setting terminal,
Reference numeral 46 is a selection circuit, 47 is a selection control signal input terminal, and 48 is a parity data output terminal.

First, prior to the input of information data, the initial value 0 or 1 is set to Nm to N0 by the initial value setting terminal 45 in the latch 43 composed of m bits.
Next, one byte of information data in byte units is input from the input terminal 41. Each bit of the input data and each output of the m-bit latch 43 are determined by a generator polynomial, that is, an exclusive OR circuit block 42 in a relation obtained as a result of shifting by 8 bits in a binary data processing type error detection circuit. Are assembled and provided as an input to the m-bit latch 43. In this state, the clock is shifted by the clock synchronized with the input data from the clock input terminal 44. When the next 1-byte data is applied to the data input terminal 41, the m-bit latch is also shifted once by the byte unit clock.
After that, the same processing is repeated for the input data. After the final shift, the m-bit latch output is sequentially selected by the selection circuit 46 from the upper side or the lower side in 8-bit units and output from the parity data output terminal 48.

In FIG. 5, the generator polynomial is G (X) = X ¹⁶ +
It is a specific circuit example for X ¹² + X ⁵ +1. In FIG. 5, 51 is a data input signal terminal, 52 is an exclusive OR circuit block, 53 is a latch, 54 is a clock input terminal, 55 is an initial value setting terminal, 56 is a selection circuit, 57 is a selection control signal input terminal, Reference numeral 58 is a parity data output terminal. It is needless to say that only the exclusive OR circuit 52 is described with reference to FIG. The exclusive OR circuit 52 of FIG. 5 is the formula of R ** (8) obtained in the first embodiment itself, and the symbol + in the formula represents a two-input exclusive OR circuit. This is also the same as before, so it is omitted.

Next, a fourth embodiment will be described. In the present embodiment, the third embodiment relates to an encoding device of an error detecting method in which serial data is input as it is while 8-bit parallel data is input.

This will be described with reference to FIG. In FIG. 6, 6
1 is a data input terminal, 62 is an 8-bit shift register, and 63 is a bit clock input terminal. The other components having the same functions as those in FIG. 4 are represented by the same numbers.

The difference from the third embodiment is that the third embodiment inputs parallel byte data, whereas the present embodiment inputs serial binary data. First, serial binary data is input from the data input terminal of 61 to the shift register of 62 in synchronization with the clock of the bit clock input terminal of 63. When 8-bit data is fetched from the beginning of the information data, serial-parallel conversion is performed with a byte clock. The subsequent operation is similar to that of the third embodiment.

Next, a fifth embodiment will be described. The fifth embodiment relates to an example of the error detecting / decoding apparatus of the second embodiment. FIG. 7 shows an example of the apparatus of this embodiment, and the operation will be described below with reference to FIG. In FIG. 7, 41 is a data input signal terminal, 42 is an exclusive OR circuit block,
43 is a latch, 44 is a clock input terminal, 45 is an initial value setting terminal, 71 is an error judgment circuit, and 72 is an error judgment output terminal. In FIG. 7, the same functional blocks as in FIG. 4 are assigned the same numbers.

First, before inputting, the m-bit latch 4
An initial value of 0 or 1 is set to 3 in Nm to N0. Next, byte-by-byte input data is input to the input signal terminal 41
1 byte is input. Each bit of input data and m
Each output of the bit latch is determined by the generator polynomial,
That is, an exclusive OR circuit is built in the relation obtained as a result of shifting by 8 bits in the binary data processing type cyclic code error detection coding apparatus, and is given as an input to the m-bit latch 43. In this state, a clock synchronized with the data is shifted by one clock from the clock input terminal 44.
When the next 1-byte data is applied to the input terminal 41, the m-bit latch is also shifted once by the byte unit clock. After that, the same processing is repeated for the input data and the parity data. After the final shift, the error judgment circuit 71 checks whether or not the m-bit latch outputs are all 0. If all the m-bit latch outputs are 0, it is determined that there is no error, and otherwise, it is determined that there is an error, and the determination result is output from the error determination output terminal 72.

In FIG. 8, the generator polynomial is G (X) = X ¹⁶ +
It is a specific device example in the case of X ¹² + X ⁵ +1. In FIG. 8, 51 is a data input signal terminal, 52 is an exclusive OR circuit block, 53 is a latch, 54 is a clock input terminal, 55 is an initial value setting terminal, 81 is an error determination circuit, and 82.
Is an error determination output terminal. In FIG. 8, the same functional blocks as in FIG. 5 are assigned the same numbers. In FIG. 8, the error decision circuit 81 outputs 0 for all 16-bit latch outputs.
In order to determine whether or not it is composed of an exclusive logic circuit and an OR circuit.

Next, a sixth embodiment will be described. In this embodiment, the second embodiment is an 8-bit parallel data
The present invention relates to a decoding device of an error detecting method in which serial data is input as it is while data is input.

This will be described with reference to FIG. In FIG. 9, 9
Reference numeral 1 is a data input terminal, 92 is an 8-bit shift register, and 93 is a bit clock input terminal. The other components having the same functions as those in FIG. 7 are represented by the same numbers.

The difference from the second embodiment is that the second embodiment inputs parallel byte data, whereas the present embodiment inputs serial binary data. First, serial binary data is input from the data input terminal of 91 to the shift register of 92 in synchronization with the clock of the bit clock input terminal of 93. When 8-bit data is fetched from the beginning of the information data, serial-parallel conversion is performed with a byte clock. The subsequent operation is similar to that of the third embodiment.

Next, a seventh embodiment of the present invention will be described. In general, either an error detection code generated by a generator polynomial for serial binary data or an error detection code generated by a generator polynomial for byte data is used as the error detection code. However, in applications where it is only necessary to determine whether or not there is an error without requiring error correction, an error detection method for serial binary data is mostly used.

In the seventh embodiment, as an error detection method, both an error detection code generated by a serial binary data type generator polynomial and an error detection code generated by a byte data type generator polynomial are used. , The former applies to the information data, the latter applies to the information data and the parity generated by the former, and relates to the encoding device when either or both of them are used according to the convenience of the system. .

This embodiment will be described with reference to FIG. In FIG. 10, both the parity data generated by the generator polynomial for serial binary data and the parity data generated by the generator polynomial for byte data are applied to the error detection of the physical address portion of the optical disk. It is a block diagram of a sector in the case.

In FIG. 10, 101 is a user data area, 102 is an error correction code area, 103 is a sector head identification code, 104 is a physical or logical address area, 1
Reference numeral 05 is physical or logical address data, 106 is the first error detection parity by a binary format generator polynomial, 1
Reference numeral 07 is a second error detection parity by a byte format generator polynomial, 108 is an auxiliary data area, and 109 is a resynchronization signal.

FIG. 11 is a diagram of an encoding device according to this embodiment. In FIG. 11, 111 is a system controller.
La, 112 is a parallel-serial conversion means, 113 is a serial-parallel conversion means, 114 is a first error detection coding means, 115 is a second error detection coding means, 116
Is a first memory means, 117 is a second memory means, 11
8 is a user data input terminal, 119 is an input I / F, 12
Reference numeral 0 is a modulation means, 121 is a resynchronization signal generation means, and 122 is an output terminal.

In the embodiment of the present invention, at the time of encoding, the identification code 103 representing the beginning of the sector is first generated by the system controller 111, and the first memory means 116 is used.
Memorized in. Next, a track of the optical disk or the like, a physical address indicating the sector number, or logical address data 105 indicating the sector number from the inner circumference to the outer circumference is generated by the system controller 111, and the second memory means 1 is generated.
Stored in 17. On the other hand, this is converted into serial binary data by the parallel-serial conversion means 112. Next, this binary data is regarded as an information polynomial as described in the first embodiment, and the first binary is generated using the serial binary format generator polynomial also described in the first embodiment. The first error detection parity 106 is generated by the error detection encoding means 114. The first error detection parity is parallelized by the serial-parallel conversion means 113 and stored in the second memory means 117 following the physical or logical address data. Next, the physical or logical address and the first error detection parity are read from the second memory means 117, and the second error detection encoding means 115 reads the physical or logical address data and the first error detection parity. The error detection parity is regarded as the information polynomial, the second error detection parity 107 is generated by the generation polynomial in the byte format, and is stored in the second memory means 117. Next, the physical or logical address data, the first error detection parity data and the second error detection parity data are read from the second memory means 117 and stored in the first memory means 116. . Here, as the second error detecting code, a generally well-known Lead Solomon code is used. For example, primitive polynomial m (X) = X
⁸ + X ⁴ + X ³ + X ² +1 as a generator polynomial, G (X) =
X ² + α ²⁵ X + α and the like. Next, the auxiliary information data 108 of the user data of the sector is transferred to the system controller 1
11 and stored in the first memory means 116. Next, the user data is transferred from the user data input terminal 118 to the first memory means 1 via the input I / F means 119.
16 are stored. Next, for example, the data for one horizontal row excluding the error correction code area 102 in FIG. Is located in. Next, the same calculation is performed in all the rows of FIG. Next, from the first memory means 116, the vertical 1 in FIG.
The data for each column is read out and modulated by the modulation means 120, for example, by a run length code or the like. The modulation means 120 includes a parallel-serial conversion function. Finally, the re-synchronization signal generating means 121 provides the re-synchronization signal 109 for each column in FIG. Error detection parity, second error detection parity, auxiliary information, user data, resynchronization signal, user data, ..., resynchronization signal, error correction parity,
.. are serialized in this order, extracted from the output terminal 122, and recorded.

Now, the coding means for the second error detection code will be described with reference to FIG. In FIG. 12, for the sake of simplicity, a Lead Solomon code with a minimum inter-code distance = 3 is used.

In FIG. 12, 123 is a data input terminal, 124 is an exclusive OR circuit, 125 is a coefficient unit, 12
6 is a latch, 127 is a clock input terminal, 128 is an initial value setting terminal, 129 is an error detection determination means, and 130 is an error determination output terminal. As is clear from FIG. 12, the basic operation is the same as in FIG. The difference is that the input data is in units of bytes, and the coefficient unit is not a simple AND circuit but a circuit that constitutes an element of α ⁿ . It goes without saying that the detailed operation is described.

Next, an eighth embodiment of the present invention will be described. The eighth embodiment relates to an error detecting / decoding device for a parity generated by a generator polynomial in the binary format of the physical or logical address data encoded in the seventh embodiment.

This embodiment will be described with reference to FIG. FIG. 13 shows a case where both the parity data generated by the generator polynomial for binary data and the parity data generated by the generator polynomial for byte data are applied to the error detection of the physical address portion of the optical disk. Alternatively, it is a decoding device for an error detection method of logical address data.

In FIG. 13, 131 is a reproduction data input terminal, 132 is a serial channel bit data, 13
Reference numeral 3 is a resynchronization signal detecting means, 134 is a demodulating means, 135 is bit serial data, 136 is a sector head identification code detecting means, 137 is an error detecting / decoding means, and 138 is an error judging output terminal.

In the embodiment of the present invention, the serial channel bit data 132 reproduced from the optical disk, which is inputted from the reproduction data input terminal 131, is inputted to the re-synchronization signal detecting means 133 to compare the patterns. Detects the resynchronization signal. Next, the demodulation means 134 demodulates, for example, run length modulation data or the like into bit serial data 135. Next, the sector head identification code detecting means 136 identifies the sector head. The output of this sector head identification code detection means is the first in binary format.
The error detection / decoding means 137 is initialized. The succeeding physical or logical address data is input to the first error detecting / decoding means 137, and the presence or absence of an error is checked. The operation of the error detection / decoding means 137 has already been described with reference to FIG. The parts other than the error detection of the physical or logical address data in this embodiment are not directly related to this embodiment and will be omitted.

Next, a ninth embodiment of the present invention will be described. The ninth embodiment relates to a decoding device for a parity error detection method generated by a byte-form generator polynomial of physical or logical address data of the data encoded in the seventh embodiment. This embodiment will be described with reference to FIG.

In FIG. 14, both the parity data generated by the generator polynomial for binary data and the parity data generated by the generator polynomial for byte data are applied to the error detection of the physical address portion of the optical disk. This is a decoding device of another error detection method of physical or logical address data in the case of performing.

In FIG. 14, reference numeral 140 is a reproduction data input terminal, 141 is a serial channel bit data, and 14 is a serial channel bit data.
2 is a re-synchronization signal detecting means, 143 is a demodulating means, 144 is a sector head identification code detecting means, 145 is a serial-parallel converting means, 146 is an error detecting / decoding means, 147.
Is an error determination output terminal.

In the embodiment of the present invention, the serial channel bit data 141 from the optical disk, which is inputted from the reproduction data input terminal 140, is inputted to the resynchronization detecting means 142, and the resynchronization signal is obtained by the pattern comparison. Is detected.
Next, the demodulation means 143 demodulates, for example, run length modulation data. Next, the sector start identification code
The head of the sector is identified by the mode detecting means 144. Next, the serial-parallel conversion means 145 uses the parallel data.
Converted to data. Next, by the output of the sector head identification code detecting means, the second error detecting and decoding means 14 in the byte format is formed.
6 is initialized. The following physical or logical address data and error detection parity in binary format are input to the error detection decoding means 146, and the presence or absence of an error is checked. Here, as the error detection code, generally well-known Lead Solomon code is used. The basic operation of error detection is the same as in FIG.

Next, a tenth embodiment of the present invention will be described. The tenth embodiment is the first physical or logical address data of the data encoded in the seventh embodiment.
The present invention relates to a decoding device that uses both the error detection method of (2) and the second error detection method.

This embodiment will be described with reference to FIG. Figure 1
5, 131 is a reproduction data input terminal, 132 is a serial channel bit data, 133 is a resynchronization signal detecting means, 134 is a demodulating means, and 135 is a bit serial data.
Data, 136 is a sector head identification code detecting means, 137 is a first error detecting / decoding means, 145 is a serial-parallel converting means, 146 is a second error detecting means, 150 is a total error determining means, and 151 is This is an error judgment output terminal. The same numbers are given to those having the same functions as those in FIGS.

In this embodiment, Embodiments 8 and 9 are used together, and by using them together, the reliability of error detection is improved. The operation of each means has already been described, so it is not necessary to explain it. The comprehensive error determining means 151 determines that there is an error unless both the first error detection result and the second error detection result are error-free.

Next, an eleventh embodiment of the present invention will be described. The eleventh embodiment is the second physical or logical address data of the data encoded in the seventh embodiment.
The present invention relates to a decoding device for the error detection method. This embodiment will be described with reference to FIG.

In FIG. 16, 160 is a reproduction data input terminal, 161 is a serial channel bit data, 16
2 is a resynchronization signal detecting means, 163 is a demodulating means, 164 is a serial-parallel converting means, 165 is a memory means, 1
Reference numeral 66 is a system control means, and 167 is an error determination output terminal.

In the embodiment of the present invention, the serial channel bit data reproduced from the optical disk, which is inputted from the reproduction data input terminal 160, is resynchronized signal detecting means 1.
The signal is input to 62 and a resynchronization signal is detected by pattern comparison. Next, the demodulation means 163 demodulates, for example, run length modulation data. Next, the demodulated data is byte data by the serial-parallel conversion means 164.
Converted to data. The data converted into byte data is stored in the memory means 165 as shown in FIG. Next, in the system controller 166, the physical or logical address data and the first error detection parity are read from the memory means 165, and the same operation as the circuit of FIG. 12 is executed by calculation. Since the address data for the operation is about 5 bytes at most, it does not burden the CPU of the system control. In this way, by using a byte-form generator polynomial as the error detection code, it is possible to substitute the function of error detection in the system control without providing any special error detection means.

[0053]

As described above, according to the present invention, the input means of the byte data, the circuit block means composed of the exclusive OR gate, the plurality of latch circuit means with set or reset, and the error judgment means. , Equipped with error determination output means,
It is possible to provide a method capable of error detection using byte-unit data without serial / parallel conversion or parallel / serial conversion, while using an error detection code for binary data.

By using both the binary error detection code and the byte data error detection code,
It is possible to provide a method capable of detecting an error even if it is the binary data or the byte data.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an encoding / decoding principle of an error detecting method according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a relationship between input data and each latch output in an explanatory diagram of the principle of encoding and decoding in the error detecting method according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a relationship between input data and each latch output in an explanatory diagram of an encoding / decoding principle of an error detection method in which a generator polynomial is limited in the first embodiment of the present invention.

FIG. 4 is a diagram of an error detection coding device according to a third embodiment of the present invention.

FIG. 5 is an error detection coding device diagram in which the generator polynomial is limited in the third embodiment of the present invention.

FIG. 6 is a diagram of an error detection coding device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram of an error detection / decoding device according to a fifth embodiment of the present invention.

FIG. 8 is a diagram of an error detecting / decoding apparatus in which the generator polynomial is limited in the fifth embodiment of the present invention.

FIG. 9 is a diagram of an error detection / decoding device according to a sixth embodiment of the present invention.

FIG. 10 is a block diagram of a sector according to the embodiment of the present invention.

FIG. 11 is a diagram of an encoding device according to a seventh embodiment of the present invention.

FIG. 12 is a diagram of an error detection coding / decoding device by a byte format generator polynomial in a seventh embodiment of the present invention.

FIG. 13 is a diagram of an error detection / decoding device according to an eighth embodiment of the present invention.

FIG. 14 is a diagram of an error detecting / decoding apparatus according to a ninth embodiment of the present invention.

FIG. 15 is a diagram of an error detection / decoding device according to a tenth embodiment of the present invention.

FIG. 16 is a diagram of an error detection / decoding apparatus according to an eleventh embodiment of the present invention.

FIG. 17 is a diagram showing an example of a conventional error detection encoding / decoding device.

[Explanation of symbols]

1 Input Terminals 2, 3, 4, 175, 176, 177 Switches 5, 125 Coefficient Units 6, 43, 53, 126, 172 Latches 7, 124, 171 Exclusive-OR Circuits 8, 45, 55, 128, 173 Initial Value setting terminals 9, 44, 54, 127, 174 Clock input terminals 10, 71, 81, 179 Error determination circuit 11, 72, 85, 130, 138, 147, 151,
167, 180 Error judgment output terminal 12, 178 output terminal 41, 51 Data signal input terminal 42, 52 Exclusive OR circuit block 46, 56 Selection circuit 47, 57 Selection control signal input terminal 48, 58 Parity data output Terminals 61, 91 Data input terminal 62, 92 Register 63, 93 Bit clock input terminal 101 User data area 102 Apologetic correction code area 103 Sector start identification code 104 Physical or logical address area 105 Physical or logical address Data 106 First error detection parity 107 Second error detection parity 108 Auxiliary information data area 109 Resynchronization signal 111, 166 System controller 112 Parallel-serial conversion means 113, 145, 164 Serial-parallel conversion Means 114 First Error Detection Encoding means 115 Second error detection encoding means 116 First memory means 117 Second memory means 118 User data input terminal 119 Input I / F 120 Modulating means 121 Resynchronization signal generating means 129 Error detection judgment Means 131, 140, 160 reproduction data input terminal 132, 141, 161 serial channel bit data 133, 142, 162 resynchronization signal detection means 134, 143, 163 demodulation means 135 bit serial data 136, 144 sectors Head identification code detecting means 137 First error detecting / decoding means 146 Second error detecting / decoding means 150 Total error determining means 165 Memory means

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11B 20/18 544 Z 8940-5D 574 N 8940-5D

Claims (12)

[Claims] 1. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Regarding the error detection coding method, the initial value R is set by the initial value setting means.
_{m-k + 1}(0) = N_{m-k + 1}N_{m-k + 1}Is initially 0 or 1
After the value is set, the information data is changed to byte data.
8 bits from the upper bit of the transmission polynomial
Minutes, that is, d_n~ D_n-7Is the result of dividing by the generator polynomial
Find, the coefficient of the remainder polynomial, R_m-1(8) = R
_m-2(7) + g_m-1・ Y (8), R_m-2(8) = R
_m-3(7) + g_m-2・ Y (8), R_m-3(8) = R
_m-4(7) + g_{m -Four}・ Y (8), ..., R₂(8) =
R₁(7) + g₁・ Y (8), R₁(8) = R₀(7) + g
₀・ Y (8), R₀(8) = Y (8), Y (8) = R_m-1
(7) + d ₀, Where Y (i) = R_m-1(I) +
d_8-i, (I = 1, 2 ... 8), R_mk(I) = R
_mk-1(I-1) + g_mk・ Y (i), (k = 1, 2, ...
・ ・) Input data di and initial value N_{m-k + 1}Expressed as
Then, regarding this remainder result as the initial value, the next input data
-D_n-8~ D_n-15And again the exclusive theory corresponding to the above remainder
This operation is composed of Riwa, and this operation is input. Byte of binary data
Repeat for a few minutes, and order the results in byte units from the high-order side.
Incorrect binary format due to subsequent retrieval
Generates detection parity by byte format parallel operation
An error detection coding method characterized by the following. 2. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Regarding error detection coding method, 8-bit parallel data
di (i = 0, 1, ... 7) input terminal and R
_{m-k + 1}(0) = N_{m -k + 1}(N_{m-k + 1}Is an initial value of 0 or 1)
M-bit with setting means and byte unit clock input terminal
Parallel latch and the m-bit parallel latch.
R by output output and input data di_m-1(8) = R
_m-2(7) + g_m-1・ Y (8), R_m-2(8) = R
_m-3(7) + g_m-2・ Y (8), R_m-3(8) = R
_m-4(7) + g_m-4・ Y (8), ..., R₂(8) =
R₁(7) + g₁・ Y (8), R₁(8) = R₀(7) + g
₀・ Y (8), R₀(8) = Y (8), Y (8) = R_m-1
(7) + d₀, Where Y (i) = R_m-1(I) +
d_8-i, (I = 1, 2 ... 8), R_mk(I) = R
_mk-1(I-1) + g_mk・ Y (i), (k = 1, 2, ...
..) exclusive OR circuit block having the relation
The output of this exclusive OR circuit block
As an input to the parallel latch, this m-bit parallel latch is used.
Select circuit that sequentially selects the output from the upper side by 8 bits
And the parity data for extracting the parity from this selection circuit.
It has a data output terminal and inputs input data in byte units.
Error by shifting the number of bytes by the latch
Error detection code characterized by generating detection parity
Method. 3. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Regarding error detection coding method, serial bit binary
Data input terminal and 8-bit serial-parallel conversion
Register means and R_{m-k + 1}(0) = N_{m-k + 1}(N_{m-k + 1}Is
0 or 1) Initial value setting means and byte unit clock input
M-bit parallel latch with input terminal
Input parallel latch output and input data after parallel conversion.
R i according to the data di (i = 0, 1, ..., 7)_m-1(8)
= R_m-2(7) + g_m-1・ Y (8), R_m-2(8) = R_m-3
(7) + g_m-2・ Y (8), R_m-3(8) = R_m-4(7)
+ G_m-4・ Y (8), ..., R₂(8) = R₁(7)
+ G₁・ Y (8), R₁(8) = R₀(7) + g₀・ Y
(8), R₀(8) = Y (8), Y (8) = R_m-1(7)
+ D₀, Where Y (i) = R_m-1(I) + d_8-i, (I
= 1, 2 ... 8), R_mk(I) = R_{mk -1}(I-1)
+ G_mk・ Y (i), (k = 1, 2, ...)
And an exclusive OR circuit block having
The output of the sum circuit block is output from the m-bit parallel latch.
Use this as an input and use this m-bit parallel latch output
A selection circuit for sequentially selecting every 8 bits and this selection time
The parity data output terminal that extracts the parity from the
Input, input data in serial binary units, and
Byte-to-parallel conversion with the right clock
By shifting the number of bytes by the latch,
Error detection characterized by generating error detection parity
Encoding method. 4. The generator polynomial for generating error detection parity according to claim 1, wherein G (X) = X ¹⁶ + X ¹² + X ⁵ +
1, the upper 1 byte of the information polynomial, that is, D * (X) =
d ₇ X ⁿ + d ₆ X ^n-1 + d ₅ X ^n-2 + d ₄ X ⁴ + d ₃ X ³ + d ₂ X ²
+ D ₁ X + d _0, and the initial value of the parallel latch is Ni (i = 15, 14, ..., 2, 1,
0) and the exclusive OR circuit block output from the upper side of the parallel latch R15 (8) = R14 (7) = R13 (6) = R12 (5) = R11 (4) + R16 (5) = R10 (3 ) + R15 (4) + d3 = R9 (2) + R14 (3) + d3 = R8 (1) + R13 (2) + d3 = R7 (0) + R12 (1) + d3 = N7 + R11 (0) + R16 (1) + N11 + R15
(0) + d7 + d3 = d7 + d3 + N15 + N11 + N7 R14 (8) = d6 + d2 + N14 + N10 + N6 R13 (8) = d5 + d1 + N13 + N9 + N5 R12 (8) = d7 + d4 + d0 + N15 + N12 + N
8 + N4 R11 (8) = d6 + N14 + N3 R10 (8) = d5 + N13 + N6 R9 (8) = d4 + N12 + N1 R8 (8) = d7 + d3 + N15 + N11 + N0 R7 (8) = d7 + d6 + d2 + N15 + N14 + N
10 R6 (8) = d6 + d5 + d1 + N14 + N13 + N
9 R5 (8) = d5 + d4 + d0 + N13 + N12 + N
8 R4 (8) = d4 + N12 R3 (8) = d7 + d3 + N15 + N11 R2 (8) = d6 + d2 + N14 + N10 R1 (8) = d5 + d1 + N13 + N9 R0 (8) = d4 + d0 + N12 + N8 A method for error detection coding. 5. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Regarding the error detection and decoding method, the initial value setting procedure of the internal latch
Initial value R in steps_{m-k + 1}(0) = N_{m-k + 1}N_{m-k + 1}Is 0
After the initial value is set to 1 or 1, the information data is
The upper bits of the transmission polynomial are
8 bits from the packet, that is, d_n~ D_n-7Divided by the generator polynomial
The result of the calculation is found, and the coefficient of the remainder polynomial, R
_m-1(8) = R_m-2(7) + g_m-1・ Y (8), R
_m-2(8) = R_m-3(7) + g_m-2・ Y (8), R
_m-3(8) = R_{m- Four}(7) + g_m-4・ Y (8)
., R₂(8) = R₁(7) + g₁・ Y (8), R₁(8)
= R₀(7) + g₀・ Y (8), R₀(8) = Y (8),
Y (8) = R _m-1(7) + d₀, Where Y (i) = R
_m-1(I) + d_8-i, (I = 1, 2 ... 8), R
_mk(I) = R_mk-1(I-1) + g_mk・ Y (i),
(K = 1, 2, ...) Input data di and initial value N
_{m-k + 1}Then, the remainder result is regarded as the initial value.
However, the next input data d_n-8~ D_n-15And again the above remainder
The exclusive OR corresponding to
Of input binary data composed of data and parity data
Repeated for the number of bytes, and if the result is all 0, it is an error.
Characteristic that it is determined that there is no error and the others are incorrect
Error detection decoding method. 6. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Regarding error detection and decoding method, 8-bit parallel data
di (i = 0, 1, ... 7) input terminal and R
_{m-k + 1}(0) = N_{m -k + 1}(N_{m-k + 1}Is an initial value of 0 or 1)
M-bit with setting means and byte unit clock input terminal
Parallel latch and the m-bit parallel latch.
R by output output and input data di_m-1(8) = R
_m-2(7) + g_m-1・ Y (8), R_m-2(8) = R
_m-3(7) + g_m-2・ Y (8), R_m-3(8) = R
_m-4(7) + g_m-4・ Y (8), ..., R₂(8) =
R₁(7) + g₁・ Y (8), R₁(8) = R₀(7) + g
₀・ Y (8), R₀(8) = Y (8), Y (8) = R_m-1
(7) + d₀, Where Y (i) = R_m-1(I) +
d_8-i, (I = 1, 2 ... 8), R_mk(I) = R
_mk-1(I-1) + g_mk・ Y (i), (k = 1, 2, ...
..) exclusive OR circuit block having the relation
The output of this exclusive OR circuit block
As an input to the parallel latch, this m-bit parallel latch is used.
If all J outputs are 0, no error is found, otherwise, there is an error.
Error determination circuit that determines the error and the error that outputs this error determination result.
It has an information judgment output terminal, and is provided with information data and parity data.
Input data consisting of
Error detection by shifting with the latch
An error detection decoding device characterized by the above. 7. Information polynomial: D (X) = d_nXⁿ+ D_n-1X
^n-1+ D_n-2X^n-2+ ... ・ + d₂X²+ D₁X + d₀,Raw
Polynomial polynomial: G (X) = X^m+ G_m-1X^m-1+ G_m-2X ^m-2+
... + g₂X²+ G₁X + g₀, Quotient polynomial: Q (X),
Remainder polynomial: R (X) = r_m-1X^m-1+ R_m-2X^m-2+ ...
・ ・ ＋ r₂X²+ R₁X + r₀, Transmission polynomial: U (X) = x
^mD (x) + R (X), where n and m are integers of 8
By a binary cyclic code defined by n> m
Error detection and decoding method, serial bit binary
Data input terminal and 8-bit serial-parallel conversion
Register means and R_{m-k + 1}(0) = N_{m-k + 1}(N_{m-k + 1}Is
0 or 1) Initial value setting means and byte unit clock input
M-bit parallel latch with input terminal
Input parallel latch output and input data after parallel conversion.
R i according to the data di (i = 0, 1, ..., 7)_m-1(8)
= R_m-2(7) + g_m-1・ Y (8), R_m-2(8) = R_m-3
(7) + g_m-2・ Y (8), R_m-3(8) = R_m-4(7)
+ G_m-4・ Y (8), ..., R₂(8) = R₁(7)
+ G₁・ Y (8), R₁(8) = R₀(7) + g₀・ Y
(8), R₀(8) = Y (8), Y (8) = R_m-1(7)
+ D₀, Where Y (i) = R_m-1(I) + d_8-i, (I
= 1, 2 ... 8), R_mk(I) = R_{mk -1}(I-1)
+ G_mk・ Y (i), (k = 1, 2, ...)
And an exclusive OR circuit block having
The output of the sum circuit block is output from the m-bit parallel latch.
As an input, this m-bit parallel latch output is all 0
If there is no error, otherwise there is an error judgment
Circuit and error judgment output terminal that outputs this error judgment result
And input data consisting of information data and parity data.
Input the data in serial binary units and byte clock
Serial to parallel conversion with byte clock with byte clock
Error detection is performed by shifting the latch for a few minutes.
An error detecting and decoding device characterized by the above. 8. As the error detecting method, both of the error detecting code generated by the generator binary polynomial of the serial binary data format and the error detecting code generated by the generator polynomial of the byte data format are used in the former case. -The latter applies to the information data and the parity generated by the former, and relates to the encoding device when either or both of them are used according to the convenience of the system. First, an identification code representing the beginning of a sector is generated by the system controller and stored in the first memory means, and then a track of an optical disk or the like, a physical address representing the sector number, or from the inner circumference to the outer circumference. The logical address data representing the sector numbers up to are generated by the system controller and stored in the second memory means, while the parallel-serial conversion means stores the logical address data. Serialized into binary data, then consider this binary data as an information polynomial,
Using the generator polynomial of the serial binary format, the first error detection coding means generates the first error detection parity, and then the first error detection parity is parallelized by the serial-parallel conversion means, The physical or logical address data is stored in the second memory means subsequently, and then the physical or logical address and the first error detection parity are read from the second memory means to obtain the second error detection code. The conversion means regards the physical or logical address data and the first error detection parity as an information polynomial, generates a second error detection parity by a byte-form generator polynomial, and stores it in the second memory means. Next, the physical or logical address data, the first error detection parity data and the second error detection parity data are read from the second memory means, and the first memory is read. Stored in the re unit, wherein, as the second error detection code, generally well-known Li - Dosoromon code (e.g., a primitive polynomial ^{m (x) = X 8 +} X 4 +
X ³ + X ² +1 and G (X) = X ² + α as a generator polynomial
²⁵ X + α, α is an element of GF (2 ⁸ ), and then
The auxiliary information data of the user data of the sector is generated by the system controller and stored in the first memory means, and then the user data is input from the user data input terminal I / I. Store in the first memory means via F means, then generate error correction parity, store in the first memory means, and then
Data is sequentially read from the first memory means and modulated by the modulating means. This modulation means includes a parallel-serial conversion function, and finally, a resynchronization signal generating means applies a resynchronization signal to the resynchronization signal, sector head identification code, physical or logical address data, and first Error detection parity of
Second error detection parity, auxiliary information, user data, resync signal, user data, ..., Resync signal,
An error detection coding device characterized by serializing in the order of error correction parity, ... And extracting from an output terminal. 9. An error detecting and decoding apparatus for serial binary data format of data encoded by both a generator polynomial of serial binary data format and a generator polynomial of byte data format. The serial channel bit data input from the input terminal and reproduced from the optical disk is input to the resynchronization signal detecting means, the resynchronization signal is detected by pattern comparison, and then the demodulation means outputs the modulation data. It demodulates to bit serial binary data, and then the sector start identification code
The head of the sector is identified by the code detection means, and this identification code
The binary format error detection means is initialized by a code, the following physical or logical address data and serial binary format parity are input to this error detection means, and the presence or absence of an error is checked. An error detection / decoding method characterized by dividing data by a generator polynomial, and judging that there is no error if the remainders are all 0 and that there is an error otherwise. 10. An error detection decoding apparatus for byte data format of data encoded by both a generator polynomial of serial binary data format and a generator polynomial of byte data format, and reproducing data input. The serial channel bit data reproduced from the optical disk, which is input from the terminal, is input to the resynchronization detecting means, the resynchronization signal is detected by the pattern comparison, and then the demodulation means demodulates the modulation data. Then, the head of the sector is identified by the sector head identification code detecting means, the serial data is converted into byte data by the serial-parallel converting means, and then the sector head identifying code is detected. -Initialize the error detection means in byte format with the output of the error detection means, and input the following physical or logical address data and error detection parity in binary format into this error detection means, Check the presence of errors, error detection means,
An error detecting / decoding apparatus characterized by dividing received data by a generator polynomial, and judging that there is no error if the remainders are all 0 and otherwise. 11. An error detecting / decoding apparatus for data encoded by both a generator polynomial of serial binary data format and a generator polynomial of byte data format, which is input from a reproduction data input terminal. , The serial channel bit data reproduced from the optical disk is input to the resynchronization signal detecting means, the resynchronization signal is detected by pattern comparison, and then the demodulation means demodulates the modulation data to obtain the bit serial. Then, the head of the sector is identified by the head identification code detecting means of the sector, and the first error detecting means in the binary format and the first error detecting means in the byte format are output from the output of the sector identification code detecting means. The second error detecting means is initialized, and the following physical or logical address data and parity in serial binary format are input to the first error detecting means,
The first error detection means divides the received data by the generator polynomial, judges that there is no error, and judges that there is an error otherwise, and the serial data. Is converted into byte data by serial-parallel conversion means, and the subsequent physical or logical address data is converted.
Data and the first error detection parity in binary format are input to the second error detection means to check whether there is an error,
The second error detecting means divides the received data by the generator polynomial, judges that there is no error if the remainder is all 0, and judges that there is an error otherwise, and uses both of these error judgment results in combination, An error detection / decoding apparatus characterized by determining that there is no error only when both the error detection means result and the second error determination result indicate that there is no error, and otherwise. 12. A serial channel bit data reproduced from an optical disk, which is inputted from a reproduction data input terminal, is inputted to a resynchronization detecting means, a resynchronization signal is detected by pattern comparison, and next, The demodulation means demodulates the modulated data, the serial-parallel conversion means then converts the demodulated data into byte data, and the byte data is stored in the memory means. In addition, the system controller
The physical or logical address data from the memory means.
An error detection / decoding device characterized in that the error detection parity is read out and the system controller performs division by a generation polynomial in a byte format.