JPH07326658A - Semiconductor device and its controlling method - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which can realize the simplification of circuit structure necessary for element isolation and the reduction of consumption power and necessary circuit area. CONSTITUTION:A field plate 1 for element isolation of an MOS transistor Q1 formed on a substrate 12 is connected with the floating gate 2A of an MOS transistor Q2 for supplying power which is formed on the same substrate 12 and provided with a source 5, a drain 6, the floating gate 2A and a control gate 2B. In the semiconductor device, the potential due to the injection of charges to the field plate 1 is controlled by charge injection operation to the floating gate 2A of the MOS transistor Q2 for supplying power.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its control technique, and more particularly to a technique effectively applied to an element isolation structure, a memory cell structure and the like.

[0002]

2. Description of the Related Art A semiconductor device requires an element isolation structure for preventing a plurality of unit element structures formed on a semiconductor substrate from interfering with other unit element structures via the semiconductor substrate. Conventionally, as such an element isolation structure, for example, "LSI Handbook" P edited by Ohmsha Co., Ltd., published on November 30, 1984, edited by Institute of Electronics and Communication Engineers, P.
The following techniques have been known, as described in documents such as 129 to P133.

That is, (1) a device isolation method using LOCOS, (2) trench isolation, and (3) a plate electrode (field plate) is formed in the device isolation region, and a voltage is applied to the plate electrode via an external circuit. By doing so, the surface of the substrate is kept in an accumulation state to separate the elements.

[0004]

However, in the above-mentioned prior art, there is a problem that the isolation width is limited by the bird's beak in the element isolation by LOCOS of the above (1). Further, although the limitation of the isolation width is relaxed in the isolation by the trench isolation of (2) above,
Since the process of engraving the trench in the depth direction of the substrate is required, the difficulty of the processing process becomes relatively high.

In the separation method using the field plate described in (3) above, since the separation width depends on the processing accuracy of the field plate on the substrate, the separation width can be reduced by the photolithography technique. An extra circuit for constantly applying a voltage to the field plate is required, power consumption increases, an increase in the required circuit formation area due to the complexity of the structure is unavoidable, and the chip size becomes larger than necessary. Causes the problem.

An object of the present invention is to provide a semiconductor device capable of simplifying the circuit structure required for element isolation and further reducing power consumption and required circuit area.

Another object of the present invention is to provide a semiconductor device and its control technique capable of correcting variations in characteristics in the manufacturing process at any time.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the semiconductor device of the present invention is a MOS
Floating gate of MOS transistor by connecting element isolation electrode to floating gate of transistor and applying voltage to power supply pad or LSI pin which was previously formed by using probe etc. when wafer or chip is completed. It is configured such that charges are injected into the element isolation electrode via the.

Further, a cell plate which constitutes a memory cell is connected to the floating gate of a MOS transistor, and a power supply pad or LSI which is formed in advance by using a probe or the like when a wafer or a chip is completed.
By applying a voltage to the pin, the charge is injected into the floating gate of the MOS transistor connected to the cell plate.

As a material for the element isolation electrode or cell plate, for example, a ferroelectric or a multi-layer film of polysilicon and a ferroelectric can be used.

Further, the semiconductor device of the present invention uses a material having a work function difference from that of the substrate as the element isolation electrode material.

[0014]

According to the above-described semiconductor device of the present invention and the control technique thereof, the amount of charges injected into the element isolation electrode and the cell plate can be externally controlled by the voltage applied to the control gate. Therefore, an internal circuit for applying a voltage to the element isolation electrode and the cell plate is not required, and the circuit configuration is simplified and the chip area is reduced. Electric power is not consumed by the electrode for element isolation and the cell plate during the circuit operation. Further, the voltage of the element isolation electrode and the cell plate can be set to any value after the chip is completed. It is possible to correct variations in characteristics in the manufacturing process at the time of completion. Therefore, in a semiconductor device such as a memory element, it is possible to improve the characteristics and yield, and further, to remedy defects after manufacturing.

Further, since the element isolation is performed by utilizing the work function difference between the element isolation electrode material and the substrate material, a feeding circuit and a feeding structure are not required at all, and the circuit configuration is simplified.
A reduction in chip area is achieved.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a schematic sectional view schematically showing an example of the configuration of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a schematic plan view thereof.

On the substrate 12, a gate 8A laminated on the channel region 12a on the surface of the substrate 12 with a gate insulating film 8a interposed therebetween, and at a position sandwiching the channel region 12a and the gate 8A (electrode 8). Placed source 7
MOS consisting of A (electrode 7) and drain 9A (electrode 9)
The transistor Q1 is formed.

In the region surrounding the MOS transistor Q1 on the substrate 12, as illustrated in FIG.
A field plate 1 is provided on the surface of a substrate 12 with an insulating film 1a (for example, a film thickness of about 0.1 μm) being laminated, and the field plate 1 is provided with an appropriate potential from the outside to cause the MOS It functions to separate the transistor Q1 from other elements. The material of the field plate 1 can be, for example, a ferroelectric material, or a multilayer film of polysilicon and a ferroelectric material, or polysilicon.

Outside the region surrounded by the field plate 1, the channel region 12 on the surface of the substrate 12 is provided.
b, the first gate insulating film 2a and the second gate insulating film 2
The floating gate 2A and the control gate 2B are sequentially stacked via the gate electrode b, and the source 5 and the drain 6 are provided at positions sandwiching the channel region 12b.
Forming a power supply MOS transistor Q2. In the case of the present embodiment, this power supply M
A part of the field plate 1 is connected to the floating gate 2A of the OS transistor Q2.

The structure of the power supply MOS transistor Q2 is EE.
The structure is the same as that of the PROM, and the method of injecting charges into the floating gate 2A can be realized by the same method as that of the EEPROM.

An electrode 3, an electrode 4 and an electrode 2 are connected to the source 5, drain 6 and control gate 2B of the power supply MOS transistor Q2. These electrodes 3, 4 and 2 are connected to a lead pad (not shown) in the chip or an external connection terminal after the chip is completely sealed, and when the chip is completed in the wafer process or the chip is completely sealed. The voltage can be applied from the outside even in a later actual use state.

In the semiconductor device of this embodiment, the control of the electric potential of the field plate 1, that is, the injection of electric charges into the field plate 1 is performed as follows.

That is, for example, a voltage is applied so that a potential difference (for example, 5 V or more) is generated between the electrode 3 of the source 5 and the electrode 4 of the drain 6 of the power supply MOS transistor Q2, and hot carriers are generated at the drain end. Then, by applying a voltage to the electrode 2 of the control gate 2B, the amount of charges injected into the field plate 1 via the floating gate 2A is adjusted.

At this time, the power supply MOS transistor Q2
The voltage applied to the electrodes 2 to 4 of the n-channel MO
When element isolation between S transistors is performed, it is necessary to inject negative charges into the field plate 1.
A positive voltage will be applied to the electrode 2 of the control gate 2B. Similarly, in the case of element isolation between p-channel MOS transistors, since it is necessary to inject positive charges into field plate 1, a negative voltage is applied to electrode 2.

As described above, the electrodes 2 to 4 of the power supply MOS transistor Q2 can be applied with a desired voltage from the outside at the wafer state or at an arbitrary timing after the completion of the sealing. As illustrated in the flow chart, the electric potential of the field plate 1 can be externally controlled at an arbitrary timing in any of the manufacturing and inspection processes and the actual use state by the user.

As described above, according to the semiconductor device of this embodiment, the potential of the field plate 1 for element isolation is externally supplied at an arbitrary timing by injecting charges into the floating gate 2A of the power supply MOS transistor Q2. Since it is possible to control an arbitrary value with, it is possible to correct variations in characteristics of the field plate 1 and the like in the manufacturing process at the time of completion. In addition, the field plate 1 connected to the floating gate 2A
Since it is in an electrically floating state, an internal circuit for constantly applying a voltage to the field plate 1 is unnecessary, and it is possible to achieve simplification of the circuit structure and reduction of the chip area.
Further, during the circuit operation of the MOS transistor Q1 or the like, which is the target of element isolation, the field plate 1 does not consume power, and power consumption can be reduced.

Although FIG. 1 shows an example in which one MOS transistor Q1 is separated from other elements, as shown in FIG. 3, a plurality of active transistors each having a MOS transistor or the like are formed. The field plate 10 for separating the regions 11 from each other is connected to the power supply MOS transistor Q2
Even if it is connected to the floating gate 2A of
It can be easily understood that the same effect can be obtained.

(Embodiment 2) FIG. 4 is a schematic sectional view schematically showing an example of the structure of a semiconductor device according to another embodiment of the present invention. In the case of the second embodiment, for example, an n-type well 13 is formed in a part of the substrate 12 made of a p-type semiconductor, and the first insulating film 15 is formed on the well 13.
a, the floating gate 15A, the second insulating film 15b,
A power supply MOS transistor Q3 having a structure in which control gates 15B are sequentially stacked is provided.

A part of the well 13 is provided with a power supply region 13a which is further doped with n-type at a higher concentration, and an electrode 14 is provided in the power supply region 13a. Further, an electrode 15 is also connected to the control gate 15B, and these electrodes 14 and 15 are connected to a lead-out pad (not shown) in the chip and an external connection terminal after the sealing of the chip is completed. At the time of completion, or even in the actual use state after the chip sealing is completed,
It is possible to apply a voltage from the outside.

The floating gate 15A of the power supply MOS transistor Q3 has an element isolation target, for example, MO.
Field plate 16 surrounding the S transistor Q1
Are connected. Field plate 16 and substrate 12
The insulating film 16a is formed between the same as in the first embodiment. The material of the field plate 16 is
For example, a ferroelectric material, a multilayer film of polysilicon and a ferroelectric material, or polysilicon can be used.

Then, in the case of the present embodiment, a voltage is applied to the electrode 14 of the power supply MOS transistor Q3 and the electrode 15 of the control gate 15B to cause a tunnel current to flow from the substrate 12 (well 13) through the floating gate 15A. Thus, charges are injected into the field plate 16 to set the field plate 16 to a desired potential, and the MOS transistor Q1 surrounded by the field plate 16 can be reliably separated from the surrounding circuit structure. That is, the power supply MOS transistor Q3
The structure of is the same as that of EEPROM, and the charge injection method is also
It can be realized by the same method as in the case of EEPROM.

In the case of the second embodiment, the same effect as in the case of the first embodiment can be obtained, and since the power supply MOS transistor Q3 requires only two electrodes, the circuit structure is further simplified. be able to.

(Embodiment 3) FIG. 5 is a schematic sectional view schematically showing an example of the structure of a semiconductor device according to still another embodiment of the present invention.

The source 1 is provided on the substrate 17 made of semiconductor.
A MOS transistor Q4 including the gate 9, the gate 20, the gate insulating film 20a, and the drain 21 is formed, and the MO transistor Q4 is formed at a position surrounding the MOS transistor Q4.
A field plate 18 for separating the S transistor Q4 from other circuit structures is arranged on the substrate 17 via an insulating film 18a.

In this case, the field plate 18 is made of a material having a work function difference from that of the substrate 17. That is, for example, when the substrate 17 is a p-type Si semiconductor (work function ≈4.6 to 5.0 ev), platinum Pt (work function = 6.0 ev) or the like is used as the material of the field plate 18 Since the surface of 17 is in an accumulation state, element isolation is possible. When the substrate 17 is n-type, the same effect can be obtained by using cesium Cs (work function = 1.8 ev) or the like. Further, in this case, since it is not necessary to inject charges into the plate electrode, there is no need for a power feeding circuit.

In the case of the third embodiment, by using a material having a work function difference from that of the substrate 17 for the field plate 18, a power feeding circuit and the like are completely unnecessary, and the circuit structure can be simplified. There is an advantage.

(Embodiment 4) FIG. 6 is a schematic sectional view schematically showing an example of the structure of a semiconductor device according to another embodiment of the present invention. In this embodiment, a case where the present invention is applied to a DRAM memory cell will be described.

On the substrate 30, a capacitance storage electrode 31 and a cell plate 32, and a thin insulating film 3 separating them from each other.
The capacitor C is formed by 3. As the material of the cell plate 32, a ferroelectric substance, a multilayer film of polysilicon and a ferroelectric substance, or polysilicon can be used. The capacitance storage electrode 31 of the capacitor C is connected via the MOS transistor Q5 formed on the substrate 30,
It is connected to the bit line 34. That is, the MOS transistor Q5 has a source 35 to which the bit line 34 is connected.
And a drain 37 to which the capacitance storage electrode 31 is connected, and a gate 37 which is stacked on the channel region 30a on the surface of the substrate 30 via a gate insulating film 37a and connected to a word line 38. By the operation of the MOS transistor Q5, a 1-bit write operation for charging the capacitance storage electrode 31 from the bit line 34 and a 1-bit read operation for discharging the charge stored in the capacitance storage electrode 31 to the bit line 34 for reading The action is taken.

In this case, the substrate 30 is partially attached to the substrate 30.
Is formed on the channel region 30b on the surface of the first gate insulating film 40.
A floating gate 40A and a control gate 40B are sequentially stacked via a and a second gate insulating film 40b, and a source 42 and a drain 43 are arranged at positions sandwiching the channel region 30b for power feeding. A MOS transistor Q6 is formed.
In the case of this embodiment, a part of the cell plate 32 is connected to the floating gate 40A of the power supply MOS transistor Q6. The structure of the power supply MOS transistor Q6 is the same as that of the EEPROM, and the method of injecting charges into the floating gate 40A is EEPR.
It can be realized by the same method as in the case of OM.

Source 4 of power supply MOS transistor Q6
2, control gate 40B, drain 43 electrode 3
The electrode 9, electrode 40, and electrode 41 are connected to a lead-out pad in a chip to which a voltage can be applied by a probe needle or the like in a wafer state or an external terminal after completion of sealing. That is, the structure is such that the voltage can be applied to the power supply MOS transistor Q6 even after the chip is completed or after the sealing.

In the semiconductor device of this embodiment, for example, due to variations in the dimensions and characteristics of the insulating film 33 that constitutes the capacitor C, the capacitance storage electrode 31, the cell plate 32, etc. during manufacturing, When the characteristics or the like change, or when the characteristics change due to a temporal factor during actual use, the amount of charge injected into the cell plate 32 via the floating gate 40A of the power feeding MOS transistor Q2 is changed as needed. By controlling to an arbitrary value, the characteristics of the memory cell after the chip is completed are externally adjusted.

Therefore, as compared with the conventional memory cell configuration, defective memory cells can be remedied, failure countermeasures can be taken during use, and the yield of memory elements and the extension of life can be realized.

In the above example, for simplicity, the cell plate 32 of one capacitor C is connected to one power supply MOS.
Although the configuration connected to the transistor Q6 is illustrated, it is also included in the present embodiment that the capacitors C are divided into predetermined groups and the electric charges are collectively injected by one power supply MOS transistor Q6 in each group. Needless to say. Further, as the power supply MOS transistor, a configuration such as the power supply MOS transistor Q3 illustrated in FIG. 4 may be used.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the element to be isolated is M
Not limited to the OS transistor, it can be widely applied to general semiconductor elements.

[0047]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the semiconductor device of the present invention, it is possible to achieve the effect that the circuit structure required for element isolation can be simplified and that the power consumption and the required circuit area can be reduced.

Further, according to the semiconductor device control method of the present invention, it is possible to obtain the effect that variations in characteristics in the manufacturing process can be corrected at any time to improve the characteristics and improve the yield.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view schematically showing an example of the configuration of a semiconductor device that is an embodiment of the present invention.

FIG. 2 is a schematic plan view thereof.

FIG. 3 is a plan view showing a modification thereof.

FIG. 4 is a schematic cross-sectional view schematically showing an example of the configuration of a semiconductor device that is another embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view schematically showing an example of the configuration of a semiconductor device that is still another embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view schematically showing an example of the configuration of a semiconductor device that is still another embodiment of the present invention.

FIG. 7 is a flowchart showing an example of the operation of the semiconductor device and the control method thereof according to the embodiment of the present invention.

[Explanation of symbols]

 1 field plate (electrode for element isolation) 1a insulating film 2 to 4 electrode 2A floating gate 2B control gate 2a first gate insulating film 2b second gate insulating film 5 source 6 drain 7 electrode 7A source 8 electrode 8A gate 8a gate insulating film 9 electrode 9A drain 10 field plate (element isolation electrode) 11 active region 12 substrate 12a channel region 12b channel region 13 well 13a power feeding region 14 electrode 15 electrode 15A floating gate 15B control gate 15a first insulating film 15b second insulating film 16 Field plate (element isolation electrode) 16a Insulation film 17 Substrate 18 Field plate (element isolation electrode) 18a Insulation film 19 Source 20 Gate 21 Drain 30 Substrate 30a Channel region 30b Channel region 31 Capacitive storage electrode 32 Cell plate 33 Insulating film 34 Bit line 35 Source 36 Drain 37 Gate 37a Gate insulating film 38 Word line 39 Electrode 40 Electrode 40A Floating gate 40B Control gate 40a First gate insulating film 40b Second gate insulating Membrane 41 Electrode 42 Source 43 Drain C Capacitor Q1 MOS transistor Q2 Power supply MOS transistor (MOS structure) Q3 Power supply MOS transistor (MOS structure) Q4 MOS transistor Q5 MOS transistor Q6 Power supply MOS transistor (MOS structure)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/788 29/792 H01L 29/78 371

Claims (9)

[Claims] 1. A semiconductor device comprising an element isolation electrode in an electrically floating state, wherein the element isolation electrode comprises:
A semiconductor device comprising a floating gate and a control gate for controlling charge injection to the floating gate, the semiconductor device being connected to the floating gate of a MOS structure. 2. A semiconductor device having a cell plate which is in an electrically floating state and constitutes a part of a capacitor, wherein the cell plate controls a floating gate and charge injection to the floating gate. A semiconductor device connected to the floating gate having a MOS structure including a gate. 3. The MOS structure comprises a source and a drain which are arranged so as to sandwich a stacked region of the floating gate and the control gate, and a state in which a potential difference to the extent that hot carriers are generated is applied between the source and the drain. 2. The amount of charge injected into the element isolation electrode or the cell plate via the floating gate is controlled by controlling the voltage applied to the control gate with.
Alternatively, the semiconductor device according to item 2. 4. The MOS structure has a structure in which the floating gate and the control gate are stacked on a well formed on a substrate via a gate insulating film, and a desired structure is provided between the well and the control gate. 3. The semiconductor device according to claim 1, wherein the amount of charges injected into the element isolation electrode or the cell plate through the floating gate is controlled by applying the voltage of 3. 5. A ferroelectric, polysilicon, or a multilayer film of ferroelectric and ferroelectric is used as a material of the element isolation electrode or the cell plate. Semiconductor device. 6. A semiconductor device comprising an element isolation electrode in an electrically floating state, wherein the element isolation electrode is made of an electrode material having a work function difference with respect to a substrate. Semiconductor device. 7. The electrode material is platinum (Pt) when the substrate is a p-type semiconductor and cesium (Cs) when the substrate is an n-type semiconductor. The semiconductor device according to claim 6. 8. A method of controlling a semiconductor device including an element isolation electrode in an electrically floating state, wherein the element isolation electrode is a floating gate and a control gate for controlling charge injection into the floating gate. Of a semiconductor device, wherein the semiconductor device is connected to the floating gate of a MOS structure having a transistor, and the voltage applied from the outside to the control gate is controlled to control the amount of charge to the element isolation electrode at any time. Method. 9. A method of controlling a semiconductor device which is electrically floating and includes a cell plate which forms a part of a capacitor, wherein the cell plate is a floating gate and a charge is injected into the floating gate. By connecting to the floating gate of the MOS structure having a control gate for controlling and controlling the voltage applied to the control gate from the outside,
A method for controlling a semiconductor device, comprising controlling the amount of electric charge to the cell plate at any time.