JP2017228616A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory device in which current leakage of a memory cell due to crystal defect can be prevented.SOLUTION: The ferroelectric memory device includes: a plurality of memory cells, each of which includes ferroelectric capacitor (4g to 4i) and transistor (4c, WL1 to WL6); and a separation gate (4b) which is formed in a semiconductor region among the plurality of memory cells via an insulating film. A fixed potential for electrically separating the plurality of memory cells is applied to the separation gate.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a ferroelectric memory device.

  There is known a semiconductor device having a semiconductor substrate having a main surface, an element formation region formed on the main surface of the semiconductor substrate, and a plurality of predetermined elements formed in the element formation region (see Patent Document 1). . The plurality of isolation regions are formed on the main surface of the semiconductor substrate and electrically isolate a predetermined plurality of elements. Each of the plurality of isolation regions is arranged in an island shape in the element formation region.

  Also known is a semiconductor memory device having a plurality of semiconductor memory cells arranged in an array and a memory cell region having element isolation shield electrodes extending in the column direction by isolating semiconductor memory cells adjacent in the row direction. (See Patent Document 2). In the peripheral circuit region, a peripheral circuit having an element isolation insulating film for transferring data to and from the semiconductor memory cell is provided. An element isolation shield electrode extends over the element isolation insulating film at the boundary between the memory cell region and the peripheral circuit region.

  A semiconductor device having a first element isolation structure and a second element isolation structure formed on a semiconductor substrate is known (see Patent Document 3). The semiconductor substrate has a first element active region defined by the first element isolation structure and a second element active region defined by the second element isolation structure. The first element isolation structure includes a first groove formed in the semiconductor substrate, and includes a first cavity region formed in the first groove. The second element isolation structure is composed of any one of an element isolation structure made of an insulating film and a field shield element isolation structure having electrodes.

JP 2006-294919 A JP 2001-210729 A Japanese Patent Laid-Open No. 11-126819

  A ferroelectric memory device has a plurality of memory cells each including a ferroelectric capacitor and a transistor. A plurality of memory cells can be electrically isolated by digging a trench in a semiconductor substrate between the plurality of memory cells and filling a silicon oxide film. However, if the ferroelectric memory device is miniaturized and the design rule is reduced, crystal defects are generated due to the difference in thermal expansion coefficient between the semiconductor substrate and the silicon oxide film, and current leakage of the memory cell occurs.

  In one aspect, an object of the present invention is to provide a ferroelectric memory device capable of preventing current leakage of a memory cell due to crystal defects.

  A ferroelectric memory device includes a plurality of memory cells each including a ferroelectric capacitor and a transistor, and an isolation gate formed on a semiconductor region between the plurality of memory cells via an insulating film. And a fixed potential for electrically isolating the plurality of memory cells is applied to the isolation gate.

  In one aspect, memory cell current leakage due to crystal defects can be prevented.

1A to 1C are layout diagrams illustrating a configuration example of the ferroelectric memory device according to the first embodiment. 2A to 2C are layout diagrams showing pattern examples of word lines, bit lines, and ferroelectric capacitors. 3A and 3B are cross-sectional views showing a configuration example of the ferroelectric memory device. FIG. 4 is a circuit diagram showing a configuration example of the memory cell. FIG. 5 is a diagram showing hysteresis characteristics of the ferroelectric capacitor. FIGS. 6A and 6B are layout diagrams showing a configuration example of a ferroelectric memory device that separates memory cells by the STI technique. 7A and 7B are cross-sectional views showing a configuration example of the ferroelectric memory device. 8A to 8C are layout diagrams illustrating a configuration example of the ferroelectric memory device according to the second embodiment. 9A and 9B are cross-sectional views showing a configuration example of the ferroelectric memory device. 10A to 10C are layout diagrams illustrating a configuration example of the ferroelectric memory device according to the third embodiment. FIGS. 11A and 11B are layout diagrams showing pattern examples of ferroelectric capacitors. 12A and 12B are cross-sectional views showing a configuration example of a ferroelectric memory device. FIG. 13 is a layout diagram showing a configuration example of the ferroelectric memory device according to the fourth embodiment. 14A and 14B are cross-sectional views showing a configuration example of a ferroelectric memory device.

(First embodiment)
FIG. 1A is a layout diagram illustrating a configuration example of the ferroelectric memory device according to the first embodiment. FIG. 1B is a layout diagram showing a diffusion region FL of a semiconductor substrate (silicon substrate) and a silicon oxide film 4a for element isolation. FIG. 1C is a layout diagram showing a polysilicon layer isolation gate 4b for isolating memory cells. FIG. 2A is a layout diagram showing word lines WL1 to WL6 of the polysilicon layer. FIG. 2B is a layout diagram showing the bit lines BL1 to BL4. FIG. 2C is a layout diagram showing the lower electrode 4g, the ferroelectric film 4h and the upper electrode 4i of the ferroelectric capacitor. FIG. 3A is a cross-sectional view taken along the line AA in FIG. FIG. 3B is a cross-sectional view taken along the line BB in FIG. FIG. 4 is a circuit diagram showing a configuration example of the memory cell.

  A ferroelectric memory device is a non-volatile memory that can retain information even when the power is turned off, and has 100,000 times more writable times than flash memory or EEPROM (Electrically Erasable Programmable Read-Only Memory). In addition, it has high speed and low power consumption during writing. As shown in FIGS. 3A and 3B, the bit lines BL1 to BL4, the ferroelectric capacitor lower electrode 4g, the ferroelectric film 4h and the upper electrode 4i are three-dimensionally formed on the word lines WL1 to WL6. By providing this, a large-capacity ferroelectric memory device can be realized. A ferroelectric memory device has a stack type memory cell called COB (Cell Over Bit line).

  The storage contact SC is indicated by a double circle. The bit line contact BLC is indicated by a single circle. A ferroelectric memory device has a plurality of two-dimensional memory cells. As shown in FIG. 4, for example, one memory cell includes a ferroelectric capacitor C1 and a field effect transistor Tr1. The word line WL1 constitutes the gate of the field effect transistor Tr1. The bit line BL1 is connected to the drain 4c of the field effect transistor Tr1 via the bit line contact BLC. The ferroelectric capacitor C1 includes the lower electrode 4g, the ferroelectric film 4h, and the upper electrode 4i shown in FIGS. 3A and 3B, and is connected between the source 4c of the field effect transistor Tr1 and the plate line CP1. . Similarly, the plurality of memory cells are provided at intersections of the word lines WL1 to WL6 and the bit lines BL1 to BL4. Each of the plurality of memory cells includes a ferroelectric capacitor C1 and the like, a field effect transistor Tr1 and the like.

  FIG. 5 is a diagram showing hysteresis characteristics of the ferroelectric capacitor C1. The horizontal axis indicates the potential difference V obtained by subtracting the potential of the bit line BL1 from the potential of the plate line CP1. The vertical axis represents the amount of polarization Q emitted from the ferroelectric capacitor C1.

  A state in which the word line WL1 is 0V, the bit line BL1 is 0V, and the plate line CP1 is 0V is a standby state. At this time, the ferroelectric capacitor C1 is in the state 501 or 505. The state 501 is a storage state of data “1” having remanent polarization −Pr. The state 505 is a storage state of data “0” having remanent polarization + Pr. States 502 and 506 are states in which the polarization quantity Q is effectively zero. The potential difference V between both ends of the ferroelectric capacitor C1 in the state 502 is the coercive voltage + Vc. The potential difference V between both ends of the ferroelectric capacitor C1 in the state 506 is the coercive voltage −Vc. States 503 and 507 are states when a voltage sufficient to reverse the polarization of the ferroelectric capacitor C1 is applied. The change in the state 501 → 502 → 503 and the change in the state 505 → 506 → 507 are called switching regions because the polarization state is reversed. Further, the change between the states 503 and 505 and the change between the states 507 and 501 are called linear regions because only the amount of polarization increases and decreases without changing the polarization direction.

  Next, a read operation of the ferroelectric memory device will be described. In the read operation, the ferroelectric memory device selects a word line and a plate line according to an address signal input from the outside. Here, an example in which the word line WL1 and the plate line CP1 are selected will be described. When the word line WL1 becomes high potential by selection and the field effect transistor Tr1 becomes conductive, the ferroelectric capacitor C1 is connected to the bit line BL1. In this state, when the plate line CP1 becomes a high potential, the ferroelectric capacitor C1 reaches the state 503 from the state 501 through the state 502 in the case of the storage state 501 of “1”. At this time, the ferroelectric capacitor C1 discharges a large amount of read charge 511 of “1” to the bit line BL1 by reversing the polarization. On the other hand, the ferroelectric capacitor C1 reaches the state 503 from the state 505 when the storage state 505 is “0”. At this time, since the polarization inversion does not occur in the ferroelectric capacitor C1, a small amount of read charge 512 of “0” is released to the bit line BL1. Even if a voltage equal to or higher than the polarization inversion is applied to the plate line CP1, only the state 503 moves to the state 504 in the linear region, and the difference between the charges 511 and 512 read from the memory cell does not change. The ferroelectric memory device amplifies a difference voltage between a charge 511 of “1” and a charge 512 of “0” by a sense amplifier, and outputs data stored in the memory cell to the outside.

  Next, the rewrite operation of the ferroelectric memory device will be described. The above read operation is destructive read, and the storage state of the memory cell is erased. Therefore, a rewrite operation is necessary. The difference voltage amplified by the sense amplifier is rewritten to the ferroelectric capacitor C1 through the bit line BL1. When the data “1” is read, the bit line BL1 becomes a high voltage, and when the data “0” is read, the bit line BL1 becomes a low voltage. For example, the high voltage corresponding to the data “1” is a step-down potential obtained by stepping down the power supply potential from the outside or the potential of the external power supply to a desired potential by the step-down circuit. The low voltage corresponding to the data “0” is the reference potential VSS. In a memory cell, in order to obtain a sufficient differential voltage at the time of reading, a certain level of potential is required for rewriting to the ferroelectric capacitor C1. For example, in the case of a memory cell designed with a design rule of 180 nm, a write voltage of about 1.8 V is required, and a bit line BL1 and a plate line CP1 are connected using a 1.8 V field effect transistor Tr1. Driving at 1.8V. Further, for example, a voltage of about 3 V is applied to the word line WL1 as a boosted potential that can overdrive the threshold voltage Vth of the field effect transistor Tr1 in order to give a sufficient voltage across the ferroelectric capacitor C1. .

  Next, the description returns to the hysteresis characteristics of FIG. The ferroelectric capacitor C1 is in a state 503 when data “1” is read. When the bit line BL1 is amplified to a high potential, the ferroelectric capacitor C1 moves from the state 503 to the state 505 because the bit line BL1 has the same potential as the plate line CP1. Thereafter, when the plate line CP1 is lowered from the high potential to the low potential, the ferroelectric capacitor C1 moves from the state 505 to the state 507 via the state 506. When the rewrite operation is completed and the standby state is restored, the bit line BL1 falls from the high potential to the low potential, and the ferroelectric capacitor C1 returns to the data storage state 501 of “1”. After that, the word line WL1 becomes low potential and shifts to a standby state.

  The ferroelectric capacitor C1 is in the state 503 when data “0” is read. The ferroelectric capacitor C1 remains in the state 503 because the potential difference between the bit line BL1 and the plate line CP1 hardly changes even when the bit line BL1 is amplified to a low potential. Thereafter, when the plate line CP1 is lowered from the high potential to the low potential, the ferroelectric capacitor C1 moves from the state 503 to the data recording state 505 of “0”. Even when the rewrite operation ends and returns to the standby state, the bit line BL1 remains at a low potential, so the ferroelectric capacitor C1 remains in the state 505. After that, the word line WL1 becomes low potential and shifts to a standby state.

  In the case of writing in which the data stored in the memory cell is changed from “1” to “0”, the write amplifier changes the bit line BL1 from a high potential to a low potential. In the case of writing in which the data stored in the memory cell is changed from “0” to “1”, the write amplifier changes the bit line BL1 from a low potential to a high potential. As a result, the “0” and “1” data write states described above are entered, and the word line WL 1 becomes low potential in the state where the “0” data storage state 505 and the “1” data state 501 are written. Transition to the standby state. In this manner, the ferroelectric memory device reads and writes “0” and “1” data.

  As shown in FIG. 1A, when the design rule is f [μm], the size of the memory cell is 4f in the direction of the bit lines BL1 to BL4 and 2f in the direction of the word lines WL1 to WL6. Next, a method for manufacturing a ferroelectric memory device having a COB stack type memory cell will be described.

  First, as shown in FIG. 1B, a silicon oxide film 4a and an impurity diffusion region FL are formed on a silicon substrate. The diffusion region FL is an activation region. The silicon oxide film 4a is an isolation region formed by STI (Shallow Trench Isolation) technology. First, a trench is dug on a silicon substrate, and a silicon oxide film is grown thereon. By polishing this silicon oxide film by CMP (Chemical Mechanical Polishing), the silicon oxide film 4a is embedded in the groove. As a result, bird's beaks generated during the growth of the silicon oxide film can be prevented, and a finer layout can be realized.

  Next, in order to adjust the characteristics of the field effect transistor of the isolation gate 4b, a p-type impurity is implanted only into the memory cell array portion. Thereby, the threshold voltage and current drive capability of the field effect transistor can be adjusted. Next, a silicon oxide film (gate oxide film) is formed on the diffusion region FL, and a polysilicon isolation gate 4b shown in FIG. 1C is formed thereon. The isolation gate 4b is a gate for isolating the memory cells, and is a single pattern provided in the same layer.

  Next, in order to adjust the characteristics of the field effect transistor Tr1 and the like in the memory cell, when the field effect transistor Tr1 and the like are n-channel field effect transistors, a p-type impurity is implanted into the silicon substrate. When p. Is a p-channel field effect transistor, an n-type impurity is implanted. Thereby, the threshold voltage and current driving capability of the field effect transistor Tr1 and the like can be adjusted.

  Next, a silicon oxide film (gate oxide film) is formed on the silicon substrate, and polysilicon word lines WL1 to WL6 shown in FIG. 2A are formed thereon. Next, in the memory cell array portion, the diffusion region 4c is formed by implanting n-type impurities into the portions masked by the isolation gate 4b and the word lines WL1 to WL6. The diffusion region 4c is a source and drain of the field effect transistor Tr1 and the like. At this time, the diffusion region of the transistor in the peripheral circuit outside the silicon oxide film 4a is also formed.

  The isolation gate 4b and the word lines WL1 to WL6 are insulated by a silicon oxide film. Further, between the isolation gate 4b and the diffusion region FL, a silicon oxide film of a type and thickness close to that of the gate oxide film such as the field effect transistor Tr1 is formed. Thereby, the isolation gate 4b functions as a gate of a transistor for isolating the memory cell.

  In addition, after forming the isolation gate 4b, by providing sidewalls made of silicon oxide films on both sides of the isolation gate 4b, the steps become gentle when the word lines WL1 to WL6 are formed, and the word lines WL1 to WL6 are formed. Becomes easier.

  Next, a silicon oxide film is formed, a contact hole for the bit line contact BLC is formed on the diffusion region (drain) 4c, and a contact hole for the storage contact SC1 is formed on the diffusion region (source) 4c. Form. The storage contact SC1 is a part of the storage contact SC. By forming the contact hole of the storage contact SC1 at the same time as the contact hole of the bit line contact BLC, the aspect ratio of the contact hole of the storage contact SC1 becomes small, and the storage contact SC1. It becomes easy to form an SC contact hole. Next, a plug layer of a metal material such as tungsten is embedded in the contact hole as the bit line contact BLC and the storage contact SC1 in order to improve the coverage.

  Next, the bit lines BL1 to BL4 in FIG. 2B are formed by low resistance wiring, and the bit lines BL1 to BL4 are connected to the diffusion region (drain) 4c through the bit line contact BLC. Next, a silicon oxide film is formed, and a contact hole for the storage contact SC2 is formed on the storage contact SC1. Next, a plug layer made of a metal material such as tungsten is buried in the contact hole as the storage contact SC2. The storage contact SC2 is a part of the storage contact SC. The storage contacts SC1 and SC2 correspond to the storage contact SC.

  Next, the lower electrode 4g connected to the storage contact SC is formed. Next, a ferroelectric film 4h is formed on the lower electrode 4g. Next, the upper electrode 4i is formed on the ferroelectric film 4h. The lower electrode 4g, the ferroelectric film 4h, and the upper electrode 4i correspond to the ferroelectric capacitor C1 and the like of each memory cell.

  In this embodiment, the isolation gate 4b is formed on the semiconductor region between the plurality of memory cells via a silicon oxide film (insulating film). The isolation gate 4b and the diffusion region (drain and source) constitute an isolation transistor. A fixed potential 0V for electrically separating a plurality of memory cells is applied to the isolation gate 4b. As a result, the isolation transistor is always turned off, and the plurality of memory cells are electrically isolated from each other. For example, the isolation gate 4b electrically connects the memory cell including the field effect transistor of the word line WL1 and the field effect transistor of the word line WL3 adjacent to each other in the horizontal direction (first direction) in FIG. Separate. In addition, the isolation gate 4b includes a field effect transistor of the bit line BL1 adjacent in the vertical direction (second direction) in FIG. 1A orthogonal to the horizontal direction (first direction) in FIG. The memory cell including the memory cell including the field effect transistor of the bit line BL2 is electrically isolated. As shown in FIG. 1C, the isolation gate 4b is a single pattern provided in the same layer, and is formed so as to cover a silicon substrate region other than the field effect transistor region of a plurality of memory cells. .

  Next, in order to explain the effect of providing the isolation gate 4b according to the present embodiment, the isolation gate 4b is provided with reference to FIGS. 6 (A) and 6 (B) and FIGS. 7 (A) and 7 (B). First, the problem of the ferroelectric memory device that separates the memory cells by the STI technique will be described.

  FIG. 6A is a layout diagram illustrating a configuration example of a ferroelectric memory device that separates memory cells using the STI technique. FIG. 6B is a layout diagram showing the diffusion region FL of the semiconductor substrate (silicon substrate) and the silicon oxide film 4a for element isolation. FIG. 7A is a cross-sectional view taken along line AA in FIG. FIG. 7B is a cross-sectional view taken along line BB in FIG. The pattern of the word lines WL1 to WL6 is the same as that of FIG. The pattern of the bit lines BL1 to BL4 is the same as that of FIG. The patterns of the ferroelectric capacitor lower electrode 4g, ferroelectric film 4h, and upper electrode 4i are the same as those in FIG. The ferroelectric memory devices shown in FIGS. 6A, 6B, 7A, and 7B are shown in FIGS. 1A to 1C, 2A to 2C, and FIG. Differences from the ferroelectric memory device of (A) and (B) will be described.

  First, as shown in FIG. 6B, a diffusion region FL and a silicon oxide film 4a are formed. The diffusion region FL is a field effect transistor region of the memory cell. The silicon oxide film 4a is provided in a region other than the diffusion region FL by the STI technique. That is, a trench is dug on the silicon substrate, a silicon oxide film is grown thereon, and a silicon oxide film 4a is formed by CMP. As a result, bird's beaks that occur during the growth of the silicon oxide film can be prevented, and a finer layout can be realized. Thereafter, the same process as that of the ferroelectric memory device of FIG. The silicon oxide film 4a is an insulating film and electrically isolates a plurality of memory cells.

  When heat treatment is performed in the above memory cell formation step, stress is generated between the silicon oxide film 4a by the STI technique and the silicon substrate because the thermal expansion coefficient is different. Specifically, the portion of the silicon substrate having a higher impurity concentration than the silicon oxide film 4a swells, and stress is applied to the silicon substrate. For example, as the impurity concentration in the silicon substrate is increased in order to control characteristics such as threshold voltage and breakdown voltage of the field effect transistor Tr1, etc., the number of atoms in the silicon substrate increases and thermal expansion easily occurs. In particular, as shown in FIGS. 6A and 7A, in a region 601 in which three directions of the diffusion region FL are surrounded by the silicon oxide film 4a, stress is transmitted in the three directions, and the silicon substrate is defective. The risk of giving is increased. When the defect in the silicon substrate reaches the diffusion region 4c of the memory cell, current leakage from the crystal defect portion to the silicon substrate occurs, or the diffusion region of another node such as the bit line contact BLC via the crystal defect Current leakage to 4c occurs. The presence of these leakage currents reduces the above differential voltage obtained from the memory cell. In particular, when the current in the diffusion region 4c of the storage contact SC and the diffusion region 4c of the bit line contact BLC leaks, the risk of data destruction of the memory cell increases due to the amplitude to the power supply potential of the bit lines BL1 to BL4. . Thereby, miniaturization of the ferroelectric memory device is hindered. Particularly, as the miniaturization of the ferroelectric memory device progresses in recent years, and the design rule of the diffusion region 4c of the memory cell and the silicon oxide film 4a becomes smaller, the above problem becomes remarkable.

  In the present embodiment, in order to solve the above-described problem, as shown in FIGS. 3A and 3B, the isolation gate 4b electrically isolates a plurality of memory cells. The stress acting on the region 601 in FIG. 7A can be prevented, current leakage due to crystal defects can be prevented, and the manufacturing yield of the ferroelectric memory device can be improved.

  The potential of the memory cell is a non-boosted voltage and is lower than that of the peripheral circuit. In addition, the isolation transistor of the isolation gate 4b only needs to be kept off regardless of the activation / deactivation state of the ferroelectric memory device. It may be lower than a transistor used in a peripheral circuit outside the oxide film 4a. For this reason, the isolation transistor does not require high-speed switching and high breakdown voltage unlike the transistors used in memory cells and peripheral circuits, and has a simple polysilicon transistor structure that is always off and is free to use. Formation with a gate oxide film thickness is possible.

  The isolation gate 4b is controlled by a gate layer different from the word lines WL1 to WL6. Since the isolation transistor of the isolation gate 4b is independent of the transistor Tr1 and the like of the memory cell, the characteristics of the transistor can be freely set. The isolation gate 4b can be formed in the same process as the gate of a transistor used in a peripheral circuit or an output circuit portion.

  Each memory cell is separated by the separation gate 4b and not separated by the silicon oxide film of the STI technique, so that the probability of occurrence of crystal defects is drastically reduced. Note that the diffusion region FL in the outer peripheral portion of the memory cell array portion is a dummy pattern for maintaining the continuity of the memory cell pattern. Therefore, even if surrounded by the silicon oxide film 4a, There is little risk of influence.

(Second Embodiment)
FIG. 8A is a layout diagram illustrating a configuration example of the ferroelectric memory device according to the second embodiment. FIG. 8B is a layout diagram showing a diffusion region FL of a semiconductor substrate (silicon substrate) and a silicon oxide film 4a for element isolation. FIG. 8C is a layout diagram showing a polysilicon layer isolation gate 5b for isolating memory cells. FIG. 9A is a cross-sectional view taken along the line AA in FIG. FIG. 9B is a cross-sectional view taken along the line BB in FIG. The pattern of the word lines WL1 to WL6 is the same as that of FIG. The pattern of the bit lines BL1 to BL4 is the same as that of FIG. The patterns of the ferroelectric capacitor lower electrode 4g, ferroelectric film 4h, and upper electrode 4i are the same as those in FIG. Hereinafter, the points of the second embodiment different from the first embodiment will be described.

  The method for manufacturing the ferroelectric memory device according to the present embodiment will be explained. First, as shown in FIG. 8B, a diffusion region FL and a silicon oxide film 4a are formed. The diffusion region FL is a field effect transistor region of the memory cell. The silicon oxide film 4a is provided in a region other than the diffusion region FL by the STI technique.

  Next, in order to adjust the characteristics of the isolation transistor of the isolation gate 5b, a p-type impurity is implanted only into the memory cell array portion. Next, a silicon oxide film (gate oxide film) is formed on the diffusion region FL, and a polysilicon isolation gate 5b shown in FIG. 8C is formed thereon. The isolation gate 5b is a gate for isolating a plurality of memory cells in the vertical direction of FIG.

  Next, in order to adjust the characteristics of the field effect transistor Tr1 and the like in the memory cell, when the field effect transistor Tr1 and the like are n-channel field effect transistors, a p-type impurity is implanted into the silicon substrate. When p. Is a p-channel field effect transistor, an n-type impurity is implanted.

  Next, a silicon oxide film (gate oxide film) is formed on the silicon substrate, and polysilicon word lines WL1 to WL6 shown in FIG. 2A are formed thereon. Next, in the memory cell array portion, a diffusion region 4c is formed by implanting an n-type impurity into a portion masked by the isolation gate 5b and the word lines WL1 to WL6. The diffusion region 4c is a source and drain of the field effect transistor Tr1 and the like. At this time, the diffusion region of the transistor in the peripheral circuit outside the silicon oxide film 4a is also formed.

  The isolation gate 5b and the word lines WL1 to WL6 are insulated by a silicon oxide film. Further, between the isolation gate 5b and the diffusion region FL, a silicon oxide film of a kind and thickness close to that of the gate oxide film such as the field effect transistor Tr1 is formed. Thereby, the isolation gate 5b functions as a gate of a transistor for isolating the memory cell.

  Also, after forming the isolation gate 5b, by providing sidewalls made of silicon oxide films on both sides of the isolation gate 5b, the steps become gentle when the word lines WL1 to WL6 are formed, and the word lines WL1 to WL6 are formed. Becomes easier.

  Next, a silicon oxide film is formed, a contact hole for the bit line contact BLC is formed on the diffusion region (drain) 4c, and a contact hole for the storage contact SC1 is formed on the diffusion region (source) 4c. Form. Next, a plug layer of a metal material such as tungsten is embedded in the contact hole as the bit line contact BLC and the storage contact SC1 in order to improve the coverage. Next, the bit lines BL1 to BL4 in FIG. 2B are formed by low resistance wiring, and the bit lines BL1 to BL4 are connected to the diffusion region (drain) 4c through the bit line contact BLC. The subsequent steps are the same as those in the first embodiment.

  As shown in FIG. 9A, the silicon oxide film 4a is an insulating film, and electrically isolates a plurality of memory cells adjacent in the horizontal direction in FIG. Further, as shown in FIG. 9B, the silicon oxide film 4a electrically isolates a plurality of memory cells adjacent in the vertical direction of FIG. The isolation gate 5b electrically isolates a plurality of memory cells adjacent in the vertical direction of FIG. The plurality of separation gates 5b extend in the horizontal direction in FIG. The plurality of word lines WL1 to WL6 extend in the vertical direction of FIG.

  In this embodiment, the memory cells are electrically isolated by the isolation gate 5b and the silicon oxide film 4a. A fixed potential 0V for electrically separating a plurality of memory cells is applied to the isolation gate 5b. The isolation transistor of the isolation gate 5b is always off, and electrically isolates the plurality of memory cells in the vertical direction of FIG. As a result, as shown in FIG. 8B, the diffusion region FL surrounded by the silicon oxide film 4a in three directions is eliminated, so that current leakage due to crystal defects can be prevented. 8B is a dummy pattern for maintaining the continuity of the memory cell pattern, it is actually used even when surrounded by the silicon oxide film 4a. There is little risk of affecting the memory cells.

  In the first embodiment, the large-area diffusion region FL shown in FIG. 1B is formed, and when the silicon oxide film is formed by CMP as described above, the diffusion region FL portion of the memory cell array portion is formed. Excessive polishing can occur. This phenomenon is called Dishing. On the other hand, in this embodiment, since the diffusion region FL shown in FIG. 8B has a small area, the occurrence of this dishing can be prevented. In addition, since there is no diffusion region FL in which the three directions are surrounded by the silicon oxide film 4a in the memory cell use region in the memory cell array, the effect of preventing current leakage due to crystal defects is obtained as in the first embodiment. It is done.

(Third embodiment)
FIG. 10A is a layout diagram illustrating a configuration example of the ferroelectric memory device according to the third embodiment. FIG. 10B is a layout diagram showing a diffusion region FL of a semiconductor substrate (silicon substrate) and a silicon oxide film 4a for element isolation. FIG. 10C is a layout diagram showing a silicon film (Fin film) 6c and a silicon oxide film (insulating film) 6d of the transistor of the memory cell. FIG. 11A is a layout diagram showing a ferroelectric capacitor lower electrode 6g, and FIG. 11B is a layout diagram showing a ferroelectric capacitor ferroelectric film 6h and an upper electrode 6i. FIG. 12A is a cross-sectional view taken along the line AA in FIG. FIG. 12B is a cross-sectional view taken along the line BB in FIG. The pattern of the separation gate 5b is the same as that in FIG. The pattern of the word lines WL1 to WL6 is the same as that of FIG. The pattern of the bit lines BL1 to BL4 is the same as that of FIG. Hereinafter, the points of the third embodiment different from the second embodiment will be described.

  In this embodiment, a ferroelectric memory device using Fin-type transistors will be described. A method for manufacturing a ferroelectric memory device will be described. First, as shown in FIG. 10B, a silicon oxide film 4a and an impurity diffusion region FL are formed on a silicon substrate. The diffusion region FL is an activation region. The silicon oxide film 4a is an isolation region formed by the STI technique. Note that the silicon oxide film 4a may be formed by STI in the entire region 6a (FIGS. 12A and 12B) inside the diffusion region FL. In this case, the memory cell array portion has an SOI (Silicon On Isolation) structure on the silicon oxide film 4a.

  Next, silicon is epitaxially grown and etched to form a silicon film (semiconductor film) 6c shown in FIG. Next, in order to adjust the characteristics of the isolation transistor of the isolation gate 5b, a p-type impurity is implanted into the silicon film 6c. Next, a silicon oxide film (gate oxide film) is formed on the silicon film 6c, and a polysilicon isolation gate 5b shown in FIG. 8C is formed thereon. The isolation gate 5b is a gate for isolating a plurality of memory cells in the vertical direction of FIG.

  Next, in order to adjust the characteristics of the field effect transistor Tr1 and the like in the memory cell, a p-type impurity is implanted into the silicon film 6c when the field effect transistor Tr1 and the like are n-channel field effect transistors. When Tr1 or the like is a p-channel field effect transistor, an n-type impurity is implanted.

  Next, a silicon oxide film (gate oxide film) is formed, and polysilicon word lines WL1 to WL6 shown in FIG. 2A are formed thereon. Next, in the memory cell array portion, a diffusion region is formed by implanting an n-type impurity into the portion of the silicon film 6c masked by the isolation gate 5b and the word lines WL1 to WL6. The diffusion regions of the silicon film 6c are the source and drain of the field effect transistor Tr1 and the like.

  The isolation gate 5b and the word lines WL1 to WL6 are insulated by a silicon oxide film. Also, a silicon oxide film of a type and thickness close to that of the gate oxide film such as the field effect transistor Tr1 is formed between the isolation gate 5b and the silicon film 6c. Thereby, the isolation gate 5b functions as a gate of a transistor for isolating the memory cell.

  Also, after forming the isolation gate 5b, by providing sidewalls made of silicon oxide films on both sides of the isolation gate 5b, the steps become gentle when the word lines WL1 to WL6 are formed, and the word lines WL1 to WL6 are formed. Becomes easier.

  Next, a silicon oxide film is formed, a contact hole for the bit line contact BLC is formed on the diffusion region (drain) of the silicon film 6c, and a contact hole for the storage contact SC is formed in the diffusion region of the silicon film 6c. Form on (source). Next, in order to improve the coverage, a plug layer of a metal material such as tungsten is buried in the contact hole as the bit line contact BLC and the storage contact SC. Next, the bit lines BL1 to BL4 in FIG. 2B are formed with low resistance wiring, and the bit lines BL1 to BL4 are connected to the diffusion region (drain) of the silicon film 6c through the bit line contact BLC.

Next, the lower electrode 6g shown in FIG. 11A connected to the storage contact SC is formed. Next, the ferroelectric film 6h shown in FIG. 11B is formed on the lower electrode 6g. Next, the upper electrode 6i is formed on the ferroelectric film 6h. The lower electrode 6g, the ferroelectric film 6h, and the upper electrode 6i correspond to the ferroelectric capacitor C1 and the like of each memory cell. The lower electrode 6g is connected to the diffusion region (source) of the silicon film 6c via the one-stage storage contact SC without passing through the two-stage storage contacts SC1 and SC2 (FIGS. 3A and 3B). Is done. Compared with the second embodiment, this embodiment can greatly reduce the design rule, for example, 180 nm can be reduced to 90 nm or less. The ferroelectric film 6h can use HfO ₂ or the like that can be thinned, and can form a three-dimensional ferroelectric capacitor C1 or the like.

  In the above description, the pillar type ferroelectric capacitor for growing the ferroelectric film 6h on the outer periphery of the lower electrode 6g is shown. However, the cylinder type in which the lower electrode is also thinned and the ferroelectric film is grown on the inner periphery of the lower electrode. The ferroelectric capacitor may be used. Alternatively, a crown-type ferroelectric capacitor in which a ferroelectric capacitor is grown on the outer periphery and inner periphery of the lower electrode may be used.

  As described above, the source and drain of the memory cell transistor are diffusion regions of the silicon film 6c formed on the semiconductor substrate. The silicon oxide film (insulating film) 6d is provided between the plurality of silicon films 6c, and electrically isolates a plurality of memory cells adjacent in the horizontal direction in FIG. The isolation gate 5b in FIG. 12B electrically isolates a plurality of memory cells adjacent in the vertical direction in FIG. The plurality of separation gates 5b extend in the horizontal direction in FIG. The plurality of word lines WL1 to WL6 extend in the vertical direction of FIG.

  In this embodiment, the memory cells are electrically isolated by the isolation gate 5b and the silicon oxide film 6d. A fixed potential 0V for electrically separating a plurality of memory cells is applied to the isolation gate 5b. The isolation transistor of the isolation gate 5b is always in an off state, and electrically isolates the plurality of memory cells in the vertical direction of FIG. Accordingly, as shown in FIG. 10C, since there is no silicon film 6c surrounded by the silicon oxide film in the three directions, current leakage can be prevented. Note that the silicon film 6c on the outer periphery of the memory cell array portion in FIG. 10C is a dummy pattern for maintaining the continuity of the memory cell pattern. There is little risk of affecting the memory cells.

(Fourth embodiment)
FIG. 13 is a layout diagram showing a configuration example of the ferroelectric memory device according to the fourth embodiment. FIG. 14A is a cross-sectional view taken along the line AA in FIG. FIG. 14B is a cross-sectional view along the line BB in FIG. Hereinafter, differences of the fourth embodiment from the third embodiment will be described.

  The plurality of silicon films 6c extend in the horizontal direction of FIG. 13 and are provided on the silicon oxide film 7a for element isolation. The source and drain of the transistor Tr1 and the like of the memory cell are diffusion regions of the silicon film 6c formed on the semiconductor substrate. The isolation gate 5b in FIG. 14A electrically isolates a plurality of memory cells adjacent in the horizontal direction in FIG. The silicon oxide film 6e in FIG. 14B is provided between the plurality of silicon films 6c, and electrically isolates a plurality of memory cells adjacent in the vertical direction in FIG. The plurality of word lines WL1 to WL4 extend in the vertical direction of FIG. The plurality of separation gates 5b extend in the vertical direction of FIG. Since the isolation gate 5b does not cross the word lines WL1 to WL4, it may be formed in the same process as the word lines WL1 to WL4. The isolation gate 5b may be formed in the same process as the gate of the transistor in the peripheral circuit or the output circuit section.

  The ferroelectric memory device of the present embodiment is a COB (Cell and Transistor Over Bitline) type ferroelectric memory device in order to enable the close-packed arrangement of memory cells. The bit lines BL1 to BL8 are provided under the silicon film 6c and connected to the diffusion region (drain) of the silicon film 6c through the bit line contact BLC.

  According to the first to fourth embodiments, by providing the isolation gates 4b and 5b, it is possible to prevent generation of defective memory cells due to crystal defects. Further, since the characteristics of the isolation transistors of the isolation gates 4b and 5b can be set independently of the characteristics of the memory cell transistors, the miniaturization of the ferroelectric memory device can be improved.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

4a Silicon oxide film 4b Isolation gate 4c Diffusion region 4g Lower electrode 4h Ferroelectric film 4i Upper electrode FL Diffusion regions WL1 to WL6 Word lines BL1 to BL4 Bit lines

Claims (9)

A plurality of memory cells each including a ferroelectric capacitor and a transistor;
An isolation gate formed through an insulating film on a semiconductor region between the plurality of memory cells;
A ferroelectric memory device, wherein a fixed potential for electrically isolating the plurality of memory cells is applied to the isolation gate. The plurality of memory cells are provided two-dimensionally,
The isolation gate electrically isolates a plurality of memory cells adjacent in a first direction, electrically isolates a plurality of memory cells adjacent in a second direction orthogonal to the first direction; 2. The ferroelectric memory device according to claim 1, wherein the pattern is a single pattern provided in the same layer.   3. The ferroelectric memory device according to claim 2, wherein the isolation gate is formed so as to cover a substrate region other than a transistor region of the plurality of memory cells. The plurality of memory cells are provided two-dimensionally,
And an insulating film for electrically isolating a plurality of memory cells adjacent in the first direction,
2. The ferroelectric memory device according to claim 1, wherein the isolation gate electrically isolates a plurality of memory cells adjacent in a second direction orthogonal to the first direction. Each of the plurality of memory cells has a plurality of word lines constituting the gate of the transistor,
The isolation gate has a plurality of isolation gates extending in the first direction;
5. The ferroelectric memory device according to claim 4, wherein the plurality of word lines extend in the second direction. The plurality of memory cells are provided two-dimensionally,
The source and drain of the transistor are diffusion regions of a silicon film formed on a semiconductor substrate,
And an insulating film for electrically isolating a plurality of memory cells adjacent in the first direction,
2. The ferroelectric memory device according to claim 1, wherein the isolation gate electrically isolates a plurality of memory cells adjacent in a second direction orthogonal to the first direction. Each of the plurality of memory cells has a plurality of word lines constituting the gate of the transistor,
The isolation gate has a plurality of isolation gates extending in the first direction;
7. The ferroelectric memory device according to claim 6, wherein the plurality of word lines extend in the second direction. The plurality of memory cells are provided two-dimensionally,
The source and drain of the transistor are diffusion regions of a silicon film formed on a semiconductor substrate,
The isolation gate electrically isolates a plurality of memory cells adjacent in a first direction,
2. The ferroelectric memory device according to claim 1, further comprising an insulating film for electrically isolating a plurality of memory cells adjacent in a second direction orthogonal to the first direction. Each of the plurality of memory cells has a plurality of word lines constituting the gate of the transistor,
The plurality of word lines extend in the second direction,
9. The ferroelectric memory device according to claim 8, wherein the isolation gate has a plurality of isolation gates extending in the second direction.

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