JPH07325667A - Data transfer system and disk control lsi - Google Patents

Abstract

PURPOSE:To make it possible to set the width of a transfer bus performing the data transfer between the disk control LSI and the signal processing LSI of a disk device to an arbitrary optimum bit width according to transfer speed. CONSTITUTION:A disk control LSI 10 and a signal processing LSI 20 are provided with counters 43 and 44, data width conversion circuits 41 and 42 and synchronizing detections 45. The counters 43 and 44 count the numbers of transferred bits, delimit data every time the numbers reach prescribed numbers of bits and impart the numbers of transfer surplus bits to the data width conversion circuits 41 and 42. The data width conversion circuits 41 and 42 convert the transfer widths of the input and output of transfer data by storing transfer data by a storage means storing the data as temporary storage data and selecting data lines by selection circuits having plural selecting methods. The synchronizing detections 45 detect the start location of transfer data and perform the settings of the counters 43 and 44. As a result, the numbers of pin of the disk control LSI and the signal processing LSI are reduced and the wiring amount of a device substrate is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device using a disk such as a magnetic disk, an optical disk, a magneto-optical disk, and more particularly to a disk control LSI and a signal processing L thereof.
It is related to SI.

[0002]

2. Description of the Related Art A conventional disk device will be described with reference to FIGS.

FIG. 2 is a block diagram showing the configuration of an information processing system including a disk device. Disk device 1
Is composed of a disk control device 2 and a drive device 3. The disk control device 2 is a disk control LSI that controls the host interface 5 that interfaces with the host computer 6 and the drive device 3 and transfers data.
10, a buffer memory 8 for holding data transmitted / received to / from the host computer 6, and a microprocessor 4 for controlling the whole. The disk control LSI 10 may be integrated into an LSI together with other processing parts. The drive device 3 includes a signal processing LSI 20 and a recording / reproducing amplifier 7.

FIG. 3 shows a disk control LSI in a conventional disk device disclosed in Japanese Patent Laid-Open No. Hei 1-193923.
10 is a block diagram showing a connection between the signal processing LSI 20 and the signal processing LSI 20. FIG. The signal processing LSI 20 is provided with an encoding / decoding circuit 21 for encoding data into a storage code (hereinafter referred to as a recording code) on the disk and for decoding the storage code, and a recording / reproducing circuit 22 for recording / reproducing on / from a magnetic disk. . The encoding / decoding circuit 21 and the recording / reproducing circuit 22 are integrated into one or more chips.

Disk control LSI 10 and signal processing L
The input / output terminals of SI20 are connected by a serial signal line. When writing to a disc, the disc control LSI 10
The data processed in parallel inside is converted into serial data by the parallel-serial conversion circuit 17 and sent to the signal processing LSI 20. Then, the signal processing LSI 2
Within 0, it is encoded as parallel data by the serial / parallel conversion circuit 16 and written to the disc. When reading data, the decoded data is the signal processing LSI 2
The data is converted into serial data by the parallel-serial conversion circuit 17 in 0 and sent to the disk control LSI 10.
Then, the serial-parallel conversion circuit 16 in the disk control LSI 10 processes the data after converting it into parallel data.

[0006] Further, as the data transfer speed to the medium has been increased, it has become difficult to serially transfer data between LSIs. Therefore, the disk control LSI
A method of transferring a parallel signal between the signal processing LSI 10 and the signal processing LSI 20 has been adopted.

However, the transfer bus width is practically limited to a power of 2 because it is based on a unit for performing internal processing.

[0008]

In the future, it is expected that the data transfer rate to the media will be further increased and the number of parallel signal lines for transferring data between LSIs will need to be increased.

However, increasing the bit width of the transfer data causes an increase in the number of LSI outputs, which is disadvantageous in terms of simultaneous switching noise and power consumption.

In particular, when an analog processing circuit is included in the signal processing LSI 20 that transfers data to and from the disk control LSI 10, noise caused by the digital section increases the data error rate at the time of reading.

Further, due to the miniaturization of the disk device,
It is necessary to reduce the area of the disk device substrate,
It is necessary to reduce the package size, that is, the number of pins and the amount of wiring on the device substrate. Increasing the number of bits of transfer data has a problem that the number of LSI pins of both the disk control LSI 10 and the signal processing LSI 20 is increased, and at the same time, the wiring amount of the board is increased. Further, when increasing the number of LSI output pins, it is necessary to increase the number of power supply and ground pins in accordance with the increase in output, which further increases the number of pins.

From the above points, it is necessary to select an appropriate value for the transfer data width according to the data transfer rate.

However, in the conventional configuration, when the LSIs are connected in parallel, the bit width of the transfer data is a divisor of the processing data width of the disk control LSI 10 and the signal processing LS.
It had to be a multiple or submultiple of the I20 data width.
Therefore, when the disk control LSI 10 process is performed in units of bytes (8 bits), the transfer data widths are 1, 2, 4,
There is a problem that the transfer data width is limited to any one of 8 and there is little freedom in setting the transfer data width.

Further, in the configuration shown in FIG. 3, since the boundary of the internal processing data of the disk control LSI 10 needs to match the boundary of the transfer data, the transfer data is also output within the signal processing LSI 20 at the output boundary. However, there is a problem that the circuit scale and power consumption increase.

Further, in the conventional configuration, the signal processing LSI
Even when the synchronization detection is performed in 20, the disk control LSI 10 needs to perform the synchronization detection again, which causes a problem that the circuit scale increases.

According to the present invention, in order to reduce the number of pins of the LSI and the wiring amount of the device substrate, the disk control LSI 10
In the data transfer between the signal processing LSI 20 and the signal processing LSI 20, the transfer data width can be arbitrarily set according to the transfer speed.

The present invention also provides a disk control LSI 10
An object of the present invention is to provide a method for aligning data after transfer to the boundary of internal processing data when the transfer data width between the signal processing LSI 20 and the signal processing LSI 20 is different from the processing data.

Furthermore, the present invention provides a disk control LSI 1
It is an object of the present invention to provide a method with a small circuit scale for aligning the data after transfer to the boundary of the internally processed data in the 0 and the signal processing LSI 20.

Further, according to the present invention, the disc control L which can be connected to various signal processing LSIs 20 or disc control LSIs 10 by arbitrarily setting the transfer data width.
The purpose is to realize the SI 10 and the signal processing LSI 20.

[0020]

In order to achieve the above object, the present invention provides a disk control LSI and a signal processing LS.
In I, by correcting the shift in bit units,
It enables conversion of arbitrary data width.

For this purpose, the disk control LSI and the signal processing LSI are provided with a data width conversion circuit having a bit deviation correcting function. The data width conversion circuit temporarily stores the amount of data that is to be transferred in units of internal processing words and the previous data that was not transferred due to the bit shift that occurred at the time of output. To output. Similarly, the data sent in the transfer unit is similarly stored and output in the unit of the internal processing word. Which part to output from the stored data is instructed by the counting means described later.

Further, the disk control LSI and the signal processing LSI are arranged so that the transfer data can be synchronized in units of processing words.
A synchronization function is provided in one or both. The synchronization function detects a leading delimiter in the transfer data and generates bit position information for the data width conversion circuit for correcting the bit shift of the transfer data. Sync pattern detection
This is performed by detecting the presence of data that matches a predetermined data pattern from the data stored in the data width conversion circuit, or by the synchronization information sent using a signal line different from the transfer data.

In the data width conversion circuit, it is necessary to correct the bit shift each time data is input / output. For this purpose, counting means for counting the number of transfer bits is provided. The counting means counts the total number of bits of the data transferred to the data width conversion circuit for each transfer, using the number of bits of the processing word as a modulus, and determines whether input / output is possible in processing word units. In addition, the number of untransferred bits, which is a surplus as a result of input / output, is given to the data width conversion circuit. When the processing word unit is smaller than the transfer unit, the processing word unit is counted for each transfer, and the transfer word unit is modulo.

According to the above method, when the processing word length and the transfer word length are not in a simple integral multiple relationship, the transfer in the transfer word unit is not an integral multiple relationship with respect to the input / output in the processing word unit. The bit shift caused by is corrected for each transfer or each input / output.

[0025]

According to the present invention, at the time of writing, the disk control L
The recording data of the processing word unit of the disk control LSI output from the SI is converted into an arbitrary number of bits and transferred to the signal processing circuit as transfer data of a plurality of times. The data transferred by a plurality of times of transfer is encoded in a unit of processing word of the signal processing circuit of one time or a plurality of times and recorded on the disc.

At the time of reading, the data recorded on the disk is reproduced / decoded by the recording / reproducing circuit, and is read in processing word units of the signal processing circuit. The read data is sent to the disk control LSI as transfer data of one time or a plurality of times, and is processed in processing word units of the disk control LSI.

[0027]

EXAMPLE An example in which the present invention is applied to a magnetic disk will be described below with reference to FIGS. 1 and 4 to 12.

FIG. 1 shows a disk control LSI according to the present invention.
10 is a block diagram of the signal processing LSI 20 and the signal processing LSI 20. FIG.

The disk control LSI 10 includes a drive control circuit 15, data width conversion circuits 41 and 42, and a counter 4.
4 and synchronization detection 45. Signal processing LSI 20
Is a recording / reproducing circuit 22, an encoding / decoding circuit 21, a VFO.
23 (Variable Frequency Oscillator), frequency division / multiplication circuit 24, data width conversion circuits 41, 42, synchronization detection 4
5, counter 43. Disk control LSI1
0 and the signal processing LSI 20 have transfer data signal lines 31,
The transfer clock signal line 33 and the control signal line 32 are connected.

The drive control circuit 15 controls the operation timing and the like of the drive device, the synchronization detection 45, the counter 4
Instruct 4 to start / end the operation. In addition, the control signal line 3
The signal processing LSI 20 is instructed to read and write via 2. Further, data is input / output via the data width conversion circuits 41 and 42.

The data width conversion circuits 41 and 42 convert the bus width so that the drive control circuit 15 inputs / outputs data to / from the transfer data signal line 31, which is an external bus. The synchronization detection unit 45 is connected to the data width conversion circuit 42 and detects a synchronization pattern in units of processed data words from the input data. The counter 43 divides the data transfer into word units from the transfer clock signal line 33 that serves as a reference for data transfer,
Drive control circuit 15 and data width conversion circuits 41, 4
2. Notify the transfer status to 2.

The recording / reproducing circuit 22 receives a recording code, which is a digital code, from the encoding / decoding circuit 21, converts it into an analog recording signal, inputs / outputs it to / from the recording / reproducing amplifier 7, and outputs it to the encoding / decoding circuit 21 as a recording code. Tell. The encoding / decoding circuit 21 is connected to the transfer data signal line 31 via the data width conversion circuits 41 and 42, and performs encoding and decoding between transfer data and recording data. The VFO 23 supplies a clock synchronized with the recording / reproducing signal. Frequency division / multiplication circuit 24
Converts the clock generated by the VFO 23 into a frequency suitable for transfer and sends it to the counter 43. Data width conversion circuit 4
1, 42, the synchronization detection 45, and the counter 43 have the same configuration as the disk control LSI 10 and convert the bus width. The counter 43 also generates a transfer clock and outputs it to the transfer clock signal line 33.

The drive control circuit 15 in the disk control LSI 10 inputs / outputs data in units of processed data words. The conversion between the data width of the processed data word unit and the data width of the transfer data signal line 31 is performed by temporarily storing the data output of the drive control circuit 15 and the input data from the transfer data signal line 31 in the data width conversion circuits 41 and 42. This is done by outputting in the required data width unit. Disk control LS
When I10 inputs data from the signal processing LSI 20, the synchronization detection 45 checks whether the data stored in the data width conversion circuit 42 matches a predetermined synchronization pattern, and when the data matches, stores it in the data width conversion circuit 42. By sending the generated data to the drive control circuit 15, the heads of the transferred transfer data and the processed data word are aligned. After that, the counter 44 counts the number of bits of the transfer data, divides the data every time the data stored in the data width conversion circuit 42 reaches a processing data word unit, and outputs a processing clock for outputting to the drive control circuit 15. Occur. When data is output from the disk control LSI 10 to the signal processing LSI 20, the data stored in the data width conversion circuit 41 is output while the number of bits of transfer data is counted by the counter 44. Also, the processing clock is generated in the same way as when inputting,
Data width conversion circuit 41 every time the processing data word unit is reached
Is input from the drive control circuit 15. If the processed data word is not a multiple of the transfer code, bits that are not transferred remain in the data width conversion circuits 41 and 42 for both data input and output. Next, the data width conversion circuits 41 and 4
The data to be stored in 2 shifts and stores the input data or the transfer residual data so as not to destroy the remaining data, and shifts the data by using the value of the counter 44 at the time of output to output the data shift. Make a correction.

In the signal processing LSI 20, the disk control L
The data width conversion is performed by the same configuration as the SI 10, and the data transfer with the disk control LSI 10 is performed. further,
In the signal processing LSI 20, the VFO 23 is used to generate a recording / reproducing clock which is a clock used when the recording / reproducing circuit 22 performs recording / reproducing on / from the disc. During reproduction, the VFO 23 is controlled so that the reproduction signal and the recording / reproduction clock are synchronized. The recording / reproducing clock generated by the VFO 23 is generated by the frequency division / multiplication circuit 24 to generate a bit reference clock corresponding to the bit of the read / write code.
The counter 43 divides the bit reference clock to generate a transfer clock for transfer with the disk control LSI 10. Since the bit reference clock is a signal used in the LSI, a higher frequency than the transfer clock output to the outside can be used. Also, the signal processing LS
A recording data clock which is a clock of a read / write code unit which is a data transfer unit in I20 is generated using a transfer clock or a bit reference clock.

Next, when data is read from the disk for the operations of the respective parts in FIG. 1, data transfer is performed between the disk control LSI 10 and the signal processing LSI 20 which perform 8-bit processing using the 3-bit transfer data signal line 31. A case will be described as an example.

First, the drive control circuit 15 in the disk control LSI 10 sends a signal processing L through the control signal line 32.
Instruct the SI 20 to read. The signal processing LSI 20 instructed to read the signal reads the signal from the recording / reproducing amplifier 7 and reproduces / decodes the data, and then the disk control LSI
Send to 10.

First, the analog signal read from the recording / reproducing amplifier 7 is discriminated into a recording code by the recording / reproducing circuit 22 and sent to the encoding / decoding circuit 21. At the same time, a clock component is extracted from the analog signal or the discriminated data and sent to the VFO 23. The VFO 23 uses the sent clock component to generate a stable clock synchronized with the recording code. The clock generated by the VFO 23 is sent to the recording / reproducing circuit 22 and the encoding / decoding circuit 21, and is used for data discrimination and decoding of the recording code.

Further, the clock generated by the VFO 23 is supplied to the encoding / decoding circuit 21 by the frequency division / multiplication circuit 24.
Is subjected to frequency division and multiplication by a bit reference clock for converting an 8-bit read / write code generated after decoding into a 3-bit width transfer code.

The bit reference clock is most preferably a bit-based clock, but when the frequency is too high, a clock having a higher internal frequency of the transfer clock or the recording data clock or a multiple thereof is used. Alternatively, a clock having a frequency that is the least common multiple of the frequencies of the transfer clock and the recording data clock may be used. If the frequency of the recording data clock is too high, a simple serial-parallel conversion circuit is used in the encoding / decoding circuit 21 to perform low-frequency parallel transfer to the data width conversion circuit 41. Good.

When the internal frequency of the VFO 23 is higher than the bit reference clock, the frequency is divided to generate the bit reference clock. If the two frequencies are close to each other, the clock of the VFO 23 may be thinned out to generate the bit reference clock. In generating the bit reference clock shown in FIG.
This is an example of thinning out the bit reference clock and the transfer clock when the internal frequency of 23 is 9 times the recording data clock. One pulse is thinned out from a pulse consisting of 9 waves to obtain a bit reference clock, and the bit reference clock is divided by 3 to obtain a transfer clock. The intervals of the transfer clock pulses are not constant, but this does not cause a big problem except that the transfer speed is reduced by 11% with respect to the minimum clock cycle.

When the internal frequency of the VFO 23 is lower than the bit reference clock, it is multiplied to generate the bit reference clock.

At the time of multiplication, or when the internal frequency of the VFO 23 is higher than the bit reference clock, but an appropriate frequency cannot be selected, P synchronized with the read / write code transfer clock is used.
It is preferable to generate the bit reference clock using an LL oscillator or the like. In the example shown in FIG. 6, when the clock is generated without thinning using the PLL oscillator or the like, the minimum interval of the transfer clock can be improved by 12.5%.

The counter 43 generates a transfer clock and a recording data clock from the bit reference clock.
FIG. 7 shows a configuration example of the counter 43 when the transfer clock is used as the bit reference clock.

The counter 43 comprises a 3-bit latch 72 and an adder 71. The 3-bit latch 72 stores the previous output value. The adder 71 outputs a value obtained by adding 3 to the stored value modulo 8. The operation of the counter 43 will be described with reference to FIG. The transfer clock is applied once as a clock each time the 3-bit transfer is performed once, and the 3-bit latch 72 is updated and incremented by 3. At this time, a carry signal is generated once every 8/3. This carry signal is used as a frequency division output for the recording data clock. The pulse interval of the recording data clock is not constant, but the deviation is the maximum transfer clock width, and since it is a signal used in the LSI that operates with the transfer clock, the data output timing of the encoding / decoding circuit 21 is changed. There is no particular problem unless the change timing of the recording data clock is overlapped.
If the transfer clock is generated in the example of FIG. 6, the output data of the encoding / decoding circuit 21 may be determined from the decimated pulse during the 3-bit reference clock.

The counter 43 can also be realized by a combination of a counter having an arbitrary eight value such as a binary counter or a Johnson counter and a decoder for decoding the count output. The recording data clock is supplied from the encoding / decoding circuit 21, and the counter 43 is supplied to the encoding / decoding circuit 21.
It may be operated in synchronization with.

The data decoded by the encoding / decoding circuit 21 is synchronized with the recording data clock, and the data width conversion circuit 4
Sent to 1.

As shown in FIG. 4, the data width conversion circuit 41 includes a latch 51 for temporarily holding transfer data and a latch 5 for holding the transfer data.
Selector 52 for selecting an output from the data held in 1
It consists of a.

In the latch 51, 8 bits of input data and 2 bits of the maximum untransferred portion of the previous data are latched in synchronization with the recording data clock. When the input data change timing is synchronized with the recording data clock and can be handled in the same manner as the latch 51 output, the input data latch 51 may be omitted.

The selector 52a outputs the 10 bits held in the latch 51 to the transfer data signal line 31 3
Select a bit. The correspondence between the data in the latch 51 and the output data will be described with reference to FIG.

In FIG. 9, data is input from the encoding / decoding circuit 21 to the data width conversion circuit 41 in the order of A0-7, B0-7, C0-7, and the input data is sequentially input from A0 by 3 bits. It is a conversion example of outputting and transferring. Data A0-7
Is input, it is output in two steps in the order of A0-2 and A3-5. The remaining A6-7 is next encoded and decoded by the encoding / decoding circuit 21.
It is output at the same time as B0 sent from. Therefore, A6-
B0-7 is input before the output of 7, and A6-7 is latched in the higher order of the latch 51 as a transfer remaining bit. And
A6-7 and B0 are output as the third output. Similarly, when B1-B3 and B4-6 are transferred, C0-
Latch B6-7 with input of 7. At this time, B6
Has been output, but to make the operation the same as A6,
Latch once. Actually, B6 latched as the transfer remaining bit is not output and is discarded, and B7 and C0-1 are output. When C2-C4 and C5-7 are transferred,
Since there are no transfer remaining bits, the same conversion as in A0-7 is repeated thereafter. At the time of the next transfer, C6-7 is once latched as a transfer remaining bit and discarded, like B6. The data output to the transfer data signal line 31 is shown in FIG.
In the bit selection number for the latch contents shown in,
2, 5, 0, 3, 6, 1, 4, 7 are selected in this order. That is, the selector 52a operates as a barrel shifter with the bit selection number as the shift amount. In this example, the count value of FIG. 8 can be used as the bit selection number. The recording data clock in FIG. 8 coincides with the data input timing from the encoding / decoding circuit 21.

In addition to the correspondence shown in FIG. 9, if the combination is such that all bits are transmitted, the correspondence of bits can be selected arbitrarily.

Further, the order of the latch 51 and the selector 52a is reversed, the bit correspondence of the input data to the latch 51 is dynamically changed at the time of fetching to the latch 51, and the bit arrangement of the latch 51 to the output is fixed. Good. In this case, it is necessary to update the latch 51 for each transfer clock, or to provide a separate selector for changing the output of the latch 51 with the transfer clock.

When the frequency of the bit reference clock is set to a common multiple of the frequency of the transfer clock and the frequency of the recording data clock, the latch 51 is composed of a shift register driven by the bit reference clock, and the selector 5 is used.
2a can be omitted. At this time, the transfer clock and the recording data clock can be supplied by individual frequency division using the bit reference clock as a common reference clock. The two divider circuits require no synchronization other than the bit reference clock. If redundant bits are added to the read / write code to make it a multiple of the width of the transfer data signal line 31, the bit reference clock can be used as the transfer clock.

From the 3-bit transfer data and transfer clock sent from the signal processing LSI 20 as described above,
In the disk control LSI 10, it is used after being converted into an 8-bit processing data word and a processing clock.

FIG. 5 is a block diagram of the data width conversion circuit 42 in which the block diagram of the data width conversion circuit 41 (FIG. 4) is rewritten for the case where the output width is larger than the input width. The data width conversion circuit 42 includes a shift register 53a,
b and c (subscripts are omitted below) and a selector 52b. If the bit correspondence between the processed data word and the transfer data is different from that shown in FIG. 9, SR cannot be used. In that case, as the data width conversion circuit 42, the configuration of FIG. 4 in which the number of feedback signals is changed to 7 can be used.

The input data is taken into the shift register 53 at every transfer clock given from the signal processing LSI 20, and is stored in the shift register 53 until an 8-bit processed data word is obtained.

In the synchronization detection 45, synchronization detection is performed on the data stored in the shift register 53, and synchronization is performed in units of processed data words. The operation of the synchronization detection 45 will be described below with reference to FIGS. 10 and 11. The synchronization detection 45 includes a coincidence detection 62 for detecting a coincidence with a predetermined synchronization pattern for each deviation pattern, and a synchronization control 61 for obtaining a bit deviation amount from the result and inhibiting a resynchronization operation after the synchronization detection. .

The sync detection 45 is provided with three coincidence detections 62 for the sync detection data sent from the data width conversion circuit 42, and each coincidence detection 62 has three different deviation patterns shown in FIG. A match check with a predetermined bit pattern is performed. The comparison result of each match detection 62 is the synchronous control 61.
Sent to. In the synchronization control 61, the first coincident time is set as the head of valid data, and the bit deviation amount is obtained depending on which coincidence detection 62 coincides. Then, the counter 44 is set with the bit shift amount of the matched bit shift pattern as an initial value. Further, the synchronization control 61 stores that the synchronization detection is performed and invalidates the subsequent synchronization detection operation. This prevents the counter from being reset even when the data string contains data that matches the synchronization pattern. It is also possible to use the signal used in the synchronization detection 45 and indicating that the synchronization has been detected for the operation control of the drive control circuit 15.

In the synchronization detection 45, the coincidence detection 62 may be simplified by inspecting a characteristic part of a predetermined synchronization pattern. At this time, match detection 6
In order to eliminate the possibility of erroneous synchronization detection by simplifying step 2, it is possible to perform detailed coincidence detection on the processed data word output by the selector 52b after the coincidence detection. When a mismatch is detected in the detailed match detection, the information indicating the sync detection may be erased and the sync may be detected again.

Further, in order to ensure a reliable synchronization detecting operation, a predetermined pattern may be inserted in the transfer data in the signal processing LSI 20. When performing synchronization detection in the signal processing LSI 20, the detected synchronization pattern may be replaced with a predetermined pattern. When the synchronization is detected in the signal processing LSI 20 and the predetermined pattern is inserted into the transfer data, the predetermined pattern is inserted before the synchronization pattern is detected by the signal processing LSI 20 to thereby insert the predetermined pattern between the signal processing LSI 20 and the disk control LSI 10. When the synchronization is secured and the synchronization pattern is actually detected, the signal processing L
The SI 20 may be synchronized with the synchronization secured in advance. In addition, when the synchronization pattern is inserted or replaced in the signal processing LSI 20, the signal processing LS
The information about I20 is replaced with a portion other than the characteristic portion of the synchronization pattern, and the disk control LSI 10 detects the synchronization 4
The processing of the disk control LSI 10 may be changed based on the content of the information regarding the signal processing LSI 20 read at the time of 5.

It should be noted that at the time of output of transfer data, synchronous processing may be performed in units of processing words at the transfer destination, and the head of the data may be adjusted to a fixed relationship with the transfer boundary. For example, when performing a synchronization process such that the first bit of the synchronization pattern always appears in a specific bit of the transfer bus, the synchronization detection 45 of the transfer destination does not have to deal with the bit shift, and therefore the coincidence detection 62 is set to one. be able to.

The counter 44, like the signal processing LSI 20, has the configuration of FIG. The bit position signal sent to the selector 52b needs to take three values. Since the carry signal, that is, the value of the counter 44 immediately after the processing clock is generated is a value modulo 3, the counter 4
The value of 4 can be used as it is as a bit position signal. The value of the counter 44 may be decoded and given so as to match the configuration of the data width conversion circuits 41 and 42.

A counter for counting the bit position signal with the processing clock may be separately prepared. Further, the information indicating the completion of the synchronization detection stored in the synchronization control 61 may also be used as the synchronization position information. In this case, the synchronization position information is stored in the synchronization control 61, is changed so as to show the following bit shift pattern for each processing clock, and is cycled three times. The same value can be obtained when using 44 outputs. Note that if the processed data word width is a multiple of the transfer data width, the bit shift will not change with the transfer, so the sync detection 45 that does not include the function to change the sync position information after the sync detection is performed. Alternatively, the synchronization position information may be provided to the data width conversion circuits 41 and 42.

At the time of writing, it is almost the same as at the time of reading, except that the disk control LSI 10 outputs the transfer data and the signal processing LSI 20 becomes the receiving side. As the transfer clock, the signal processing LSI 20 generates a recording data clock in the same manner as when the recording clock is read from the recording clock,
It is supplied to the disk control LSI 10. The recording clock is
Microprocessor 4 directly or disk control LS
It is set in the signal processing LSI 20 via I10 or the like. It may be supplied from a clock generation circuit different from that at the time of reading.
Further, the transfer clock may be generated by the disk control LSI 10 and synchronized by the signal processing LSI 20.

In the configuration of FIG. 1, the data from the disk control LSI 10 is synchronized in the signal processing LSI 20 on a recording code basis. If the recording / reproducing of the signal processing LSI 20 is completely transparent in bit units, the synchronization processing in the signal processing LSI 20 may be omitted. When reading, signal processing LSI
When the synchronization check is performed in recording code units within 20, when writing, the transfer data is subjected to synchronization processing in recording code units.

With the above configuration, the disk control LSI 1
The processing data width of 0 and the encoding / decoding circuit 21 can be set independently of the transfer width. In the above description, 8-bit and 3-bit conversion is taken as an example, but latch 5
1, selectors 52a, b, synchronization detection 45, counter 4
It can be used for arbitrary data width conversion by changing the number of corresponding bits of 3, 44. Even when the read / write code width and the transfer data width are different, the disk control LS
I10 and the signal processing LSI 20 can be connected if the widths of the transfer data signal lines 31 are the same, only the number of corresponding bits for each data width conversion is different. Therefore, the disk control LSI
The internal processing data widths of 10 and the encoding / decoding circuit 21 can be set individually.

On the other hand, when the internal processing data widths of the disk control LSI 10 and the encoding / decoding circuit 21 are the same, or the disk control LSI 1 is separately provided in the signal processing LSI 20.
In the case of performing the processing according to the internal processing data width of 0, it is possible to set the synchronization detection in the signal processing LSI 20 and perform the external synchronization type data transfer in which the synchronization position information is sent to the disk control LSI 10 as an external signal. At this time, the synchronization detection 45 can be removed from the disk control LSI 10.

The structure and operation in the case of external synchronous data transfer will be described with reference to FIG. 12, the control information 34 is added to the connection between the disk control LSI 10 and the signal processing LSI 20 as compared with FIG.
The synchronization detection 45 is excluded from 0. Also, the signal processing L
In SI 20, it is assumed that the encoding / decoding circuit 21 performs synchronization detection, and instead of the synchronization detection 45, the synchronization control 46 coupled to the encoding / decoding circuit 21 sends a synchronization signal to the counter 43. At the time of reading from the disc, synchronization detection is performed in the signal processing LSI 20, synchronization information is set based on the synchronization position information, and the disk control LSI 10 uses the synchronization information and the transfer clock to perform the data width conversion circuit. 41,4
Pass the sync position information to 2. At this time, the synchronization information may be sent from the beginning of the transfer data, and the synchronization information may be sent to the drive control circuit 15 as well, thereby eliminating the detection circuit of the data start position from the drive control circuit 15.

At the time of writing, the counter in the disk control LSI 10 generates a transfer clock based on the processing clock and the synchronization information generated by the signal processing LSI 20, and the data output of the drive control circuit 15 is synchronized with the transfer clock. On the contrary, the external synchronization information signal is bidirectional, and at the time of writing, the disk control LSI 10 outputs the signal processing LSI.
The synchronization information may be given to 20.

As described above, in this embodiment, the transfer data width is set to the disk control LSI 10 and the signal processing LSI 20.
It can be set arbitrarily regardless of the internal processing word length of. The data width conversion circuit 41, shown in the present embodiment,
By preparing a plurality of 42, synchronization detection 45, and counters 43 and 44, the transfer data width and the bit arrangement can be changed outside the transfer period. The transfer data width and bit arrangement are set using an external terminal or a register writable from the μP. The external terminal may be dedicated or may be combined with other functions. If it is not necessary to change it while the device is operating, it may be set at reset. In addition, the constituent elements can be shared. In the case of the counters 43 and 44 shown in FIG. 7, the constants to be added may be changed and the counters 43 and 44 may be shared. The data width conversion circuits 41 and 42 and the synchronization detection 45 can also be partially shared. In addition to the function of dynamically changing the bit arrangement, a predetermined synchronization pattern is selected so as not to overlap in a plurality of transfer data widths and bit arrangements, and the synchronization control 61 of the synchronization detection 45 is made common to all at the time of synchronization detection. It is possible to automatically select an appropriate transfer data width and bit arrangement.
At this time, a plurality of combinations to be automatically detected may be prepared so that the combination of the transfer data width and the bit arrangement to be automatically detected can be selected in advance. A disk that uses a function that dynamically changes the transfer data width and bit arrangement to switch between signal processing LSIs 20 having different transfer data width and bit arrangement specifications on the inner and outer peripheries of the disk. The control LSI 10 can be realized.

When synchronization is performed using an external signal,
The synchronous circuit can be removed from the disk control LSI 10 to simplify the circuit.

In this embodiment, a magnetic disk is taken as an example, but it is also applicable to an optical disk, a magneto-optical disk, etc.

[0073]

As described above, according to the present invention, the disk control LSI and the signal processing are processed on the basis of the transfer speed necessary for the data transfer between the disk control LSI and the signal processing LSI and the setting of the appropriate transfer frequency. The transfer bus width between LSIs can be set to an arbitrary number of bits. Therefore, high-speed data transfer can be performed with the minimum number of LSI pins and wiring amount of the board.

Further, according to the present invention, the disk control LS
It is possible to provide a strict synchronization detection circuit in only one of I and the signal processing LSI, and omit one of the synchronization detection circuits or use a simple synchronization detection circuit. Therefore, it is possible to reduce the circuit scale of the disk control LSI and the signal processing LSI.

Furthermore, by preparing a plurality of specifications of the transfer bus and providing a function for easily switching, it is possible to realize a disk control LSI excellent in versatility that can be connected to any signal processing LSI.

Further, by dynamically changing the transfer bus width, it is possible to change the transfer bus width between the inner circumference and the outer circumference of the disk and to switch the signal processing LSIs having different transfer bus specifications. LSI can be realized.

Further, by providing a plurality of specifications of the transfer bus in the signal processing LSI and having a function of easily switching, it is possible to realize a versatile signal processing LSI that can be connected to any disk control LSI.

Furthermore, by providing a plurality of specifications of the transfer bus in both the disk control LSI and the signal processing LSI and providing a function of dynamically switching, a disk device that changes the use of the transfer bus between the inner circumference and the outer circumference of the disk is provided. realizable.

[Brief description of drawings]

FIG. 1 is a diagram showing data transfer between a disk control LSI and a signal processing LSI.

FIG. 2 is a diagram showing a disk device.

FIG. 3 is a diagram showing data transfer between a conventional disk control LSI and a signal processing LSI.

FIG. 4 is a diagram showing a data width conversion circuit 1.

5 is a diagram showing a data width conversion circuit 2. FIG.

FIG. 6 is a diagram showing clock generation by pulse decimation.

FIG. 7 is a diagram showing a configuration of a counter.

FIG. 8 is a diagram showing an operation of a counter.

FIG. 9 is a diagram showing conversion of data width.

FIG. 10 is a diagram showing a synchronization detection circuit.

FIG. 11 is a diagram showing an example of bit shift.

FIG. 12 is a diagram showing external synchronous data transfer between a disk control LSI and a signal processing LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Disk device, 2 ... Disk control device, 3 ... Drive device, 4 ... Microprocessor, 5 ... Host interface, 6 ... Host computer, 7 ... Recording / reproducing amplifier, 8 ... Buffer memory, 10 ... Disk control LSI, 15 ... drive control circuit, 16 ... serial-parallel conversion circuit, 17 ... parallel-serial conversion circuit, 20 ... signal processing LSI, 21 ... encoding / decoding circuit, 22 ... recording / reproducing circuit, 23 ... VFO, 24 ... frequency division / multiplication circuit, 31 ... Transfer data signal line, 32 ... Control signal line, 33 ... Transfer clock signal line, 34 ... Control information, 41, 42 ... Data width conversion circuit, 43, 44 ... Counter, 45 ... Sync detection, 46 ... Sync control, 51 ... Latch, 52a, 52b ... Selector, 53a, 53b, 53c ... Shift register, 61 ... Synchronous control , 62 ... Match detection, 71 ... Adder, 72 ... 3-bit latch.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Toyoro Nogiwa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Micro Software Systems Co., Ltd. System Division (72) Inventor Yoshikatsu Fujii 2880 Kokuzu, Odawara, Kanagawa Hitachi Storage Systems Division (72) Inventor Shoichi Miyazawa 1099 Ozenji, Aso-ku, Kawasaki, Kanagawa Hitachi Systems Development Laboratory Co., Ltd.

Claims (19)

[Claims] 1. An interface between a disk control LSI for controlling a recording operation and a reproducing operation of a disk device and a signal processing circuit for performing recording and reproducing on a disk medium,
Counting means for counting the transferred number of bits and dividing the data each time reaching a predetermined number of bits to give a surplus bit number,
Conversion means for storing transfer data as temporary storage data, and selecting transfer data from the temporary storage data based on the number of surplus bits given by the counting means to convert the transfer width of input and output of the transfer data. And a conversion circuit having a synchronization detecting means for detecting a division that divides transfer data into appropriate processing units and setting the counting means, and the data bus width is converted into a predetermined connection bus width. Transfer method. 2. An interface between a disk control LSI and a signal processing circuit, which counts the number of transferred bits and divides the data each time a predetermined number of bits is reached to give a surplus bit number and counting means for transferring the transferred data. A part of the data is stored as temporary storage data, and the transfer width of the input and output of the transfer data is converted by selecting data from the temporary storage data and the transfer data based on the number of surplus bits given from the counting means. The data bus width is converted into a predetermined connection bus width by a conversion circuit having a conversion unit for converting the transfer data into appropriate processing units and a synchronization detection unit for setting the counting unit by detecting a delimiter. And data transfer method. 3. In a recording and reproducing operation of a disk device, an internal processing data width of a signal processing LSI or a disk control LSI, the signal processing LSI and the disk control LS.
A data transfer method characterized by converting the connection bus width used for data transfer between I and I to make the connection bus width excluding redundant bits for inspecting transfer data a value that is not a power of two. . 4. In a recording and reproducing operation of a disk device, a specific pattern indicating a delimiter of transfer data is inserted into transfer data of a disk control LSI and a signal processing circuit, or a part of the transfer data is specified. A data transfer method characterized by replacing with a pattern. 5. The data transfer method according to claim 1 or 2, wherein at least a part of a predetermined data pattern indicating a head of data to be recorded on a disk is detected in order to detect a break of transfer data. A data transfer method characterized by: 6. The data transfer method according to claim 5, wherein a part of a specific pattern indicating a head of data to be recorded on the disc is detected and the detection signal is detected in order to detect a boundary of the transfer data. Based on a plurality of conversion methods that exist based on the conversion method, after converting the transfer data by the conversion method,
A data transfer system characterized by comprising means for detecting a match with the specific pattern. 7. The data transfer method according to claim 1 or 2, wherein synchronous processing is performed for each processing unit of the transfer destination when the transfer data is output, and the start position of the transfer data is fixed with respect to the transfer boundary. The data transfer method is characterized by simplifying the synchronization detection circuit at the transfer destination. 8. The data transfer method according to claim 1 or 2, wherein a predetermined signal line is used to detect a boundary of transfer data. 9. In a recording and reproducing operation of a disk device, a specific data pattern is used to indicate a delimiter of transfer data between a disk control LSI and a signal processing circuit,
A data transfer system characterized in that a part of the specific pattern includes information indicating an operating state of a disk control LSI and a signal processing circuit. 10. The data transfer system according to claim 1, wherein the data transfer system can be selected from a plurality of data transfer systems having different transfer data widths or transfer data bit arrangements. 11. The data transfer according to claim 10, wherein the transfer data format is identified by detecting a specific pattern from the transfer data, and an appropriate transfer data conversion method is automatically set. method. 12. A signal processing circuit having a function of performing transfer using a plurality of transfer data widths or transfer data bit arrangements, and being capable of data transfer with a signal processing circuit having different transfer data widths or transfer data bit arrangements. Disk control LSI characterized by. 13. A disk control LSI having a function of switching a signal processing circuit having a plurality of different transfer data formats to transfer by changing the transfer data format during operation of the disk device. 14. The disk control according to claim 12, wherein a signal for detecting the head of the record data sent from the outside is used, and thus the function for detecting the head at the time of reproducing the record data is not provided internally. LSI. 15. An internal processing data width is set to a multiple of a transfer data width for transfer with a signal processing device, and a storage means for storing the transfer data as temporary storage data and at least a part of a predetermined synchronization data pattern are temporarily stored. A plurality of coincidence detecting means for detecting coincidence with a plurality of partial storage data composed of a part of data, and a synchronization for judging a bit position in the transfer bus of the synchronization pattern from a coincidence detecting signal generated by the coincidence detecting means. A disk control LSI having a position detecting means and a selecting means for selecting a part of the temporarily stored data, and specifying a portion selected by the selecting means from the synchronous position indicated by the synchronous position detecting means. 16. A signal processing LSI having a function of performing transfer using at least one of the data transfer methods according to claim 1. Description: 17. The signal processing LSI according to claim 16, further comprising a circuit for detecting the head of the recording data and outputting the detected position as an external signal. 18. A disk control LSI according to claim 12 or claim 15 or a signal processing LSI according to claim 16 or 17.
A disk device comprising: 19. An information processing system comprising the disk device according to claim 18.