JPH07321857A - Modulator - Google Patents

Abstract

PURPOSE:To adjust the central frequency of a modulated signal constant without depending on the pattern of a digital signal. CONSTITUTION:An MSK modulated signal provided from the digital signal by a VCO 14 is double multiplied by a multiplier 24, for example, and applied to a comparator 38 of a first PLL circuit 34. At the comparator 38, the phase of an output from a VCO 36 is compared with that of the multiplied output and corresponding to the result, a signal synchronized with the multiplied output is applied to a frequency divider 44 of a second PLL circuit 42 by the VCO 36, frequency-divided and applied to a comparator 48. At the comparator 48, the phase of an oscillated frequency from a reference oscillator 46 is compared with that of the output from the frequency divider 44, an output corresponding to the phase difference is applied to an LPF 50 and a control signal from the LPF 50 is correspondently applied to the VCO 14. Corresponding to this control signal, the central frequency of the MSK modulated signal is controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM modulator, and more particularly to an AFC (Auto Frequency Control) of a modulator used in, for example, MSK and GMSK modulators.

[0002]

2. Description of the Related Art In recent years, in the fields of satellite broadcasting and mobile communication, MSK (Minimum Shift Keying) modulation method and GMSK which are modulation methods capable of narrow band transmission of digital signals.
(Gaussian Filtered MSK) Modulation method is used. MSK and GMSK are described, for example, in "Digital Modulation and Demodulation Technology in Mobile Communications" (Trikeps).

MSK is a phase-continuous frequency shift keying modulation with a modulation index of 0.5, which is modulated with an NRZ signal, and the modulating wave has a constant amplitude and an extremely narrow band modulation spectrum can be obtained. MS
The K modulator 1a is a voltage controlled oscillator (hereinafter, simply referred to as "VCO") as shown in FIG.
scillator) 2. In FIG. 11, 3 is an input terminal to which a digital signal (NRZ) is input, and 4 is an output terminal to which a modulated signal is output.

GMSK is a base band signal (NRZ) of MSK band-limited by a filter having a Gaussian characteristic. By changing the bandwidth of the filter having the Gaussian characteristic, the transmission power spectrum can be controlled, and the band of the modulation spectrum can be further narrowed as compared with MSK. GMSK modulator 1b
As shown in FIG. 12, a Gaussian low-pass filter (hereinafter, simply referred to as “LPF”) 5 can be added to the MSK modulator 1a shown in FIG.

Further, if the switches 6 and 7 are switched in the configuration shown in FIG. 13, MSK / GMS
A modulator corresponding to both K can be constructed. Here, the VCO 2 operates as an FM modulator and can be configured by an LC type oscillator. This is a system in which an FM wave is generated by changing the value of C of an LC oscillator according to an input digital signal.

However, in this method, since the frequency stability of the VCO (FM modulator) 2 composed of the LC type oscillator is poor, the frequency stability of the modulation signal output from the VCO 2 is also poor. It is necessary to stabilize the frequency of the modulation signal. That is, AFC is required. Therefore, a modulator 1c as shown in FIG. 14 has been proposed. The modulator 1c is an improvement of the system of the MSK modulator 1a shown in FIG. 11, in which a part of the output of the VCO 2 is taken out and input to the frequency divider 8a of the PLL circuit 8,
The comparator 8 compares the output of the frequency divider 8a and the output of the reference oscillator 8b.
Phase comparison is performed with c. Then, the output of the comparator 8c is set to the LPF.
8d is averaged and the output of the LPF 8d is added to VCO2 to control the frequency of the modulation signal output from VCO2.
When the number of appearances of the mark and space of the digital signal input from the input terminal 3 is equal, assuming that the frequencies corresponding to the mark and space of the input digital signal are f2 and f1, respectively, the output averaged by the LPF 8d Therefore, the center frequency of VCO2 is fc = (f
The control is performed at a frequency of 1 + f2) / 2. Therefore, the oscillation frequency of the reference oscillator 8b = the center frequency of the modulation signal /
If the frequency division number is selected, even if the frequency of the modulation signal output from the VCO 2 fluctuates, the frequency of the modulation signal can be controlled to be constant by controlling the oscillation frequency of the VCO 2 in the above operation. Further, by dividing the modulated signal by the frequency divider 8a, the modulation index in the signal for frequency comparison is reduced, and the influence of the modulation is reduced.

[0007]

However, in the modulator 1c shown in FIG. 14, when the number of appearances of the mark and the space of the input digital signal is equal, the control can be performed at a predetermined center frequency. If there is a gap in the number of appearances from the space, control is performed at a frequency outside the predetermined center frequency, and the modulated signal cannot be output at a constant center frequency.

Therefore, a main object of the present invention is to provide a modulator capable of outputting a modulation signal at a constant center frequency regardless of the pattern of an input digital signal.

[0009]

SUMMARY OF THE INVENTION A first invention is an FM modulating means for modulating a digital signal to obtain a modulated signal, a multiplying means for multiplying a modulated signal from the FM modulating means, and a digital signal based on an output of the multiplying means. First PLL means for outputting a signal having a frequency equal to the bright line frequency component corresponding to the mark or space, and FM modulating means for adjusting the center frequency of the modulation signal to a predetermined frequency based on the signal output from the first PLL means. Is a modulator including second PLL means for outputting a control signal for controlling the oscillation frequency of.

A second aspect of the present invention is FM modulating means for modulating a digital signal to obtain a modulated signal, voltage controlled oscillating means for converting the modulated signal from the FM modulating means into a predetermined frequency,
Mixing means for mixing the modulated signal from the FM modulating means and the output from the voltage controlled oscillating means to obtain a modulated signal of a predetermined frequency by frequency conversion, multiplying means for multiplying the modulated signal from the mixing means, and output of the multiplying means. Based on the first PLL means for outputting a signal having a frequency equal to the bright line frequency component corresponding to the mark or space of the digital signal based on the first PLL means, and the center frequency of the modulated signal becomes a predetermined frequency based on the signal output from the first PLL means. A second P that outputs a control signal for controlling the oscillation frequency of the voltage controlled oscillation means to
A modulator comprising LL means.

[0011]

In the first aspect of the invention, the modulator is an MSK modulator or a G
In the case of the MSK modulator, AFC is performed using the bright line frequency component generated when the MSK modulated signal from the FM modulating means is multiplied by the multiplying means. Digital signal (binary FSK)
The frequency of the MSK modulated signal corresponding to the space of f1,
When the frequency of the MSK modulated signal corresponding to the mark is f2, when the MSK modulated signal is doubled, for example, bright line frequency components are generated at frequencies f1 × 2 and f2 × 2 corresponding to the mark and space of the digital signal.
Either of the bright line frequency components is extracted by the first PLL means and given to the second PLL means. And
The second PLL means compares it with the reference signal and applies the resulting control signal to the FM modulating means which determines the center frequency of the modulating signal. Therefore, the center frequency of the modulated signal is controlled.

That is, first, a digital signal is applied to the FM modulating means to obtain an MSK modulated signal. When the frequency of the MSK modulated signal corresponding to the space of the digital signal (binary FSK) is f1 and the frequency of the MSK modulated signal corresponding to the mark is f2, when the MSK modulated signal is multiplied by, for example, 2 times, the digital signal Frequencies f1 × 2 and f2 × 2 corresponding to marks and spaces, respectively
A bright line frequency component is generated at. Any one of the bright line frequency components is given to the first PLL means.

In the first PLL means, the comparison means performs phase comparison between the output from the first voltage controlled oscillation means and the multiplied output from the multiplying means, and the output from the comparing means is averaged by the low-pass filter to obtain a control signal. Is applied to the first voltage controlled oscillation means. In this way, the PLL is constructed based on the output from the first voltage controlled oscillation means and the output from the multiplication means,
The output from the first voltage controlled oscillator is synchronized with the bright line frequency component f1 × 2 (or f2 × 2) which is a multiplied output.

Next, the output from the first voltage-controlled oscillating means synchronized with the bright line frequency component which is the multiplied output is supplied to the second PLL.
It is input to the means and the phase is compared with the reference signal. And
Number 1

[0015]

Fp = [(fc-fs / 4) × 2] / M or fp = [(fc + fs / 4) × 2] / M M: frequency division number fc: center frequency of modulated signal fs: bit rate The oscillating frequency of the reference signal from the reference oscillating means is set to fp so as to synchronize with the frequency fp shown, and control is performed.

In the second PLL means, the frequency division output obtained by dividing the output of the first voltage control oscillation means by the frequency division means and the reference signal from the basic oscillation means are phase-compared by the comparison means, and control is performed according to the output. The signal is output from the low pass filter. Then, after all, the bright line spectrum from the multiplied output depends only on the center frequency and the bit rate.
If the control signal output from the LL means, that is, the low-pass filter is given to the control terminal of the FM modulating means that determines the center frequency of the modulation signal, as a result, it is constant at the center frequency of the modulation signal without depending on the pattern of the digital signal. Can be adjusted to

In the second aspect of the invention, the digital signal is FM-modulated by the FM modulating means, the output thereof is given to the mixing means and mixed with the output from the voltage controlled oscillating means to obtain a modulated signal having a constant center frequency. Modulators such as MSK
When the modulator or the GMSK modulator is used, AFC is performed by utilizing the bright line spectrum generated by multiplying the MSK modulated signal output from the mixing means by the multiplying means.
In other respects, it operates similarly to the first invention. That is, if the output from the first PLL means is given to the second PLL means and the control signal from the second PLL means is given to the circuit for determining the center frequency of the modulation signal, that is, the voltage control oscillation means, the modulation signal is oscillated by the voltage control oscillation means. It is controlled by the frequency, and as a result, the center frequency of the modulated signal can be adjusted to be constant without depending on the pattern of the digital signal.

[0018]

According to the present invention, the center frequency of the modulated signal can be adjusted to be constant without depending on the pattern of the digital signal. The above objects of the present invention, other objects,
Features and advantages will become more apparent from the following detailed description of the embodiments with reference to the drawings.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An MSK modulator 10 of this embodiment shown in FIG.
Is an input terminal 1 to which a digital signal (NRZ) is input
2, the digital signal is FM-modulated by the VCO 14 which operates as an FM modulator to obtain an MSK-modulated signal. The VCO 14 can be realized by, for example, an LC type oscillator, and is configured as shown in FIG. 2, for example. In Figure 2, LC
A Clapp oscillator, which is a type of tuning oscillator, is shown.
This circuit constitutes a high frequency resonance circuit, and an FM wave, that is, a modulation signal is generated by changing the capacitance of this circuit according to a digital signal. The variable capacitance diode C1 is used to change the capacitance. A digital signal is input from the input terminal 16 and an appropriate reverse bias voltage (LP
The control signal from F50) is applied to change the voltage across the variable capacitance diode C3 and thus the capacitance, and the output terminal 2
From 0, an MSK modulated signal is output.

Here, the oscillation condition of this LC tuning oscillation circuit is expressed by equation 2.

[0021]

[Equation 2] ω ² = (1 / L) · {(1 / C1) + (1 / C
2) + (1 / C3)} Since the values of L, C2, and C3 shown in Equation 2 are fixed, the output of the variable capacitance diode C1 is changed by changing the capacitance of the variable capacitance diode C1 according to the digital signal from the input terminal 16. The output frequency ω of the MSK modulated signal output from the terminal changes. The output frequency ω is finely adjusted by the control signal from the LPF 50. That is, a control signal is given from the control terminal 18 according to the deviation from the center frequency of the MSK modulation signal, and the deviation is corrected. The inductor L1 has a function of preventing the high frequency current from flowing backward in the a direction, and the capacitors C4 and C5 remove the DC component.
Further, the base potential of the transistor TR is determined by the resistors R1 and R2, and the bias current is determined by the resistor R3. The capacitor C6 serves to AC-ground the collector of the transistor TR.

M from the VCO 14 constructed in this way
The SK modulation signal is given to the filter 22 and the multiplication circuit 24. The filter 22 removes unnecessary frequency components from the MSK modulated signal, and outputs only the necessary modulated signal from the output terminal 26. The multiplier 24 is configured, for example, as shown in FIG. The multiplier 24 shown in FIG. 3 includes a full-wave rectifier circuit 26 and an LPF 28. Full wave rectifier circuit 26
When a signal as shown in FIG. 4A is applied from the primary side terminal 30 of FIG.
When the signal shown in is obtained and given to the LPF 28, L
High frequency components are removed by the PF 28, and a doubled output as shown in FIG. 4C is obtained.

The output from the multiplier 24 is given to the first PLL circuit 34. The first PLL circuit 34 includes a VCO 36 that outputs a single frequency, an output from the multiplier 24, and a VC.
It includes a comparator 38 and a LPF 40 for comparing the phase with the output from O36. The LPF 40 averages the output of the comparator 38 and outputs a control signal for controlling the output of the VCO 36 to match the frequency of the bright line spectrum which is the multiplied output. Therefore, from the first PLL circuit 34 to the second P
The LL circuit 42 is supplied with a single frequency output synchronized with the bright line spectrum corresponding to the mark or space of the digital signal.

The second PLL circuit 42 divides the output of the VCO 36 by a frequency divider 44, a reference oscillator 46 that oscillates a reference signal, for example, using a crystal, and the phase of the output of the frequency divider 44 and the output of the reference oscillator 46. And a LPF 50 for averaging the output of the comparator 48 to generate a control signal for controlling the oscillation frequency of the VCO 14. Therefore, the second PLL circuit 42 generates a control signal for controlling the oscillation frequency of the VCO 14 based on the output of the VCO 36.

In the MSK modulator 10 thus formed, when the oscillation frequency fp of the reference oscillator 46 is set as shown in the equation 1, the multiplied output from the multiplier 24 is only the center frequency fc and the bit rate fs. The control signal generated in the second PLL circuit 42 is VC
If it is given to the control terminal 18 of O14, as a result, the center frequency of the MSK modulated signal can be adjusted to be constant without depending on the pattern of the digital signal.

A more specific description will now be given with reference to FIGS. MSK is a kind of FSK, where f0 and f1 are frequencies corresponding to digital signals "0" (space) and "1" (mark), respectively, and a bit rate is B, f1-f0 = B / 2. The relationship is established. Now, to satisfy this formula, B = 4
0.96 Mbps, f0 = 40.96 MHz, f1 = 6
The frequency is 1.44 MHz.

Then, when a digital signal of "0, 1, 0, 1" shown in FIG. 5 (A) is input from the input terminal 12,
In the VCO 14, the MSK modulation signal (40.
96 Mbps) is obtained. This MSK modulated signal has one waveform in one data period if the digital signal is "0" and 1.5 waveforms in one data period if the data is "1". That is, if the digital signal is "0", 40.96 MHz shown in FIG.
If the frequency f0 of the digital signal is "1",
The frequency f1 of 61.44 MHz shown in (E) is output from the VCO 14 as an MSK modulation signal.

Here, it is assumed that the MSK modulation signal from the VCO 14 has a frequency of center frequency (for example, 51.2 MHz) + Δ (deviation). Center frequency is 5
The frequency of 1.2MHz is generally f0 (40.96M
This is because the center frequency is obtained by averaging (Hz) and f1 (61.44 MHz). Further, Δ (deviation) occurs due to temperature change and the like.

This MSK modulated signal is applied to the multiplier 24 and is multiplied by, for example, to obtain a multiplied output as shown in FIG. 5 (F). This multiplied output is 81.92 MHz shown in FIG. 5 (G) and 122.88 MH shown in FIG. 5 (H).
Includes the bright line frequency component of z. Thus, the multiplier 24 outputs the bright line frequency component of either 81.92 MHz or 122.88 MHz. Therefore, when the MSK modulated signal is 51.2 MHz + Δ, the multiplier 24 gives the output of 102.4 MHz (bright line frequency component) + 2Δ, which is twice the output, to the first PLL circuit 34.

The reason why the output obtained by multiplying the MSK modulated signal by the multiplier 24 is used in this embodiment will be described with reference to FIG. Comparing the MSK modulated signal shown in FIG. 5 (C) with the 40.96 MHz signal shown in FIG. 5 (D), when the first digital signal is “0”, the MSK modulated signal and the 40.96 MHz signal are When the phases are the same, but the second digital signal is "0", MSK
The modulation signal and the signal of 40.96 MHz have opposite phases. Therefore, VCO 36 to 40.96 MHz
When a single frequency signal of
Even if the SK modulated signal is compared with the 40.96 MHz signal, the signals cancel each other out when the second digital signal is "0", and the comparator 38 cannot accurately compare the phases. Thus, if the MSK modulated signal is directly applied to the first PLL circuit 34 without using the multiplier 24, the PLL operation cannot be performed quickly and accurately. Even when the VCO 36 outputs the 61.44 MHz signal, the same phenomenon occurs between the MSK modulated signal and the 61.44 MHz signal.

On the other hand, the MSK modulation signal is multiplied by the multiplier 2
The multiplied output obtained by multiplying by 2 in 4 is given to the first PLL circuit 34,
81.92M which is double of 40.96MHz from VCO 36
If a signal of Hz is output, the phases are always in agreement at the portion where the digital signal becomes "0" (FIGS. 5F and 5G). Therefore, in this case, the comparator 38 can accurately compare the phases of the multiplied output and the output from the VCO 36, and the PLL operation of the first PLL circuit 34 becomes quick and accurate. The VCO 36 to 122.88 MH
Even when a signal of z (twice of 61.44 MHz) is output, the same applies between this signal and the multiplied output (FIGS. 5F and 5H). Therefore, the MSK modulated signal is multiplied by the multiplier 24, and the signal is also output from the VCO 36 accordingly. In this embodiment, the case where the frequency is multiplied by 2 by the multiplier 24 is described, but the present invention is not limited to this, and any integer multiple of 2 or more may be used. Along with that, VC
It goes without saying that the signal from O36 is also changed appropriately.

The operation of the first PLL circuit 34 will be described with reference to FIG. It should be noted that here, 12 from the VCO 36
It is assumed that a 2.88 MHz signal is output. The comparator 38 outputs the multiplied output shown in FIG.
When the 122.88 MHz signal (correct phase) from the VCO 36 shown in (B) is output, the output of the comparator 38 becomes an output as shown by the solid line in FIG.
A control signal as indicated by a broken line in FIG. 6C is output from 0.

Also, from the VCO 36 to 122.88 MHz
6D has a lead phase as shown in FIG. 6D, the comparator 38 gives the output shown by the solid line in FIG. 6E to the LPF 40, and the LPF 40 gives the control signal shown by the broken line in FIG. 6E. Is output. Furthermore, the signal from the VCO 36 is shown in FIG.
If the delay phase is as shown in FIG.
The output shown by the solid line in (G) is applied to the LPF 40, and L
The PF 40 outputs the control signal indicated by the broken line in FIG.

In this way, the VCO 36 has the multiplier 24
To output a signal of a single frequency f _VCO synchronized with the bright line frequency component from. Therefore, the multiplied output from the multiplier 24 is 102.4 MHz (81.9 MHz and 1
(Including 22.88 MHz) + 2Δ, VCO3
6 outputs a signal of 122.88 MHz + 2Δ. Next, the operation of the second PLL circuit 42 will be described with reference to FIG. The output from the VCO 36 is frequency-divided by the frequency divider 44 into M (for example, 10) and applied to the comparator 48.
Accordingly, the oscillation frequency fp of the reference oscillator 46 is calculated by
It is set as shown in. The oscillation frequency fp is (122.88 / M) MHz, for example.

Then, the comparator 48 compares the phase of the output from the frequency divider 44 and the phase of the output from the reference oscillator 46, and as shown in FIG. 7B, the phase of the output from the frequency divider 44. Is correct, the output from the comparator 48 is given to the LPF 50 as shown by the solid line in FIG. 7 (C). LPF
From 50, the control signal as shown by the broken line in FIG.
The center frequency from the VCO 14 is supplied to the CO 14 and is controlled.

Further, as shown in FIG.
7E is in the advanced phase, the output from the comparator 48 is as shown by the solid line in FIG. 7E, and accordingly, from the LPF 50 is shown by the broken line in FIG. 7E (overlapped with the solid line). Such control signals are provided to the VCO 14. Further, if the output from the frequency divider 44 has a delay phase as shown in FIG. 7 (F), the output from the comparator 48 will be as shown by the solid line in FIG. 7 (C), and the output from the LPF 50 will be as shown in FIG. The control signal as shown by the broken line (overlapping the solid line) in (G) is VCO14.
Given to.

That is, the LPF 50 according to Δ (deviation)
Outputs a control signal that cancels the deviation, and MSK
Even if the frequency of the modulation signal is 51.2 MHz + Δ, it is controlled to be 51.2 MHz. Therefore,
The center frequency of the MSK modulated signal can be controlled to be constant. It should be noted that, in the above embodiment, the VCO 36 to 122.88M
I have described the case where a Hz signal is output.
The same applies when a 1.92 MHz signal is output. In this case, from the multiplier 24 to 102.4 MHz + 2Δ
If the signal of is output, VCO 36 is 81.92MHz
The signal of + 2Δ is output, and the output of the reference oscillator 46 is (81.92 / M) MHz.

Here, in the MSK modulator 10 shown in FIG. 1, the output frequency from the VCO 14 is set by the equation 2, but the variable width of the variable capacitance diode C3 is limited to a narrow range. That is, the capacitance of the variable capacitance diode C3 is controlled only by whether the digital signal from the input terminal 16 is at high level or low level, and is only finely adjusted by the control signal from the LPF 50. Absent. Therefore, the output terminals 20 to 4
Even if an MSK modulated signal of 0.96 MHz and 61.44 MHz is to be obtained, the ratio band is large with respect to the center frequency because the variation width of the variable capacitance diode C3 is limited.
Two MSKs at 0.96MHz and 61.44MHz
There were times when I couldn't get a modulated signal. These two MSKs
An MSK modulator 60 from which a modulated signal can be easily obtained is shown in FIG.

In the MSK modulator 60 shown in FIG. 8, the value of (1 / L) in equation 2 is increased by reducing the inductance of the inductor L shown in FIG. Since the center frequency of the VCO 14 is increased in this way, the change width of the output frequency ω can be increased even if the change width of the capacitance of the variable capacitance diode C3 is small, and the difference between the two frequencies can be set to a desired value (here, , 61.44-40.96 = 2
0.48 MHz). At this time, the output frequency ω itself also becomes higher than the desired frequency, but frequency conversion is performed as follows to obtain a predetermined frequency.

The MSK modulator 60 of FIG. 8 has a VCO 62 that operates as an oscillator for frequency conversion and a mixer 64 that mixes the outputs of the VCOs 14 and 62 and frequency-converts them to a predetermined frequency. The MSK modulator 10 of FIG. The VCO 14 of the MSK modulator 60 is also shown in FIG.
However, it should be noted that the control signal from the control terminal 18 is a constant voltage and the inductance of the inductor L is set smaller than that in the case of FIG.
Other configurations are the same as those of the embodiment of FIG. 1, and thus duplicated description will be omitted.

In the operation, description will be made assuming that when a digital signal is input from the input terminal 12, the VCO 14 gives a signal of, for example, the center frequency f + 51.2 MHz + Δ (deviation) to the mixer 64. The mixer 64 is
For example, it is configured by EX-OR and performs frequency conversion based on the oscillation frequency from VCO 62. If the oscillation frequency from the VCO 62 is f, the mixer 64 outputs an MSK modulation signal having a frequency of 51.2 MHz + Δ by frequency conversion, but the LPF 50 cancels Δ (deviation) according to Δ (deviation). Output a signal. Then VC
Since the oscillation frequency of O62 is f + Δ, the output from the mixer 64 is controlled to be 51.2 MHz + Δ to 51.2 MHz. The operations of the multiplier 24, the first PLL circuit 34, and the second PLL circuit 42 are the same as those in the embodiment of FIG.

According to the embodiment shown in FIG. 8, since the output from the VCO 14 is frequency-converted by the mixer 64, the inductor L (FIG. 2) of the VCO 14 is made small so that the VCO 14 has a small size.
Even if the output frequency ω from 14 is increased, a desired MSK modulation signal having two different frequencies can be easily obtained without any problem. Furthermore, FIGS. 9 and 10 show GMSK modulators 70 and 80 according to another embodiment. In each of the GMSK modulators 70 and 80, a Gaussian type LPF 72 is inserted in front of the VCO 14.

The LPF 72, as shown in FIG.
The input digital signal is converted into a sine wave, and VC
Give to O14. In this way, the band of the digital signal is limited by the filter having the Gaussian characteristic. Then, the transmission power spectrum can be controlled by changing the bandwidth of the LPF 72, and the band of the modulation spectrum can be further narrowed as compared with the embodiments shown in FIGS. 1 and 8. The GMSK modulator 7 of FIG.
0 corresponds to the MSK modulator 10 shown in FIG. 1, and the GMSK modulator 80 shown in FIG. 10 is the MSK modulator 6 shown in FIG.
Corresponds to 0. Other configurations and effects are the same as those of the embodiment shown in FIGS. 1 and 8, and thus duplicated description will be omitted.

It should be noted that in the above-described embodiment, the present invention is applied to the MS.
The case where the present invention is applied to the K modulator and the GMSK modulator has been described, but the present invention can also be applied to other modulators such as a modulator for TFM (Tamed FM).

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a VCO 14.

FIG. 3 is a circuit diagram showing an example of a multiplier.

FIG. 4 is a waveform diagram showing the operation of the multiplier.

FIG. 5 is a waveform diagram showing the main outputs of this embodiment.

FIG. 6 is a timing diagram showing an output of the first PLL circuit.

FIG. 7 is a timing diagram showing an output of the second PLL circuit.

FIG. 8 is a block diagram showing another embodiment of the present invention.

FIG. 9 is a block diagram showing another embodiment of the present invention.

FIG. 10 is a block diagram showing another embodiment of the present invention.

FIG. 11 is a block diagram showing a conventional MSK modulator.

FIG. 12 is a block diagram showing a conventional GMSK modulator.

FIG. 13 is a block diagram showing a conventional MSK / GMSK modulator.

FIG. 14 is a block diagram showing a conventional MSK modulator.

[Explanation of symbols]

 10, 60 ... MSK modulator 14, 36, 62 ... VCO 24 ... Multiplier 34 ... First PLL circuit 42 ... Second PLL circuit 64 ... Mixer 70, 80 ... GMSK modulator L, L1 ... Inductor C3 ... Variable capacitance diode

Front page continuation (72) Inventor Hisakazu Kato 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Technology Laboratory

Claims (6)

[Claims] 1. An FM modulating means for modulating a digital signal to obtain a modulated signal, a multiplying means for multiplying the modulated signal from the FM modulating means, and a mark or space of the digital signal based on an output of the multiplying means. First PLL means for outputting a signal having a frequency equal to the corresponding bright line frequency component, and the FM so that the center frequency of the modulated signal becomes a predetermined frequency based on the signal output from the first PLL means.
A modulator comprising second PLL means for outputting a control signal for controlling the oscillation frequency of the modulating means. 2. FM modulating means for modulating a digital signal to obtain a modulated signal, voltage controlled oscillating means for converting the modulated signal from the FM modulating means into a predetermined frequency, and the modulating from the FM modulating means. Mixing means for mixing a signal and the output from the voltage controlled oscillating means to obtain a modulated signal of a predetermined frequency by frequency conversion, multiplying means for multiplying the modulated signal from the mixing means, based on the output of the multiplying means First PLL means for outputting a signal having a frequency equal to the bright line frequency component corresponding to the mark or space of the digital signal, and the center frequency of the modulated signal becomes a predetermined frequency based on the signal outputted from the first PLL means. A modulator comprising second PLL means for outputting a control signal for controlling the oscillation frequency of the voltage controlled oscillation means. 3. The first PLL means includes first voltage controlled oscillation means for outputting a signal of a single frequency, comparison means for comparing the output of the multiplication means with the output of the first voltage controlled oscillation means, and the comparison. A low-pass filter that outputs a control signal for controlling the frequency of the signal from the first voltage-controlled oscillating means to be equal to the bright line frequency component corresponding to the mark signal or space signal of the digital signal based on the output of the means. Claim 1 including
Or the modulator according to 2. 4. The second PLL means includes reference oscillation means, frequency division means for dividing the output of the first PLL means, comparison means for comparing the output of the reference oscillation means with the output of the frequency division means, and The modulator according to claim 1, further comprising a low-pass filter that applies a control signal based on the output of the comparison means to the FM variation means to control an oscillation frequency of the FM variation means. 5. The second PLL means includes reference oscillation means, frequency division means for dividing the output of the first PLL means, comparison means for comparing the output of the reference oscillation means with the output of the frequency division means, and The modulator according to claim 2, further comprising a low-pass filter that controls the oscillation frequency of the voltage-controlled oscillation means by applying a control signal based on the output of the comparison means to the voltage-controlled oscillation means. 6. The modulator is an MSK modulator or a GMS.
The modulator according to any one of claims 1 to 5, which is a K modulator.