JP2780529B2 - FSK modulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FSK modulator used for digital data communication, and more particularly to an FSK modulator for transmitting high-speed data with high frequency accuracy.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional FSK modulator.
The output of the voltage controlled oscillator (VCO) 41 of 20MH _Z band is input to the variable frequency divider 42. Variable frequency divider 42, and 418 divided on the basis of the data inputted signals inputted 20MH _Z bands to the data input terminal 2 (space) or 382 divided (mark), the signal 50KH _Z band . Phase comparator 4
3 compares the phase of the reference signal 50KH _Z from the output signal and the reference signal generator 1 of the variable frequency divider 42, VCO 4
1 to control the output frequency of the variable frequency divider 42 to match the frequency of the reference signal. A low-pass filter 44 is provided between the VCO 41 and the phase comparator 43 to remove unnecessary components. In this configuration, the VC when the data is a mark
Oscillation frequency of O41, the oscillation frequency of the VCO41 when the 50KH _Z × 382 = 19.1MH _Z, and the data space becomes 50KH _Z × 418 = 20.9MH _Z. Also, VCO41
Is divided by 200 by the frequency divider 45, and the low-pass filter 4
Since output from the output terminal 3 after removal of the high frequency through 6 can be obtained FSK signal 100KH _Z ± 4.5KH _Z.

FIG. 3 shows another conventional FSK modulator. Data input from the data input terminal 2 is passed through a limiter amplifier 52 in order to prevent line level fluctuation. Then, after a bias is applied by the DC power supply 53 and the adder 54, the band is limited by the low-pass filter 55 and applied to the VCO 51. VCO 51 is 1
And oscillates a 00KH _Z band, here 100KH _Z ± 4.5K
FSK modulation of H _Z is applied. After the high frequency is removed by the low-pass filter 56, the output of the VCO 51
Output from

[0004]

In the FSK modulator shown in FIG. 2, the low-pass filter 44 generally employs a primary filter composed of a CR primary integration circuit. With a filter having such a configuration, high-frequency attenuation is not sufficient, and an unnecessary signal appears at the output of the VCO 41 when the cutoff frequency of the filter is increased in order to speed up the response of the loop. Conversely, if the response of the loop is slowed down, phenomena, such as intersymbol interference, which hinder high-speed data communication will appear. On the other hand, when a high-order filter is used for the low-pass filter, phenomena such as loop oscillation and overshoot are likely to occur due to the delay of the filter. In addition, there is a problem that a jitter corresponding to the period of the phase comparison frequency is involved.

In the FSK modulator shown in FIG. 3, a high-order Bessel filter suitable for high-speed data communication can be used as the low-pass filter 55 for band limitation. However, the output frequency depends on the characteristics of the VCO 51 alone, and there is a problem that the output frequency and the frequency shift tend to fluctuate due to the temperature characteristics of the VCO itself. An object of the present invention is to provide an FSK modulator suitable for high-speed data communication by increasing frequency stability and reducing intersymbol interference.

[0006]

An FSK modulator according to the present invention includes a first voltage-controlled oscillator, a first PLL circuit controlled to one frequency, and a second voltage-controlled oscillator. a second PLL circuit to be controlled to the frequency of the modulation
Select the control voltage of the first or the second voltage controlled oscillator in accordance with the signal, the control voltage to the modulated the selected voltage
A third circuit including a third voltage controlled oscillator for outputting a signal is configured, and the first to third voltage controlled oscillators are each configured by a circuit having the same configuration .

[0007]

According to the present invention, FSK modulation is enabled by switching the control voltage of the first PLL circuit and the control voltage of the second PLL circuit to control the oscillation output frequency of the third circuit. .

[0008]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
First VCO 11, first frequency divider 12, first phase comparator 1
3. The first PLL circuit 10 is configured by the first low-pass filter 14. Wherein the 1VCO11 at least 19MH _Z ~
It can be oscillated in a range of 21MH _Z, the first 1VCO
An output of 11 which is the first frequency divider 12 with the 418 divided 50KH _Z bands, are phase compared with the reference signal 50KH _Z from the reference signal generator 1 in the first phase comparator 13. After passing through the first low-pass filter 14, the phase error voltage becomes the first VC
O11 control voltage, the first VCO 11 is always 20.9M
It is controlled so as to oscillate the H _Z. At this time, the cut-off frequency of the first low-pass filter 14 can be made sufficiently low because the oscillation frequency of the first VCO 11 is always constant.
It is possible to reduce the leakage of the phase comparison frequency of 50KH _Z in the control voltage.

Similarly, a second VCO 21, a second frequency divider 22,
The second phase comparator 23 and the second low-pass filter 24
The L circuit 20 is constituted. However, the second frequency divider 22 is 3
In order to divide the frequency by 82, the oscillation frequency of the second VCO 21 is 19.1
MH _Z.

Further, a third VCO 31 is provided, and an output is taken out by a third frequency divider 32 and a third filter 33. A Vessel-type low-pass filter 34 is connected in front of the third VCO 31, and an analog switch 3 is further in front of the third VCO 31.
5 to form the third circuit 30. Then, based on the data from the data input terminal 2, the control voltage of the third VCO 31 is changed to the control voltage of the first VCO 11 or the second VCO 2
The control voltage is switched to 1. This makes it possible to change the control voltage of the third VCO 31 according to the data, and to apply FSK modulation to the third VCO 31.
The Bessel type low-pass filter 34 has a DC gain of 1,
Perform band limiting. The output of the third VCO 31 is 20 MHz _Z ± 9
A 00KH _Z, which signals 100KH _Z ± 4.5KH _Z by 200 divided by the third frequency divider 32 is obtained, after removing the high frequency like this in the third low-pass filter 33, Output from output terminal 3.

Here, consider the case where the surrounding environment changes. Since the first VCO 11 is controlled by the first PLL circuit 10, it always oscillates at a constant frequency.
At this time, the control voltage of the first VCO 11 is the first VCO 1
1 is compensated for by the change in the characteristic (1). 2nd VCO
21 is also the same. The third VCO 31 includes first and second VCs.
Because it is configured by the same circuit as O11 and 21,
The change of the characteristic of the third VCO 31 with respect to the change of the environment is the first.
And the characteristics of the second VCOs 11 and 21 are substantially the same. Therefore, it is possible to keep the oscillation frequency of the third VCO 31 highly stable.

[0012] Thus, with three of the VCO consists of the same circuit configuration, the first PLL the first 1VCO11 always so as to oscillate at 20.9MH _Z (frequency space)
Controlled by circuit 10, the first 2VCO21 always controlled by the second PLL circuit 20 so as to oscillate at 19.1MH _Z (frequency of the mark), these first 1VCO11 and second 2VCO2
1 by switching the control voltage based on the data and applying the control voltage to the third VCO 31 through the Bessel type low-pass filter 34 to generate a signal with good frequency stability and low intersymbol interference suitable for high-speed data communication It is possible to configure an FSK modulator that performs

[0013]

As described above, the present invention provides a modulated signal
A control voltage of the first PLL circuit according to the data
Switching and selecting the control voltage of the second PLL circuit ,
Since along with obtaining the structure to the modulated signal to output an oscillation signal as the control voltage of the third circuit, constitute a VCO provided in each circuit in the circuit of the same configuration, good frequency stability, An FSK modulated signal with little intersymbol interference suitable for high-speed data communication can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of a conventional FSK modulator.

FIG. 3 is a block diagram of another example of the conventional FSK modulator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st PLL circuit 20 2nd PLL circuit 30 3rd circuit 11 1st VCO 21 2nd VCO 31 3rd VCO 34 Bessel type low-pass filter 35 Analog switch

Claims (2)

(57) [Claims] 1. A first PLL circuit controlled to one frequency including a first voltage controlled oscillator, and a first PLL circuit controlled to another frequency different from the one frequency including a second voltage controlled oscillator. A second PLL circuit, and a control voltage of the first or second voltage-controlled oscillator according to the modulation signal , the selected voltage as a control voltage , and an output of the selected voltage as a control signal.
And a third circuit including a third voltage-controlled oscillator that is output as a signal. The first to third voltage-controlled oscillators are each configured by a circuit having the same configuration . . Wherein said first PLL circuit includes a reference signal oscillator for outputting a reference signal of 50KH _Z, a first voltage controlled oscillator for oscillating a 20MH _Z bands, an output of said first voltage controlled oscillator a first frequency divider for 418 minutes division, a first phase comparator for outputting an error voltage by comparing the phase of the output and the reference signal of the first frequency divider, the first phase comparator removes unnecessary components from the output of, is composed of a low-pass filter for controlling said first voltage controlled oscillator output signal, before
Serial second PLL circuit, the said first voltage controlled oscillator
A second voltage controlled oscillator that generates a composed 20MH _Z zone in the circuit of one configuration, the output of the second voltage controlled oscillator
Comparing a second frequency divider for 382 divide the phase of the output and reference signals of the second frequency divider, a second outputting an error voltage
A phase comparator, removes unnecessary components from the output of the second phase comparator, is composed of a second low-pass filter for controlling said second voltage controlled oscillator output signal, It said third circuit receives said first control voltage applied to the voltage controlled oscillator and control voltage applied to the second voltage controlled oscillator, select one based on the data as a modulation signal an analog switch, a Bessel filter for band-limiting an output of said analog switch, the oscillation frequency by the output of the Bessel filter is controlled, 20 composed of a circuit of the first voltage controlled oscillator and the same configuration
A third voltage controlled oscillator that oscillates MH _Z bands, the third
A voltage controlled oscillator frequency divider for division 200 minutes the output of, claim 1, characterized in that it comprises a low-pass filter for removing high frequency and the like from the output of the <br/> divider of the FSK modulator.