JPH07321369A - Semiconductor photodetector and its manufacture and method and device for forming film - Google Patents

Abstract

PURPOSE:To provide a semiconductor photodetector in which the characteristic is not deteriorated and a means for easily growing a cover film with desired patterns. CONSTITUTION:The surface of a crystalline semiconductor layer (a low dissociation pressure semiconductor layer) 2 in which the dissociation pressure of a constituent element which is a substrate 1 or deposited on the substrate 1 is low is processed so that the projecting part of a column. wall or grid form is formed, and a crystalline semiconductor layer (a high dissociation pressure semiconductor layer) 3 in which the dissociation pressure of a constituent element is high is formed so as to fill a recessed part between the projecting parts, and the low dissociation pressure semiconductor layer 2 is removed in a groove, hole or grid form thereby separating the high dissociation pressure semiconductor layer 3 at least in part to form a photo detection element of the high dissociation pressure semiconductor layer 3. A substrate mounting base with a thick part of patterns of a cover film to be grown is interposed between a substrate heating base for heating a substrate for growing a cover film and the substrate for growing a cover film thereby forming a high-temperature region of a pattern form to grow a cover film. Also, the thick part can be provided in the substrate for growing a cover film.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photodetector, and more particularly to an infrared detector, a method of manufacturing the same, a film forming method and a film forming apparatus.

[0002]

2. Description of the Related Art Conventionally, an infrared detecting device has an infrared detecting element substrate for receiving infrared rays and performing photoelectric conversion, and a signal processing circuit substrate for forming an electric signal processing CCD circuit or a MOS switch circuit, which is attached via electrodes. The combined structure is adopted, and CdZnTe is used for the infrared detection element substrate.
A substrate in which an HgCdTe layer is grown is used, and Si is used for the signal processing circuit substrate.

However, infrared detectors are usually -190 ° C.
Since it is used after being cooled to a certain degree, the problem of peeling of the coupling electrode is likely to occur due to the difference in thermal expansion coefficient between the infrared detection element substrate and the signal processing circuit board. Has become noticeable.

Therefore, in order to match the thermal expansion coefficients of the infrared detection element substrate and the signal processing circuit board, it is necessary to change the infrared detection element substrate to one in which a thin HgCdTe layer is grown on a Si substrate, or It is necessary to grow an HgCdTe layer on the processing circuit board to form an infrared detection element, and to form an infrared detection device having a structure (monolithic type) in which the signal processing circuit board and the infrared detection element are integrated.

However, HgCdT is formed on the Si substrate.
When the e-layer is grown to form the sensing element, no problem occurs in the coupling electrode, but the Si substrate and H
Since the coefficient of thermal expansion of the gCdTe layer is different, strain is added,
There is a problem that the HgCdTe layer is cracked or peeled off.

In order to prevent this, HgC
Forming groove-shaped, hole-shaped, or lattice-shaped recesses around the infrared detection element formed in the dTe layer to at least partially separate each infrared detection element and reduce strain applied to each infrared detection element. is necessary.

FIG. 8 is an explanatory view of manufacturing steps of a conventional infrared detecting device, and FIGS. 8 (A) to 8 (C) show respective steps.
In this figure, 41 is a Si substrate, 42 is a CdTe buffer layer, 43 is a HgCdTe layer, 43 ₁ is a defect layer, 44
Is an n-HgCdTe layer, and 45 is a groove. A conventional infrared detection device and a method of manufacturing the same will be described as an example of a semiconductor light detection device with reference to the manufacturing process explanatory diagram.

First Step (See FIG. 8A) A CdTe buffer layer 42 is grown on a Si substrate 41, an HgCdTe layer 43 is grown on the CdTe buffer layer 42, and the HgCdTe layer 43 is heat-treated. (P-type processing) is added.

By this heat treatment, the HgCdTe layer 43 is formed.
Hg having a large dissociation pressure is partially dissociated among the elements constituting the, and a large number of vacancies (point defects) formed by the dissociation of Hg supply positive charges (holes) in the HgCdTe layer 43. P-type HgC to act as (acceptor)
A dTe layer 43 is obtained. In order to obtain the Hg vacancy concentration capable of forming the infrared detection device, it is necessary to apply heat treatment at about 300 ° C. By this heat treatment, HgC
Since the defect layer 43 ₁ containing defects is formed on the surface of the dTe layer 43, it is necessary to remove this defect layer 43 ₁ by polishing, etching or the like.

Second step (see FIG. 8B) A mask having an opening is formed on the surface from which the defect layer 43 ₁ is removed, and n-type impurities such as B are ion-implanted using this mask to selectively An n-type HgCdTe layer 44 is formed on
A pn junction for forming an infrared sensing element is formed.

Third step (see FIG. 8C) Grooves 45 are formed by dry etching (RIE) in the region surrounding the selectively formed n-type HgCdTe layer 44 to form individual infrared detecting elements. .

When forming the groove 45 in the third step,
When the wet etching method is used with an etching solution, the etching proceeds isotropically. Therefore, when the deep groove 45 is formed, the width of the groove 45 is also widened and the distance between the adjacent infrared detecting elements is increased. Therefore, the dry etching method that allows anisotropic etching is used.

When the p-type HgCdTe layer 43 is formed by heat treatment after forming the isolation structure by the groove 45 and then the surface defect layer 43 ₁ is removed, the defect layer 43 ₁ formed on the side surface of the groove 45 is removed. Will also be removed, and the width of the groove 45 will be widened, and the same problem as in the case of forming the groove 45 by using the wet etching method will occur. Therefore, heat treatment is performed to remove the defect layer 43 ₁ . After that, the procedure of forming the separation structure is adopted.

[0014]

When the isolation structure is formed between the semiconductor photodetectors by the dry etching method as described above, the high-energy particles used for the dry etching form the trenches forming the isolation structure of the p-type HgCdTe layer 43. Damage the sides and tips.

Due to this damage, p-type HgCd
There occurs a phenomenon that impurities near the surface of the Te layer 43, Hg, etc. knocked out between crystal lattices diffuse, or defects are introduced, and this diffusion and the phenomenon of introducing defects is promoted through Hg vacancies. Therefore, p-type HgC that has Hg vacancies
The dTe layer 43 has a problem that a damaged layer expands.

Therefore, when the isolation structure is formed by the above-mentioned conventional technique, the damaged layer extends to the pn junction and the performance of the infrared detecting element is deteriorated. In order to avoid this problem, an impurity (donor or acceptor) serving as a supply source of carriers that are electrons or holes is added to the p-type HgCdTe layer 43 in advance, and the p-type or n-type is used without using Hg vacancies. There is a method of obtaining a mold layer and forming an infrared detection element.

In this case, Hg holes are formed to form p-type Hg.
Although the heat treatment (p-type treatment) for obtaining the CdTe layer 43 is not necessary, after the growth of the p-type HgCdTe layer 43, the heat treatment for filling the Hg vacancies generated at this growth temperature (200 to 400 ° C.) (n-type treatment, temperature). 250 ° C), so
Although only the amount of the equilibrium dissociation pressure at this temperature reduces the concentration of Hg vacancies, there is a problem that when the p-type HgCdTe layer 43 is dry-etched, the influence of the damaged layer on the infrared detection element cannot be sufficiently reduced. It was An object of the present invention is to provide a semiconductor photodetector capable of reducing characteristic deterioration, particularly an infrared detector, a method for manufacturing the same, a film forming method for easily forming a film having a desired pattern, and a film forming apparatus therefor. .

[0018]

In a semiconductor photodetector according to the present invention, a substrate and a semiconductor crystal layer having different thermal expansion coefficients from each other and having a high dissociation pressure of a constituent element, the dissociation of the constituent element are included. The semiconductor crystal layer having a high pressure is at least partially divided by groove-shaped, hole-shaped, or lattice-shaped recesses to form a photodetecting element, and the side surface of the recess dividing the photodetecting element has a dissociation pressure of constituent elements. And a semiconductor crystal layer having a low lattice constant and a semiconductor crystal layer having a similar lattice constant is adopted.

In this case, the substrate is made of Si, GaAs or A.
The semiconductor crystal layer formed of 1 ₂ O ₃ and having a high dissociation pressure of the constituent elements forming the photodetector is formed by Hg _1-x Cd _x Te
The semiconductor crystal layer formed of (x <0.3) and having a low dissociation pressure of constituent elements and covering the side surface of the recess dividing the photodetector is CdTe, CdZnTe, or Hg _1-x Cd _x Te.
(X> 0.4).

Further, in this case, the light detecting element is formed by a pn junction of a semiconductor crystal layer having a high dissociation pressure of constituent elements,
The p-type region or the n-type region forming the pn junction can be formed by a semiconductor layer in which carriers which are electrons or holes are generated by holes generated by dissociating the constituent elements from the semiconductor crystal layer.

Further, in this case, the light detecting element is formed by a pn junction of a semiconductor crystal layer having a high dissociation pressure of constituent elements,
The p-type region or the n-type region forming the pn matching can be formed by a semiconductor layer which generates carriers which are electrons or holes by introducing different kinds of impurities.

Further, in these cases, it is possible to adopt a structure in which the p-type region and the n-type region are exposed on the upper surface of the photodetecting element.

Further, in the method for manufacturing the photodetector according to the present invention, the surface of the substrate or the semiconductor crystal layer having a low dissociation pressure of the constituent elements deposited on the substrate has columnar, fence-shaped or lattice-shaped convex portions. A step of processing so as to form, a step of forming a semiconductor crystal layer having a high dissociation pressure of constituent elements so as to fill the concave portions formed between the convex portions, and the substrate or the substrate. By selectively removing the semiconductor crystal layer having a low dissociation pressure of the constituent element into a groove shape, a hole shape, or a lattice shape, the semiconductor crystal layer having a high dissociation pressure of the constituent element is at least partially separated, The step of forming a photodetection element with a semiconductor crystal layer having a high dissociation pressure of elements is adopted.

In this case, as a method for selectively removing the substrate or the semiconductor crystal layer having a low dissociation pressure of the constituent elements deposited on the substrate into a groove shape, a hole shape, or a lattice shape, high energy such as ions or plasma is used. A dry etching method using particles can be used so that a region to be dry-etched does not reach a semiconductor crystal layer in which a dissociation pressure of a constituent element forming a photodetector element is high.

Further, in the film forming method according to the present invention, the thick portion of the film pattern to be grown on the film growth substrate is provided between the substrate heating table for heating the film growth substrate and the film growth substrate. The substrate growth table with the thick part in contact with the substrate for film growth, or vice versa, the thick film part in contact with the substrate heating table. The process of growing a film on the substrate for use was adopted.

In another film forming method according to the present invention, a film growth substrate having a thick part of a film pattern to be grown is formed on a substrate heating table for heating the film growth substrate. The step of growing a film on the film-growth substrate with the part placed in contact with the substrate heating table was adopted.

Further, in the film forming apparatus according to the present invention, the substrate mounting table having the thick portion of the film pattern to be grown is placed on the substrate heating table for heating the film growth substrate. Adopted.

[0028]

1A to 1C are views for explaining the manufacturing process of the photodetector of the present invention, and FIGS. 1A to 1C show each process. In this figure, 1 is a Si substrate, 2 is a CdTe buffer layer, 2
₁ is a recess, 2 ₂ is a groove, 3 is a p-type HgCdTe layer, 4 is n
It is a type HgCdTe layer.

A method of manufacturing an infrared detecting device using an HgCdTe layer grown on a Si substrate and a configuration of the infrared detecting device manufactured as a result will be described with reference to the manufacturing process explanatory diagrams.

First step (see FIG. 1A) The CdTe buffer layer 2 is formed on the Si substrate 1, and the region of the CdTe buffer layer 2 where the infrared detecting element is to be formed is formed on the CdTe buffer layer 2. leaving part forming a recess 2 ₁ is removed by etching.

[0031] The second step (FIG. 1 (B) refer) p-type HgCd to fill the recess 2 ₁ formed in the preceding step
After growing the Te layer 3, the upper portion of the p-type HgCdTe layer 3 is removed so that the p-type HgCdTe layer 3 is surrounded by the CdTe buffer layer 2.

Third step (see FIG. 1C) A mask having an opening is formed on the upper surface of each p-type HgCdTe layer 3 isolated in the previous step, and B is formed using this mask.
N-type impurities such as n-type HgCd are selectively implanted by ion implantation.
The Te layer 4 is formed to form a pn junction of the infrared detection element. Then, although the n-type HgCdTe layer 4 around the region for forming the infrared detection element is etched to form the grooves 2 ₂ separating individual infrared detector element, in this case, around the p-type HgCdTe layer 3 Etching is performed so that the CdTe buffer layer 2 partially remains, and etching is performed using p-type HgCd.
Do not reach the Te layer 3. Therefore, after the etching, the infrared detecting elements are separated by the grid-shaped grooves 2 ₂ to form the infrared detecting elements of the p-type HgCdT.
The side surface of the e layer 3 is covered with the CdTe buffer layer.

The CdTe buffer layer 2 is a p-type HgCdT.
The dissociation pressure of constituent elements such as Hg forming the e layer 3 is not high, and the lattice constant of the CdTe buffer layer 2 and the p-type HgCd
Since the Te layer 3 has substantially the same lattice constant, no strain occurs between the two layers. Therefore, even if the CdTe buffer layer 2 is dry-etched, the holes do not promote diffusion or defect introduction. Therefore, the damage caused by dry etching does not spread to the p-type HgCdTe layer 3, and the problem that the performance of the infrared detection element formed on the p-type HgCdTe layer 3 deteriorates can be solved.

[0034]

EXAMPLES Examples of the present invention will be described below. (First Embodiment) FIG. 2 is a drawing explaining the manufacturing process of the infrared detector of the first embodiment, and (A) to (D) show each process.

In this figure, 1 is a Si substrate, 2 is Cd
Te buffer layer, 2 ₁ is a recess, 2 ₂ is a groove, 3 is p-type Hg
A CdTe layer, 4 is an n-type HgCdTe layer, 5 is a ZnS protective film, and 6 ₁ and 6 ₂ are metal wirings.

A method of manufacturing the infrared detecting device according to the first embodiment and the structure of the infrared detecting element manufactured as a result will be described with reference to the manufacturing process explanatory drawings.

First Step (See FIG. 2A) A CdTe buffer layer 2 having a thickness of 15 μm is formed on the Si substrate 1.
Forming a photolithography technique region where to form the infrared sensing element of the CdTe buffer layer 2 leaving a part of the CdTe buffer layer 2, to form a recess 2 ₁ is selectively etched and removed. As for this etching, since the width is wider than the depth of the concave portion, wet etching or dry etching may be adopted. In addition, instead of the Si substrate 1 described above, a GaAs substrate,
An AlO substrate or the like can be used, and a CdZnTe buffer layer or the like can be used instead of the CdTe buffer layer 2.

The second step thick 15μm to fill (see FIG. 2 (B) refer) recess 2 ₁ formed in the preceding step
After growing the HgCdTe layer of, heat treatment (p-type treatment)
Hg vacancies are formed by means of p-type HgCdT
The e-layer 3 is formed.

Third step (see FIG. 2C) p-type HgCdT produced by heat treatment in the second step
In order to remove the defect layer near the surface of the e layer 3, the p-type HgCdTe layer 3 is removed by polishing or wet etching to about 4 μm. At this time, the p-type HgCdTe layer 3 is removed until the convex portion of the CdTe buffer layer 2 appears on the surface so that the p-type HgCdTe layer 3 is surrounded by the CdTe buffer layer 2.

A mask is formed on a part of the surface of the p-type HgCdTe layer 3 remaining after that by using a photolithography technique, and boron (B) is ion-implanted through the mask to change this part to an n-type. n-type HgCdTe layer 4
To form. As a result, the p-type HgCdTe layer 3 has p
This means that a plurality of infrared detecting element regions are formed by n-junction.

Next, a photolithography technique is used on the p-type HgCdTe layer 3 to form a mask (resist, metal) having openings around a plurality of infrared detection element regions by pn junction, and the surface is formed through the openings. The CdTe buffer layer 2 shown in FIG. 2 is etched to separate each infrared detecting element. This etching has a width since the depth of about 3μm to form a lattice-shaped grooves 2 ₂ of about 15 [mu] m, it is necessary to apply the anisotropic dry etching.

[0042] In this example, 2 [mu] m approximately Cd between the grooves 2 ₂ and p-type HgCdTe layer 3 is etched
Since the Te buffer layer 2 is present, direct damage due to dry etching does not reach the p-type HgCdTe layer 3.
Further, the CdTe buffer layer 2 is the p-type HgCdTe layer 3
Since the dissociation pressure of the constituent elements is not so high as Hg constituting H.sub.g, even if the CdTe buffer layer 2 is dry-etched, the holes do not promote diffusion or defect introduction.

Therefore, the p-type HgCdTe layer 3 is not damaged by dry etching, and the p-type HgCdTe layer 3 is not damaged.
It is possible to solve the problem that the performance of the infrared detection element formed on the gCdTe layer 3 is deteriorated. Further, the CdTe buffer layer 2 covers the side surface of the infrared detection element and also serves as a surface protective film.

Fourth step (see FIG. 2D) A ZnS protective film 5 is formed on the surface of the infrared detecting element, an opening is formed in a portion where an electrode is to be formed, and then a metal layer is formed thereon. By patterning, the metal wirings 6 ₁ and 6 ₂ are attached, and an element substrate for an infrared detection device in which a large number of infrared detection elements (pn junction photodiodes) are arranged at a pitch of 37 μm is completed. As described above, when the structure in which the p-type region and the n-type region are exposed on the upper surface of the infrared detecting element is used, the electrode can be taken from the upper surface of the infrared detecting element and the electrode forming process can be simplified.

FIG. 3 is an explanatory view of the structure of the hybrid type infrared detecting device of the first embodiment. In this figure, 1 is a Si substrate, 2 is a CdTe buffer layer, 2 ₂ is a groove, 3 is p.
Type HgCdTe layer, 4 n-type HgCdTe layer, 5 Zn
S protective film, 6 ₁ and 6 ₂ metal wiring, 7 Si signal processing circuit board, 7 ₁ and 7 ₂ MOS circuit section, 7 ₃ common electrode,
8 ₁ , 8 ₂ and 8 ₃ are In bumps.

The Si signal processing circuit board 7 having the MOS circuit parts 7 ₁ and 7 ₂ and the common electrode 7 ₃ is placed on the element substrate for the infrared detecting device completed by the manufacturing process described with reference to FIG. Metal wiring 6 ₁ , 6 ₂ of the element substrate for the detection device and the MOS circuit portion 7 of the Si signal processing circuit substrate 7
_1, 7 _2, an In bump 8 between the common electrode 7 _{3 1,} 8 _2,
Connect by 8 ₃ .

As a result, C formed on the Si substrate 1
The bottom surface and the periphery are surrounded by the dTe buffer layer 2, and Cd
A pn junction is formed between the n-type HgCdTe layer 4 formed on a part of the upper surface of the p-type HgCdTe layer 3 separated by the lattice-shaped grooves 2 ₂ provided in the Te buffer layer 2 and the upper surface thereof is formed. The metal wirings 6 ₁ and 6 ₂ formed through the openings of the ZnS protective film 5 for covering and the MO of the Si signal processing circuit board 7 are formed.
The In bump 8 is provided between the S circuit portions 7 ₁ and 7 ₂ and the common electrode 7 _3.
A hybrid type infrared detection device connected by ₁ , 8 ₂ and 8 ₃ is realized.

FIG. 4 is a diagram showing the construction of the monolithic infrared detector of the first embodiment. In this figure, 1 is a Si substrate, 2 is a CdTe buffer layer, 2 ₂ is a groove, 3 is p.
Type HgCdTe layer, 4 n-type HgCdTe layer, 5 Zn
S protective film, 6 ₁ and 6 ₂ are metal wiring, and 7 ₁ and 7 ₂ are MOS
It is a circuit part.

In the manufacturing process described with reference to FIG. 2, the infrared detecting device is formed by using the Si substrate 1 on which the MOS circuit parts 7 ₁ and 7 ₂ are formed, and the infrared detecting device is formed on the Si substrate 1 between the adjacent infrared detecting elements. Exposed MOS circuit parts 7 ₁ , 7
Connect the metal wires 6 ₁ , 6 ₂ of the infrared detection element to ₂ .

As a result, C formed on the Si substrate 1
The bottom surface and the periphery are surrounded by the dTe buffer layer 2, and Cd
A pn junction is formed between the n-type HgCdTe layer 4 formed on a part of the upper surface of the p-type HgCdTe layer 3 separated by the lattice-shaped grooves 2 ₂ provided in the Te buffer layer 2 and the upper surface thereof is formed. Metal wirings 6 ₁ and 6 ₂ formed through the opening of the ZnS protective film 5 for covering and M formed on the Si substrate 1
A monolithic infrared detection device in which the OS circuit parts 7 ₁ and 7 ₂ are connected to each other is realized.

(Second Embodiment) In the first embodiment, H
Introduce Hg vacancies into the gCdTe layer to make it p-type, and
Was ion-implanted to form a pn junction. Alternatively, a HgCdTe layer may be grown to form As and Sb as acceptors and I, In, and Ga as donors to form a pn junction. it can.

FIG. 5 is an explanatory view of the manufacturing process of the infrared detector of the second embodiment. In this figure, the Si substrate 11, 12 is CdTe buffer layer, 12 _first recess, 13 p-type HgCdTe layer 14 is an n-type HgCdTe layer. A method of manufacturing the infrared detection device according to the second embodiment will be described with reference to the manufacturing process explanatory diagram.

First Step A CdTe buffer layer 12 is formed on the Si substrate 11,
The region of the CdTe buffer layer 12 where the infrared detecting element is to be formed is selectively removed by etching while leaving a part of the CdTe buffer layer 12 to form the recess 12 ₁ .

Second step CdTe buffer layer 12 recess 12 ₁ formed in the previous step
P-type HgCdTe layer 13 with As added to fill
To form. The surface shape of the p-type HgCdTe layer 13 is similar to the shape of the concave portion 12 ₁ of the CdTe buffer layer 12, and unevenness occurs.

Third Step: An n-type HgCdTe layer 14 containing iodine (I) is formed on the p-type HgCdTe layer 13 having an uneven surface.

Fourth Step A part of the n-type HgCdTe layer 14 and the p-type HgCdTe layer 13 having irregularities on the surface is partially replaced with the CdTe buffer layer 12.
The upper portions of the convex portions between the concave portions 12 ₁ are removed by polishing or the like, and the n-type HgCdTe layer 13 is partially formed on the p-type HgCdTe layer 13.
By leaving the layer 14, a pn junction to be an infrared sensing element is formed.

After that, the steps after the step of forming a groove in the CdTe buffer layer 12 around the pn junction which becomes the infrared detecting element to separate the elements or the step of manufacturing the hybrid type or monolithic type infrared detecting device are performed first. First
As described in the examples.

By changing the heat treatment from the p treatment to the n treatment, the infrared detecting element substrate having the separation structure similar to that of the second embodiment can be formed by the same process as described above. In this case, the p-type layer and the n-type layer may be reversed.

(Third Embodiment) FIGS. 6A to 6C are explanatory views of the manufacturing process of the infrared detector of the third embodiment. In this figure,
21 Si substrate, 22 is CdTe buffer layer, 23 ₁ recesses, p-type Hg _0.5 Cd _0.5 Te layers 23, 23 ₂ grooves, 24 p-type Hg _0.8 Cd _{0. 2} Te layer 25 is n-type H
g _0.8 Cd _0.2 Te layer, 26 a protective film, and 27 a metal electrode. A method of manufacturing the infrared detection device according to the second embodiment will be described with reference to the manufacturing process explanatory diagram.

First Step A CdTe buffer layer 22 is formed on the Si substrate 21,
On the CdTe buffer layer 22, a p-type Hg _0.5 Cd _0.5 Te layer 23 containing As is formed. This p-type Hg
The region of the _0.5 Cd _0.5 Te layer 23 where the infrared detecting element is to be formed is selectively removed by etching while leaving a part of the p-type Hg _0.5 Cd _0.5 Te layer 23 to form the recess 23 ₁ .

Second Step p-type Hg _0.8 having Hg vacancies so as to fill the recess 23 ₁ of the p-type Hg _0.5 Cd _0.5 Te layer 23 formed in the previous step.
A Cd _0.2 Te layer (Cd composition ratio <30%) 24 is formed.

Third step p-type Hg_0.8Cd_0.2Photo on part of the surface of Te layer 24
A mask is formed using lithography technology, and
Boron (B) is ion-implanted through the
N type Hg_0.8Cd_0.2Form Te layer 25
And then p-type Hg _0.8Cd_0.2Pn junction in Te layer 24
Due to this, multiple infrared detection element areas have been formed.
It

Fourth Step Next, a mask having openings around a plurality of infrared detection element regions formed by pn junction is formed on the p-type Hg _0.8 Cd _0.2 Te layer 24 by photolithography.
P-type Hg _0.5 Cd _0.5 exposed on the surface through this opening
The Te layer 23 is etched to separate the infrared detecting elements by the groove 23 ₂ .

This etching forms a lattice-shaped groove 23 ₂ having a small width and a large depth, and therefore it is necessary to apply a dry etching method. In this embodiment, the groove 23 ₂ to be etched and the groove 23 ₂ to be etched are formed. Type Hg _0.8 Cd _0.2 Te layer 24
Since there is a p-type Hg _0.5 Cd _0.5 Te layer 23 between them, the direct damage due to dry etching is p-type Hg _{0.5 .}
It does not reach the ₈ Cd _0.2 Te layer 24.

Further, p-type Hg having a relatively large Cd composition ratio
_{The 0.5} Cd _0.5 Te layer 23 does not have a dissociation pressure of constituent elements higher than that of the p-type Hg _0.8 Cd _0.2 Te layer 24 having a relatively small Cd composition ratio, and therefore the p-type Hg _0.8 Cd _0.2 It will protect the Te layer 24. In addition, the p-type Hg _0.5 Cd _0.5 Te layer 23 and the p-type Hg
Since the lattice constants of the g _0.8 Cd _0.2 Te layer 24 are equal, no strain occurs between the two layers.

Fifth Step A protective film 26 is formed from the p-type Hg _0.8 Cd _0.2 Te layer 24 having the pn junction formed thereon to the p-type Hg _0.5 Cd _0.5 Te layer 23, and the metal electrode is formed through the opening of the protective film 26. 27 is formed.

Impurities are added to the side surface of the separating groove 23 ₂ of the p-type Hg _0.5 Cd _0.5 Te layer 23 so that electrical conduction can be established, and the depth of the groove 23 ₂ is adjusted so that p
When the type Hg _0.5 Cd _0.5 Te layer 23 is left slightly, the step of forming the metal wiring becomes unnecessary.

(Fourth Embodiment) FIG. 7 is a drawing for explaining the manufacturing process of the infrared detector of the fourth embodiment, and (A) and (B) show the respective processes. In this figure, 31 is a Si substrate, 31 ₁ is a ridge, 31 ₂ is a groove, 32 is a CdTe buffer layer, 32 ₁ is a recess, and 33 is a p-type HgCdTe layer. A method of manufacturing the infrared detection device of the fourth embodiment will be described with reference to the manufacturing process explanatory diagram.

First step (see FIG. 7A) The upper surface of the Si substrate 31 is preliminarily processed to have projections and depressions to form a ridge 31 ₁ surrounding an area where an infrared detecting element is to be formed.
A CdTe buffer layer 32 is grown on this Si substrate 31. A recess 32 ₁ is formed on the surface of the grown CdTe buffer layer 32. CdTe having this recess 32 ₁
A p-type HgCdTe layer 33 is grown on the buffer layer 32.

Second step (see FIG. 7B) CdTe buffer layer 32 and p-type HgC formed in the previous step
The ridge 3 having the dTe layer 33 formed on the upper surface of the Si substrate 31.
It was removed to 1 ₁ of the upper end, and then, by forming a groove 31 ₂ ridges 31 ₁ part of the upper surface of the Si substrate 31 is dry etched to separate the infrared detection element region.
The step of forming a pn junction on the p-type HgCdTe layer 33 and the like are the same as those in the above-described embodiment, and are therefore omitted.

In the above-described methods for manufacturing the infrared detectors according to the first to third embodiments, the CdTe buffer layer grown to have a uniform thickness on the Si substrate or the Si substrate on the Si substrate is used. After the p-type Hg _0.5 Cd _0.5 Te layer 23 having a uniform thickness was grown on the CdTe buffer layer that was grown, the target unevenness processing was performed using the photolithography technique.

The film forming method and the film forming apparatus of the present invention described below can be widely applied to the manufacturing method of the crystal and the element using the vapor phase growth technique. It can be applied suitably.

In general, when the vapor phase growth method is used, it is possible to continuously grow a film such as a crystal layer having different kinds or different characteristics on a substrate. Therefore, for example, a compound is formed on an inexpensive substrate. It is indispensable for mass production of compound semiconductor devices and the like by forming semiconductor crystal layers and the like, or for development of new functional devices that require multilayered element structures.

Conventionally, when it is necessary to form protrusions, ridges, etc. on a substrate, a wafer having a uniform thickness or a film grown with a uniform thickness is subjected to a processing technique such as an etching method. Has achieved the desired structure. But,
Such a processing technique increases the number of processes or complicates the process along with the miniaturization of devices, which causes a decrease in yield.

In the case of a film such as a crystal layer grown on a different type of substrate, due to the difference in the coefficient of thermal expansion between the substrate and the film,
At the stage of adding a process having a heat cycle, transitions and the like that cause deterioration of device characteristics are likely to occur. Therefore,
It is necessary to realize the device to some extent by the growth of the coating itself, aiming at simplification and omission of the process.

The film-forming method or film-forming apparatus of the present invention has a target device structure in the step of growing a film such as a semiconductor layer on the substrate instead of etching the substrate having a uniform thickness. It is intended to provide a means of forming part of the device structure by growth of the film itself, using a method commensurate with. By forming a part of the device structure on the substrate by so-called selective growth, it is possible to separate the film such as a crystal layer into the device size from the beginning of the manufacturing process. It is possible to suppress the influence of.

FIG. 9 is an explanatory view of the principle of the film forming method and the film forming apparatus of the present invention, and (A) to (E) show respective modes. In this figure, 51 is a substrate heating table, 52 is a substrate mounting table, and 53 and 54 are film growth substrates.

This figure shows a film forming method and a film forming apparatus according to three aspects of the present invention. First Aspect (See FIG. 9A) Between the substrate heating table 51 for heating the film growth substrate 53 in the vapor phase growth apparatus and the film growth substrate 53, the film is grown on the film growth substrate 53. A substrate mounting table 52 having a thick portion of a desired film pattern is interposed so that the thick portion contacts the film-growth substrate 53, and a film having a desired pattern is grown on the film-growth substrate 53. .

Second Mode (Refer to FIG. 9B) Between the substrate heating table 51 for heating the film growth substrate 53 in the vapor phase growth apparatus and the film growth substrate 53, the film growth substrate 53 is provided. The substrate mounting table 52 having the thick portion of the coating pattern to be grown on is intervened so that the thick portion contacts the substrate heating table 51, and the coating of the desired pattern is formed on the coating growth substrate 53. grow up.

Third Mode (see FIG. 9C) For film growth having a thick portion of a film pattern to be grown on a substrate heating table 51 for heating a film growth substrate in a vapor phase growth apparatus. The substrate 54 is placed with its thick portion in contact with the substrate heating table 51, and a film having a desired pattern is grown on the film growth substrate 54. In addition, FIG.
(E) shows the positional relationship between the substrate mounting table 52 and the film growth substrate 53.

In the first and second aspects, when the substrate heating table 51 is heated, the portion of the surface of the film growth substrate 53 corresponding to the thick portion of the substrate mounting table 52 is the substrate heating table 51. Since the thermal resistance between the two is small, the temperature becomes high, and the portion corresponding to the thin portion has a space and the thermal resistance is large, so the temperature becomes low, and the pattern of the thick portion of the substrate mounting table is formed on the surface of the film growth substrate 53. A temperature distribution with the same high temperature region results.

In this state, on the upper surface of the film growth substrate 53,
When a film such as a crystal layer is grown by a growth method such as CVD or MOCVD, a thick film grows because the organic metal is easily decomposed in a high temperature portion, and the organic metal is difficult to decompose in a low temperature portion, which is thin. The film grows. Therefore, it is possible to grow protrusions, ridges, etc. corresponding to the pattern of the thick portion of the substrate mounting table 52.

FIG. 10 is a diagram for explaining the relationship between the growth temperature and the growth rate of HgCdTe. The horizontal axis of this figure shows the growth temperature and the vertical axis shows the growth rate of HgCdTe, but it can be seen that the growth rate increases with the increase of the growth temperature.

When growing a mixed crystal type film,
Since a film having a mixed crystal ratio (composition) different depending on the temperature of the film-growth substrate grows, it is possible to provide a composition distribution corresponding to the pattern of the thick portion of the substrate mounting table 52. This is effective when forming regions having different electrical characteristics due to different composition ratios.

FIG. 11 shows the growth temperature and C in HgCdTe.
It is a relationship explanatory view of the composition ratio of d. The horizontal axis of this figure shows the growth temperature and the vertical axis shows the composition ratio of Cd in the grown HgCdTe. However, as the growth temperature rises, the composition ratio of Cd decreases and Hg _{1- x} Cd _x Te is seen to grow.

Further, in the third embodiment, when the substrate heating table 51 is heated, the portion of the surface of the film growth substrate 54 corresponding to the thick portion of the film growth substrate 54 is heated by the substrate heating table 5.
1 has a small thermal resistance with respect to 1 and becomes a high temperature, and a portion corresponding to the thin portion has a space and has a large thermal resistance, resulting in a low temperature, and the surface of the film growth substrate 54 has a thickness of the film growth substrate 54. A temperature distribution occurs that has the same high temperature region as the pattern of the parts.

In this state, on the upper surface of the film growth substrate 54,
When a film such as a crystal layer is grown by a growth method such as CVD or MOCVD, the growth rate depends on the surface temperature of the film-growth substrate 54. Therefore, a thick film grows in a high temperature part and a low temperature part in a low temperature part. A thin film grows. Therefore, it is possible to grow a film having a composition with respect to the growth temperature, such as a protrusion or a ridge corresponding to the pattern of the thick portion of the film growth substrate 54.

(Fifth Embodiment) FIG. 12 is a schematic diagram showing the structure of a metal-organic vapor phase film forming apparatus according to the fifth embodiment. In this figure, 61 is a vapor phase growth chamber, 62 is a raw material introduction port, 63 is an exhaust port, 64 is a substrate heating table, 65 is a substrate mounting table, 66 is a film growth substrate, and 67 is an RF coil.

Metal-organic vapor phase deposition (MOCV) of this example
D) In the apparatus, the substrate heating table 64 is arranged in the vapor phase growth chamber 61 having the raw material introducing port 62 and the exhaust port 63, and the substrate having the structure described with reference to FIG. The mounting table 65 is mounted, and the film growth substrate 66 is mounted thereon. Then, the substrate heating base 64 is heated by the RF coil 67 arranged outside the vapor phase growth chamber 61.

In this metal-organic vapor phase film forming apparatus, a substrate placing table 65 having a thick portion of a desired pattern is placed on a substrate heating table 64 in a vapor phase growth chamber 61, and Si or the like is placed thereon. The substrate 66 for growing the film is placed on the substrate heating table 6 by the RF coil 67 arranged outside the vapor phase growth chamber 61.
4 is heated, an organic metal gas containing the constituent elements of the film to be grown is introduced from the raw material introduction port 62, and the organic metal gas is decomposed on the film growth substrate 66 to grow a film having a desired composition. To do.

FIGS. 13A to 13C are explanatory views of the manufacturing process of the infrared detector of the fifth embodiment. FIGS. 13A to 13C show each process, and FIG. 13D shows an enlarged joint. In this figure, 71 is a film growth substrate, 72 is a CdTe buffer layer, 72 ₁ is p-type CdTe (Hg), and 72 ₂ is CdTe.
(Hg), 73 is p-type HgCdTe layer, 74 is n-type Hg
CdTe layer, 74 ₁ is an opening, 75 is an HgTe layer, 76 is an insulating film, 76 ₁ is an opening, and 77 is a p-type electrode.

The manufacturing method of the infrared detector according to the fifth embodiment will be described with reference to the manufacturing process explanatory diagram.
A case of manufacturing an infrared detector having a pn junction in gCdTe will be described as an example.

First step (see FIGS. 13 (A) and 13 (D)) The thickness is up to 500 μm and is carved at a depth of up to 100 μm to form a meat pressure portion having a pattern with a pitch of up to 100 μm. , Si, sapphire or the like, and the substrate heating table 64 (see FIG. 12) of the metal-organic vapor phase film deposition apparatus with the thick portion facing upward or downward.
) And a substrate mounting table 65 on the substrate heating table 64 with a thickness of ˜100 μm of Si or GaAs.
A film growth substrate 71 made of is placed. The film growth substrate 71 is heated by induction heating the substrate heating table 64 by the RF coil 76 (see FIG. 12).

The raw materials introduced into the metal-organic vapor phase film forming apparatus are
Organometallic dimethyl cadmium (DMCd), diisopropyl tellurium (DIPTe) and metallic mercury (Hg)
That is, these are diluted with hydrogen gas and simultaneously supplied from the raw material inlet 62 at a flow rate of 5 liters / minute. Growth is carried out at 360 ° C. under normal pressure. This is HgTe (HgCdT
This is because the dissociation pressure of e) is high and the crystals will not grow when the growth temperature is raised.

Therefore, the growth temperature is set to the lower decomposition temperature of DIPTe, which has a higher decomposition temperature among the organic metals used. The partial pressure of the raw material is such that Hg is -10 ^-2 at
m, DMCd is -10 ^-5 atm, DIPTe is -10 ^-3
It is set to atm. Then, the CdTe buffer layer 72
/ P-type HgCdTe layer 73 / n-type HgCdTe layer 74 /
Although the HgTe layer 75 and the HgTe layer 75 are continuously grown, they will be sequentially described below.

When the CdTe buffer layer 72 is grown, a thick CdTe buffer layer 72 grows at a high temperature portion where the group VI DIPTe, which makes a large contribution to the grown film thickness, is easily decomposed, and a thicker CdTe buffer layer 72 becomes thinner at a low temperature portion. The CdTe buffer layer 72 grows.

The temperature difference between the high temperature portion and the low temperature portion is about -20 ° C., and the difference in the growth rate of the CdTe buffer layer 72 is about 20%. The thickness of the grown CdTe buffer layer 72 is 15 μm in the high temperature portion and 12 μm in the low temperature portion.

This CdTe buffer layer 72 is made of GaAs.
When a substrate for film growth made of is used, it is necessary to prevent impurity diffusion from the substrate for film growth or to alleviate lattice mismatch.

P-type HgC is formed on the CdTe buffer layer 72.
A dTe layer 73 and an n-type HgCdTe layer 74 are grown. More specifically, the composition of the Hg _1-x Cd _x Te layer is quite sensitive to the growth temperature, and a temperature difference of -20 ° C. causes a composition difference of x = 0.5 or more. This is because DMCd decomposes at a lower temperature than DIPTe. At this growth temperature, radiant heat from the substrate heating table causes decomposition of DMCd before it grows on the film growth substrate 71 such as Si or GaAs. Will end up. Therefore, in a region where the temperature is high, DMCd is excessively decomposed, so that the amount of Cd taken into the crystal is reduced.

On the other hand, in the low temperature region, since excessive decomposition of DMCd is suppressed, a large amount of C is contained in the growing crystal layer.
d is captured. When making a device, x = 0.
Since a composition of 2 to 0.3 is required, the source material concentration ratio to be supplied is adjusted so that the target composition is obtained in the high temperature portion of the film growth substrate. Therefore, the Hg _1-x Cd _x Te layer having a composition of x = 0.7 or more grows in the low temperature portion.

The p-type HgCdTe layer 73 was grown by introducing tert-butylarsine (partial pressure: 10 ⁻⁴ atm), which is an organic As, as a dopant to grow the n-type HgCdTe layer 73.
The CdTe layer 74 is grown undoped without introducing impurities. Also for the p-type HgCdTe layer 73 and the n-type HgCdTe layer 74, the CdTe buffer layer 7
Similar to No. 2, a difference in thickness occurs between the high temperature portion and the low temperature portion.

The thickness of the p-type HgCdTe layer 73 after growth is 2.5 μm, and the thickness of the n-type HgCdTe layer 74 after growth is 20 μm. Therefore, the region of high composition corresponding to the low temperature portion is about 18 μm. Further, an HgTe layer 75 having conductivity is grown thereon to have a thickness of 10 μm or more, thereby forming an element structure as shown in FIG.

Since the CdTe buffer layer 72 and the non-doped HgCdTe layer 72 ₂ (x value is 0.7 or more) exhibit insulating properties, the p-type HgCdTe layer 73 and the n-type HgCdTe layer 73 are not formed.
Since the n / p structure formed of the gCdTe layer 74 is separated by the insulating film, the CdTe buffer layer (insulating film) 72, the p-type CdTe layer as shown in FIG.
(Hg) 72 ₁ , CdTe (Hg) 72 ₂ (insulating film),
A film having a structure composed of the p-type HgCdTe layer 73 and the n-type HgCdTe layer 74 is formed.

Second Step (Refer to FIG. 13B) On the Si or GaAs film growth substrate 71, C
After growing the dTe buffer layer 72 / p-type HgCdTe layer 73 / n-type HgCdTe layer 74 / HgTe layer 75,
By surface polishing, n-type HgCdTe layer 74 / p-type Hg
The HgTe layer 75 on the CdTe layer 73 is ground flat.

[0105] The third step of the opening ₁ 74 to reach the p-type HgCdTe layer 73 is formed on the n-type HgCdTe layer 74 (FIG. 13 (C) see) n-type HgCdTe layer 74 / p-type HgCdTe layer 73 structure, the opening An insulating film 76 made of ZnS is grown around the opening 76 of the insulating film 76.
P-type electrode 7 reaching p-type HgCdTe layer 73 through ₁
Form 7.

The CdTe buffer layer 72 insulates the infrared detecting elements from each other, and the HgT is in contact with the p-type HgCdTe layer 73 through the n-type HgCdTe layer 74.
A common electrode is formed by the e layer 75. Therefore,
For the electrode formation process after the semiconductor layer growth process, Hg
Since it is only necessary to remove the electrode from the Te layer 75,
A great simplification of the manufacturing process is realized.

(Sixth Embodiment) Regarding the film growth substrate 71, it is necessary to select the optimum one for each embodiment because of the problem of the coefficient of thermal expansion with CdTe (HgCdTe). In the case of the fifth embodiment, there is an advantage that the common electrode is formed by growth instead of having no separation groove.

However, since there is no separation groove, if a Si substrate having a large difference in coefficient of thermal expansion from CdTe is used, the crystal may be cracked during the thermal cycle. In such a case, the crystal expands as a substrate. It is necessary to use GaAs with a small difference in the rate.

FIG. 14 is a drawing explaining the manufacturing process of the infrared detector of the sixth embodiment, and (A) to (D) show each process. In this figure, 81 is a Si substrate and 82 is Cd.
Te buffer layer, 83 p-HgCdTe layer, 84 n
-HgCdTe layer, 84 ₁ opening, 85 CdTe layer,
85 ₁ is a separation groove, 86 is a common electrode, 87 is an insulating film, 87
₁ is an opening and 88 is an electrode. A method of manufacturing the infrared detector according to the second embodiment will be described with reference to the manufacturing process explanatory diagram.

First Step (See FIG. 14A) CdTe buffer layer 82 and p-Hg are formed on the Si substrate 81.
After forming the CdTe layer 83 and the n-HgCdTe layer 84, the n-HgCdTe layer 84 and the p-HgCdTe layer 83 are formed.
Then, a recess is formed by selectively etching away the region where the infrared detecting element is to be formed. A CdTe layer 85 is formed on the entire surface including the separation groove on the CdTe layer 85 in a thickness of 10 μm or more.
In this case, the upper surface of the CdTe layer 85 becomes uneven due to the shape of the underlying separation groove.

Second step (see FIG. 14B) The CdTe layer 85 having an uneven surface is formed on the n-HgC layer.
The dTe layer 84 is removed by polishing until the upper surface is exposed. The obtained p-HgCdTe layer 83 and n-HgCd
The crystal layer of the Te layer 84 is composed of the CdTe buffer layer 82 and the CdTe buffer layer 82.
A pn junction, which serves as an infrared detection element, is formed by element separation by the Te layer 85.

Third step (see FIG. 14C) By dry etching, pn to be an infrared detecting element is formed.
Part of the CdTe layer 85 and the CdTe buffer layer 82 surrounding the junction and having a low dissociation pressure is removed to remove the separation groove 85 _1.
To form.

Fourth Step (See FIG. 14D) A common electrode 86 is formed by forming a conductor layer on the sidewall of the isolation trench 85 _1.
To form p-HgCdTe on the n-HgCdTe layer 84.
An opening 84 ₁ reaching the layer 83 is formed, an insulating film 87 is formed on the side wall of the opening 84 ₁ , and an electrode 88 on the p-HgCdTe layer 83 side is formed in the opening 87 ₁ of the insulating film 87.

Through the above steps, the n-HgCdTe layer 84 is connected by the common electrode 86, and p-HgCdTe of the independent infrared detecting element separated by the separation groove is formed.
An infrared sensing device having an electrode connected to layer 83 is formed. In this case, each infrared detection element has a separation groove 85 ₁
Are separated by Si substrate 81 and CdT.
e buffer layer 82, p-Hg CdTe layer 83, n-Hg
It is possible to relieve the strain during the thermal cycle caused by the difference in the coefficient of thermal expansion between the CdTe layers 84. In this case, the p-type layer and the n-type layer may be reversed.

In this embodiment, the case of manufacturing the infrared detecting device has been described, but it goes without saying that the film forming method and the film forming device of this embodiment can be applied to the case of growing a general film. Absent.

[0116]

As described above, according to the semiconductor photodetecting device and the method of manufacturing the same of the present invention, the strain generated when the semiconductor crystal layer forming the plurality of photodetecting elements and the substrate have different thermal expansion coefficients is applied. To prevent damage to the semiconductor crystal layer that occurs when separating each infrared detection element by grooves or multiple holes by dry etching to prevent each infrared detection element, use dry etching to narrow the separation. The structure can be realized, and it greatly contributes to high integration and performance improvement of the infrared detection device.

Further, according to the film forming method and the film forming apparatus of the present invention, the manufacturing process can be greatly simplified, and the yield can be improved by omitting the manufacturing process, which contributes widely to the field of film forming technology. There is a lot to do.

[Brief description of drawings]

FIG. 1 is an explanatory view of a manufacturing process of a photodetector of the present invention,
(A)-(C) has shown each process.

FIG. 2 is an explanatory view of the manufacturing process of the infrared detection device according to the first embodiment, in which (A) to (D) show each process.

FIG. 3 is a structural explanatory view of a hybrid type infrared detection device of a first embodiment.

FIG. 4 is an explanatory diagram of a configuration of a monolithic infrared detector according to the first embodiment.

FIG. 5 is a drawing explaining the manufacturing process of the infrared detector of the second embodiment.

FIG. 6 is a drawing explaining the manufacturing process of the infrared detector of the third embodiment.

FIG. 7 is an explanatory view of the manufacturing process of the infrared detector of the fourth embodiment, in which (A) and (B) show the respective processes.

FIG. 8 is an explanatory view of a manufacturing process of a conventional infrared detection device, and (A) to (C) show each process.

FIG. 9 is an explanatory view of the principle of the film forming method and the film forming apparatus of the present invention, in which (A) to (E) show respective modes.

FIG. 10 is an explanatory diagram of a relationship between a growth temperature and a growth rate of HgCdTe.

FIG. 11 is a diagram illustrating the relationship between the growth temperature and the composition ratio of Cd in HgCdTe.

FIG. 12 is a schematic structural explanatory view of a metal-organic vapor phase film forming apparatus according to a fifth embodiment.

13A to 13C are explanatory views of the manufacturing process of the infrared detection device of the fifth embodiment, in which (A) to (C) show each process, and (D) shows an enlarged joint portion.

FIG. 14 is an explanatory view of the manufacturing process of the infrared detector of the sixth embodiment, in which (A) to (D) show each process.

[Explanation of symbols]

1 Si Substrate 2 CdTe Buffer Layer 2 ₁ Recess 2 ₂ Groove 3 p-type HgCdTe Layer 4 n-type HgCdTe Layer 5 ZnS Protective Film 6 ₁ , 6 ₂ Metal Wiring 7 Si Signal Processing Circuit Board 7 ₁ 7 ₂ MOS Circuit Section 7 ₃ Common electrode 8 ₁ , 8 ₂ , 8 ₃ In bump 11 Si substrate 12 CdTe buffer layer 12 ₁ recess 13 p-type HgCdTe layer 14 n-type HgCdTe layer 21 Si substrate 22 CdTe buffer layer 23 p-type Hg _0.5 Cd _0.5 Te layer 23 ₁ Depression 23 ₂ groove 24 p-type Hg _0.8 Cd _0.2 Te layer 25 n-type Hg _0.8 Cd _0.2 Te layer 26 protective film 27 metal electrode 31 Si substrate 31 ₁ ridge 31 ₂ groove 32 CdTe buffer layer 32 ₁ recess 33 p-type HgCdTe layer 41 Si substrate 42 CdTe buffer layer 43 HgCdTe layer 43 ₁ defect layer 44 n-HgCdTe layer 45 groove 51 substrate Heat block 52 substrate mounting table 53, 54 coat the growth substrate 61 vapor deposition chamber 62 feed inlet 63 outlet 64 substrate for heating the substrate table 65 substrate mounting table 66 film growth 67 RF coil 71 Si substrate 72 CdTe buffer layer 72 ₁ p-type CdTe (Hg) 72 ₂ CdTe (Hg) 73 p-type HgCdTe layer 74 n-type HgCdTe layer 74 ₁ opening 75 HgTe layer 76 insulating film 76 ₁ opening 77 p-type electrode 81 Si substrate 82 CdTe buffer layer 83 p-HgCdTe layer 84 n-HgCdTe layer 84 ₁ opening 85 CdTe layer 85 ₁ separation groove 86 common electrode 87 insulating film 87 ₁ opening 88 electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/14 A

Claims (11)

[Claims] 1. The substrate and the substrate have different thermal expansion coefficients,
A semiconductor crystal layer having a high dissociation pressure of the constituent elements, wherein the semiconductor crystal layer having a high dissociation pressure of the constituent elements is at least partially divided by groove-shaped, hole-shaped, or lattice-shaped recesses to form a light-sensing element. And the side surface of the recess dividing the photo-sensing element is covered with a semiconductor crystal layer having a lattice constant similar to that of a semiconductor crystal layer having a low dissociation pressure of the constituent element and a high dissociation pressure of the constituent element. Semiconductor photo detector. 2. The substrate is Si, GaAs or Al ₂ O ₃
And a semiconductor crystal layer having a high dissociation pressure of the constituent elements forming the photodetector is Hg _1-x Cd _x Te (x <
0.3), which has a low dissociation pressure of the constituent elements and covers the side surface of the recess that divides the photodetector, the semiconductor crystal layer is C
dTe, CdZnTe or Hg _1-x Cd _x Te (x>
The semiconductor photodetector according to claim 1, wherein the semiconductor photodetector is formed of 0.4). 3. A photodetecting element is formed by a pn junction of a semiconductor crystal layer having a high dissociation pressure of constituent elements, and a p-type region or an n-type region forming the pn junction dissociates the constituent elements from the semiconductor crystal layer. The semiconductor photodetecting device according to claim 1, wherein the semiconductor photodetecting device is formed of a semiconductor layer that generates carriers that are electrons or holes by the generated holes. 4. The photo-sensing element is formed by a pn junction of a semiconductor crystal layer having a high dissociation pressure of constituent elements, and the p-type region or the n-type region forming the pn matching is formed by introducing different kinds of impurities. The semiconductor photodetector according to claim 1, wherein the semiconductor photodetector is formed of a semiconductor layer that generates carriers that are electrons or holes. 5. The semiconductor photodetecting device according to claim 3, wherein a p-type region and an n-type region are exposed on the upper surface of the photodetecting element. 6. A step of processing the surface of a substrate or a semiconductor crystal layer having a low dissociation pressure of constituent elements deposited on the substrate to form columnar, fence-shaped or lattice-shaped convex portions, and the convex portions. A step of forming a semiconductor crystal layer having a high dissociation pressure of constituent elements so as to fill the recess formed between the substrate and the semiconductor crystal layer having a low dissociation pressure of constituent elements deposited on the substrate or the substrate. , The semiconductor crystal layer having a high dissociation pressure of the constituent element is at least partially separated by selectively removing the constituent element with a high dissociation pressure of the constituent element. A method of manufacturing a photodetecting device, comprising the step of forming. 7. A method for selectively removing a substrate or a semiconductor crystal layer having a low dissociation pressure of constituent elements deposited on the substrate into a groove shape, a hole shape, or a lattice shape, by using high-energy particles such as ions or plasma. 7. The light according to claim 6, wherein the dry etching method using is used so that the region to be dry-etched does not reach the semiconductor crystal layer in which the dissociation pressure of the constituent elements forming the photodetecting element is high. Manufacturing method of detection device. 8. A substrate mounting table having a thick portion of a coating pattern to be grown on the substrate for growing a film is provided between the substrate heating table for heating the substrate for growing a film and the substrate for growing the film. A film forming method, wherein a film is grown on the film-growth substrate with the film being interposed so as to contact the film-growth substrate. 9. A substrate mounting table having a thick portion of a coating pattern to be grown on the substrate for growing a film is provided between the substrate heating table for heating the substrate for growing a film and the substrate for growing the film. A film forming method, wherein a film is grown on a film-growth substrate while the film is interposed so as to contact a substrate heating table. 10. A substrate for growing a film having a thick portion of a coating pattern to be grown is placed on a substrate heating table for heating the substrate for growing a film so that the thick portion contacts the substrate heating table. In the state, a film forming method comprising: growing a film on a film growth substrate. 11. A film forming apparatus, wherein a substrate mounting table having a thick portion of a film pattern to be grown is mounted on a substrate heating table for heating a film growth substrate.