JPH07321071A - Manufacture of semiconductor device and chip transfer jig - Google Patents

Abstract

PURPOSE:To decrease the probability of causing damage after a semiconductor device is formed by a method wherein a discoid wafer subjected to slicing work is diced into semiconductor device chips before being transferred to an integrated circuit formation process and the chips are transferred to the integrated circuit formation process one by one. CONSTITUTION:A wafer W manufactured by a process of manufacturing the wafer W is subjected to dicing work by a diamond blade 10 to manufacture chips T. In this dicing process, the chips T are polished and thinned down. After this polishing process, the chips T are cleaned. The chips T are transferred to an integrated circuit formation process one by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and a chip carrying jig for manufacturing chips by dicing before an integrated circuit forming process.

[0002]

2. Description of the Related Art Generally, in a conventional semiconductor device manufacturing process, as shown in FIG. 11, an integrated circuit forming process 71 for forming semiconductor elements on the entire surface of a wafer and a semiconductor device formed from the wafer on which the integrated circuit is formed. A chip manufacturing process 72 for manufacturing a chip which is the smallest unit of the shape, and an assembly process 73 for bonding and molding the chip. That is, the back surface grinding for reducing the thickness of the semiconductor element and the dicing for individually cutting the semiconductor element from the wafer are performed after the integrated circuit forming step 71.

On the other hand, the semiconductor device, on the other hand,
While thinning of semiconductor elements is required for incorporation in IC cards and the like, on the other hand, wafer size is reduced from φ5 inch to φ6 in response to mass production of semiconductor products.
Inches → φ8 inches → φ12 inches ... It tends to be expanded. Along with this, a high-performance and highly-efficient processing method and processing apparatus are being demanded for the back surface grinding technology and the dicing technology in the assembly process.

[0004]

Problems to be solved by the semiconductor manufacturing process in the prior art are as follows. <1> Back surface grinding and dicing in the assembly process are processes that generate dust after semiconductor elements are formed. Therefore, a great deal of cost and time are spent on reducing element damage during processing and cleaning during or after processing. However, these post-processing must be avoided. <2> DRAM (D ynam
ic R andom A ccess M emory) semiconductor device with a focus on, when reaching the 1G bit or 4G bit, high integration is also the element area is relatively large is attained,
It is easier to simplify the manufacturing line by adopting the transfer and manufacturing management for each individual element than the transfer and manufacturing management for each wafer. <3> Semiconductor devices centering on DRAM consume a great deal of expense and time in the element forming process,
It is not preferable from the viewpoint of yield and manufacturing cost to make a semiconductor device completed through such steps defective through back grinding and dicing, which are likely to cause damage due to impact.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device and a chip carrying jig in which dicing is performed before an integrated circuit forming process.

[0006]

According to the present invention, a disc-shaped wafer subjected to slicing processing is diced into chips for a semiconductor device before being transferred to an integrated circuit forming step, and the chips are integrated one by one. It is adapted to be transferred to a circuit forming process.

[0007]

According to the present invention, it is not necessary to spend a great deal of money and time for cleaning the chip. Also, since it becomes possible to adopt transport and manufacturing control for each individual element,
Easy to simplify the production line. Further, since the dicing is performed before the formation of the semiconductor element, the probability of causing damage after the formation of the semiconductor element becomes extremely small. By combining the above-mentioned effects, it is possible to increase the product yield and reduce the manufacturing cost. Especially, this special effect is 1G
It is remarkably effective for semiconductor devices centering on DRAMs of more than 1 bit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a method of manufacturing the semiconductor device of this embodiment. That is, the method of manufacturing a semiconductor device according to this embodiment includes, for example, a chip manufacturing process 1 for manufacturing a chip that is a minimum shape unit of a semiconductor device having a rectangular shape with one side of 10 mm to 30 mm, and a chip manufacturing process after the chip manufacturing process 1. An integrated circuit forming step 2 for forming an integrated circuit, an assembling step 3 for assembling a chip into the package after the integrated circuit forming step 2, and an inspection step 4 for inspecting electrical characteristics and reliability after the assembling step 3. ing. Then, the chip manufacturing process consists of the flowchart shown in FIG.
That is, the chip manufacturing process includes an ingot manufacturing process 7 in which a single crystal ingot 6 is formed by pulling the molten Si 5 from the molten Si 5 by the CZ (Czochralski) method shown in FIG. A wafer manufacturing step 9 for manufacturing a wafer W by slicing into a disc shape having a thickness of 625 μm by a diamond inner peripheral grinding wheel 8 shown in FIG. Wafer W
As shown in FIG. 5, a dicing process 11 for manufacturing the chip T by dicing the diamond T with a diamond blade 10, and polishing (including lapping, polishing, back surface grinding and etching) of the chip T after the dicing process 11. The polishing step 12 is performed to reduce the thickness to, for example, 200 μm, and the cleaning step 13 for cleaning the chip T after the polishing step 12. Here, as the dicing processing method, there are a blade dicing method using a diamond blade 10 as shown in FIG. 5, a laser scriber method, a diamond scriber method and the like. On the other hand, the integrated circuit formation process 2, such for example CMOS (C omplementary M eta 6
l O xide S emiconductor: If complementary MOS ... MOS P-channel and N channels, that form a circuit are formed on the same substrate), FIG. 7
As shown in the flowchart of FIG. 3, the oxidation step 1 in which the chip T is exposed to a high temperature oxidizing atmosphere to form the Si oxide film 14
5, a P well patterning step 16 for forming a pattern to be a P well region using a photoresist on the Si oxide film 14, and boron implantation by an ion implantation method using the patterned photoresist as a mask.
After the well impurity doping step 17, after the P well impurity doping step 17, the photoresist is removed and the implanted boron is thermally diffused to form a layer of the P well 18, and after the P well diffusion step 19. A Si nitride film is formed on the oxide film by the CVD method (vapor-phase growth by chemical reaction), a pattern of the element isolation region is formed by the photoresist method, and then the nitride film in the openings of the photoresist is removed by etching to open. A device isolation region patterning step 20 for forming holes and a thick field oxide film 21 by exposing the photoresist film to a high temperature using the nitride film as a mask after removing the photoresist.
A field oxidation step 22 for forming a film, a nitride film used as a mask and an oxide film thereunder are removed by etching to newly form a clean thin oxide film, and a polysilicon film 23 is formed thereon by a CVD method. Gate forming step 24 for forming a gate electrode, and gate forming step 2
After that, arsenic is ion-implanted in the P-well 18 region and boron is ion-implanted in the P-well region 18 other than the P-well region 18, and N ⁺ region 25
And N ⁺ / P ⁺ region forming step 2 for forming the P ⁺ region 26
7 and an interlayer insulating film forming step 29 of forming a thick oxide film 28 by the CVD method after the N ⁺ / P ⁺ region forming step 27.
And a contact hole patterning step 31 for opening contact holes 30 for connecting the individual elements and the metal wiring, and Al using the contact holes.
It is composed of an electrode / wiring forming step 33 for forming an electrode / wiring 32 of (aluminum). Further, in the assembling step 3, as shown in the flow chart of FIG. 8, the chip T passed through the integrated circuit forming step 2 is connected to the lead frame 3
4, a bonding step 37 for bonding the wires 36 to the electrodes and outer leads formed on the chip T after the mounting step 35, and the bonded chip T is sealed with an epoxy resin 38. And a molding step 39.

As described above, according to the semiconductor device manufacturing method of this embodiment, the sliced disk-shaped wafer W is used.
Are transferred to the integrated circuit forming step before being transferred to the integrated circuit forming step, and the chips T are transferred one by one to the integrated circuit forming step, so that the following remarkable effects are obtained. That is, since [1] the dicing is performed before the semiconductor element is formed, it is not necessary to spend a great amount of money and time for cleaning the chip T as in the case where the dicing is performed after the semiconductor element is formed. [2] DRAM
Since the semiconductor device centering on 1G bit or 4G bit has a relatively large element area even with high integration, transfer and manufacturing control for each individual element is adopted as in this embodiment. It is easier to simplify the production line.
[3] When dicing is performed after the semiconductor element is formed, there is a high probability that the semiconductor element will be damaged by the impact generated during the dicing process, which is one of the causes of the lower product yield and the higher manufacturing cost. Since the dicing is performed before the formation of the semiconductor element, the probability of damage occurring after the formation of the semiconductor element becomes extremely small, and the product yield can be increased and the manufacturing cost can be reduced. In particular, a semiconductor device centering on a DRAM consumes a great deal of cost and time in an element forming process, and is remarkably effective for a semiconductor device completed through such a process.

Next, the chip transfer jig 30 used in the method of manufacturing the semiconductor device of this embodiment will be described. The chip transfer jig 50 is used for various transfer operations of the chip T manufactured in the chip manufacturing process 1 in the integrated circuit forming process 2 and the assembly process 3, which are the next processes, and is as shown in FIG. In addition, a rectangular parallelepiped holding portion 52 having a hollow portion 51 inside, and a pipe-shaped decompression port 53 protruding from one side portion of the holding portion 52 and communicating with the hollow portion 51.
A valve 54 provided in the middle of the decompression port 53 for opening and closing the hollow portion 51 with respect to the outside air; and a holding portion 52.
Of the suction holes 55 provided on the chip mounting surface 52a. The area of the chip mounting surface 52a of the holding portion 52 is set larger than the area of the chip T.

In such a chip transfer jig 50,
First, the chip T is mounted on the chip mounting surface 52a. Next, after opening the valve 54, the decompression port 53 is connected to a decompression source such as a vacuum pump via a removable hose (not shown) to reduce the air pressure inside the hollow portion 51, and then the valve 54 is opened. Close it. As a result, the chip T
It closely adheres to the chip mounting surface 52a and is firmly fixed. Then, the hose is detached from the decompression port 53 and transferred to the predetermined semiconductor manufacturing process together with the transfer jig 50.

Thus, according to the chip carrying jig 50, it is possible to surely hold the chips T one by one even when they are processed in the integrated circuit forming step, the assembling step and the like. The chip T has an advantage that it is very easy to attach and detach from the chip mounting surface 52a. Therefore, when the chip transport jig 50 is used in the method of manufacturing a semiconductor device described above, a remarkable effect is obtained. The chip mounting surface 5 of the chip transfer jig 50
The number of chips T mounted on 2a is not limited to one,
You may make it mount multiple pieces.

[0013]

According to the present invention, the disc-shaped wafer subjected to the slicing process is diced into chips, which are the smallest unit of shape, before being transferred to the integrated circuit forming process, and the chips are individually processed into the integrated circuit forming process. Since it is transferred to, the following remarkable effects are achieved. That is, [1]
Since the dicing is performed before the semiconductor element is formed, it is not necessary to spend a great amount of money and time for cleaning the chip unlike the case where the dicing is performed after the semiconductor element is formed. [2] Since the transportation and manufacturing control for each individual element are adopted, the manufacturing line can be simplified easily.
In particular, the semiconductor device centering on DRAM has a relatively large element area up to 1 Gbit and 4 Gbit even if high integration is achieved, so that the method of the present invention is remarkably effective. [3] When dicing is performed after the semiconductor element is formed,
The impact of the dicing process has a high probability of damaging the semiconductor element, which has been a cause of lowering the product yield and increasing the manufacturing cost, but since the present invention performs dicing before forming the semiconductor element. , The probability of causing damage after forming a semiconductor element is extremely small,
It is possible to improve the product yield and reduce the manufacturing cost. In particular, a semiconductor device centering on a DRAM consumes a great deal of cost and time in an element forming process, and is remarkably effective for a semiconductor device completed through such a process.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a flow chart showing a chip manufacturing process of a semiconductor device manufacturing method according to an embodiment of the present invention.

FIG. 3 is an explanatory diagram of an ingot manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of a wafer manufacturing process of the method for manufacturing the semiconductor device according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of a dicing process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is an enlarged cross-sectional view of a main part of a semiconductor device manufactured in an integrated circuit forming step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a flow chart showing an integrated circuit forming process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a flow chart showing an assembling process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view of the semiconductor device manufactured in the assembling process of the method for manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 10 is a sectional view of a chip carrying jig according to an embodiment of the present invention.

FIG. 11 is a flowchart showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

1: chip manufacturing process, 2: integrated circuit forming process, 3: assembly process, T: chip.

Claims (4)

[Claims] 1. A semiconductor device comprising: a chip manufacturing process for manufacturing a semiconductor device chip from a wafer; and an integrated circuit forming process for forming an integrated circuit on the chip after the chip manufacturing process. Production method. 2. The chip manufacturing process includes an ingot manufacturing process for forming a single crystal ingot, a wafer manufacturing process for slicing the ingot manufactured in the ingot manufacturing process to manufacture a disk-shaped wafer, and the wafer. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a dicing process of dicing the wafer manufactured in the manufacturing process to manufacture chips for the semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the diced chip is thinned before the integrated circuit forming step. 4. A holding part having a hollow part inside and a chip mounting surface on which a chip for a semiconductor device is mounted, and a pipe shape projecting from the holding part and communicating with the hollow part. Decompression port, a valve provided in the middle of the decompression port for opening and closing the hollow portion with respect to the outside air, and a plurality of adsorption holes provided on the chip mounting surface of the holding portion and communicating with the hollow portion. Then, by depressurizing the hollow portion via the depressurizing port, the chip is adsorbed to the chip mounting surface via the adsorption hole.