JPH07319826A - Multi-processor system - Google Patents

Abstract

PURPOSE:To execute request arbitration having high throughput without forming a gap between requests. CONSTITUTION:A priority determining circuit in a multi-processor system receives requests from respective processors and arbitrates the competition of these requests. The requests from respective processors are inputted to a fixed priority circuit 420 through a selector 410. The circuit 420 selects only one request and the selected result is stored in an output register 430. The stored request is detected by an AND circuit 450 and the detected result is stored in a holding register 440. When the request stored in the register 440 exists, a succeeding request is not selected by the selector 410. On the other hand, plural fixed priority circuits 420 in the multi-processor system can determine mutually different priority values in accordance with the using situation of the system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to a multiprocessor system including a priority determining circuit that arbitrates requests from each processor.

[0002]

2. Description of the Related Art In a multiprocessor system, it becomes necessary to send a request from a plurality of processors to a plurality of memory modules or between a plurality of processors. For example, in the multiprocessor system of FIG. 1, the priority determination circuits 401 to 404 output to the output port a signal in which any one of the request signals from the four input ports is selected. As a result, any one of the four requests is selected by the selectors 501 to 504. In this case, various methods have been conventionally proposed for arbitrating each request in the priority determination circuits 401 to 404.

The most primitive one is a fixed priority method in which a fixed priority is given to an input port and arbitration is always performed according to this priority. In this fixed priority method, a particular input port is always preferentially treated, and there is a problem that the throughput of the entire system is not improved. In this case, for example, a fixed priority circuit as shown in FIG. 6 is used.

Further, there is a round robin method as a method for cyclically changing the priority of each input port. According to this round robin method, there is a problem that the amount of hardware increases due to the circuit for changing the priority. More seriously, there is a problem that requests are frequently overtaken for multiple requests.

In order to solve these problems, for example,
U.S. Pat. No. 4,991,084 describes a technique for confirming that all the requests that have been accepted once have been output and then accepting the next request so that overtaking of requests does not occur. ing. That is, referring to FIG. 7, each of the priority determination circuits 401 to 404 in FIG. 1 includes a register 930 that holds the input request group and this register 9
A NOR gate 960 that detects that there is a request that has not been output, a fixed priority arbitration circuit 920 that arbitrates each request by giving a fixed priority, and that there are no remaining requests. NOR gate 96
When it is detected by 0, it has a logical product gate 950 which fetches a new request group from the input port. The request held in the register 930 is reset when it is output after being arbitrated. This prevents subsequent requests from entering register 930 until all of the simultaneously held requests have been output. That is, overtaking does not occur between requests that occur at different timings.

[0006]

However, the above-mentioned conventional technique has the following problems.

Referring to FIGS. 7 and 8, if a request is issued at port 1 and port 3 at time T1, the request signal is sent to register 93 at the next T2.
It is held at 0. Then, the request of the port 1 is selected by the fixed priority arbitration circuit 920, and “1” is output only to the output port 1 and “0” is output to the other ports. Therefore, the request from the port 3 is held and output at the next T3.

When a request from the port 3 is output at T3, all the values in the register 930 become "0". Therefore, the outputs at T4 are all "0". The NOR gate 960 informs the logical product 950 accordingly. As a result, the request of port 2 input from T2 is fetched in the register 930 at T5 and output without conflict.

Considering this operation, even though the request from port 2 was input from T2, T4
So no request has been issued. The cause is
It is based on the value of the register 930 to determine whether to receive the subsequent request.

Another problem is that, in each of the priority determining circuits 401 to 404, the fixed priority circuit 920 is set to follow the same priority order. That is, the priority determination circuits 401 to 40
By preferentially treating a specific input port in all four, an imbalance occurs in the processing of requests. Therefore, there arises a problem that the performance of the entire system is not improved.

An object of the present invention is to solve the above problems and perform request arbitration with high throughput without leaving a gap between requests.

Another object of the present invention is to perform request arbitration so that requests from each input port are processed as evenly as possible.

[0013]

In order to solve the above problems, a multiprocessor system of the present invention provides a plurality of processors, a plurality of ports to which requests from the processors are output, and a request from the processors. A multiprocessor system having a plurality of priority determining circuits arbitrating for a plurality of ports, wherein each of the plurality of priority determining circuits selects a request from the processor according to a fixed priority. A priority circuit, a holding circuit that detects a request that is not selected by the fixed priority circuit and holds the detection result, and a new request that is held in the holding circuit, receives a new request from the processor. Including with no selector.

Further, in another multiprocessor system of the present invention, the holding circuit detects a request which is held without being selected by the fixed priority circuit.
Further includes a detection circuit of No. 3, a holding register that holds the result detected by the first detection circuit, and a second detection circuit that detects that there is a request remaining in the holding register.

Further, in another multiprocessor system of the present invention, the selector selects the output of the holding register when the second detection circuit determines that a request remains in the holding register. Then
When the second detection circuit determines that no request remains in the holding register, a new request from the processor is selected.

Further, in another multiprocessor system of the present invention, each of the fixed priority circuits of the plurality of priority determination circuits selects one of the requests from the processors in accordance with the same fixed priority order. To do.

Further, in another multiprocessor system of the present invention, each of the fixed priority circuits of the plurality of priority determination circuits selects one of requests from the processor according to a fixed priority order different from each other. .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the multiprocessor system of the present invention will now be described in detail with reference to the drawings.

Referring to FIG. 1, a multiprocessor system to which the present invention is applied has four processors 101 to 101.
104 and the respective input buffers 201-204,
Decoder 30 that decodes each destination address
1 to 304, priority determining circuits 401 to 404 for arbitrating contention in the output port, and priority determining circuits 401 to
It has selectors 501 to 504 for selecting requests from the input buffers 201 to 204 according to the output of 404. The requests from the four processors 101 to 104 are input to the input buffers 201 to 204 together with the destination addresses. Then, each destination address is decoded by the decoders 301 to 304, and as a request signal, the priority determination circuit 401 of each destination.
To 404. Priority decision circuits 401-404
On the basis of the request signals given to the input ports by the decoders 301 to 304, one request is selected and given to the corresponding selectors 501 to 504 as a control signal. The selectors 501 to 504 output the requests from the input buffers 201 to 204 according to the control signals from the priority determination circuits 401 to 404.
The output results of the selectors 501 to 504 may be connected to the memory module or the processor.

The processors 101 to 104 send memory access requests and data transfer requests to other processors to the corresponding input buffers 201 to 204.
Output to. The input buffers 201 to 204 are configured as first-in first-out buffers. Therefore, the requests held at the beginning are sequentially output. When the preceding request is suspended, the subsequent request waits in the input buffers 201 to 204.

The decoders 301 to 304 decode the 2-bit destination address into 4-bit. The decoded signals are input to the priority determining circuits 401 to 404 of the corresponding output ports one by one.

The selectors 501 to 504 are 4-input 1-output selectors. It has a bit width corresponding to the bit width of the requests from the input buffers 201 to 204.

Referring to FIG. 2, the priority determination circuit 401
To 404 are the selector 410 and the selector 4
Fixed priority circuit 420 for arbitrating the output result of 10 and output register 43 for holding the output of fixed priority circuit 420
0, a logical product circuit 450 that detects a request pending by the fixed priority circuit 420, a pending register 440 that holds the output of the logical product circuit 450, and a pending register 4
40 and a logical sum circuit 460 for detecting whether or not a request is held.

Here, the description will be made by using the symbols such as "selector 410", but when the configuration in a specific priority determining circuit is limitedly referred to, it is specified by the lowest number. . For example, when specifying the selector 410 in the priority determination circuit 401, the “selector 411” is set.

One of the inputs of the selector 410 is a 4-bit request signal from the decoders 301 to 304, and the other is a 4-bit output of the holding register 440. Which input is output is determined by the output of the OR circuit 460. That is, the holding register 440
If at least 1 bit of the OR is "1", the OR circuit 46
The output of 0 becomes "1", and in this case, the holding register 4
The value of 40 is output from the selector 410. On the other hand, if all the bits of the holding register 440 are “0”, the output of the OR circuit 460 is “0”, and in this case, the requests from the decoders 301 to 304 are output from the selector 410.

The fixed priority circuit 420 arbitrates so that at most 1 bit of the 4-bit output of the selector 410 becomes "1". That is, when all the bits of the input data are “0” or only one bit is “1”, the input data is output as it is. When a plurality of bits are "1" in the input data, only one of the bits that is "1" is selected and all other bits are set to "0". An example of such a fixed priority circuit is given, for example, by FIG. In FIG. 6, the upper bit is selected preferentially.
In other words, [011
When the data [0] is given, the third bit "1" is masked by the AND circuit, and the data [0100] is output.

The output register 430 holds the result arbitrated by the fixed priority circuit 420 as described above. The outputs of the output registers 431 to 434 are used as control signals of the selectors 501 to 504, respectively.

The logical product circuit 450 is a fixed priority circuit 420.
Detects requests pending by. That is,
Inversion signal of output of fixed priority circuit 420 and fixed priority circuit 4
The request signal left unselected is output by taking the logical product of 20 input signals.

The output of the AND circuit 450 is held in the hold register 440 and can be arbitrated in the next cycle. That is, at least one of the holding registers 440
If the bit is "1", the output of the holding register 440 is selected by the selector 410, so that the subsequent request is not accepted and the held request is preferentially processed.

It will be shown below that one of the problems of the prior art is solved by such a configuration.

Referring to FIGS. 2 and 3, the request value [1 [1] input to the selector 410 at time T1.
010] means that there is a request at the first port and the third port. Assuming that the contents of the hold register 440 are all "0", the request at T1 is selected by the selector 410. In the fixed priority circuit 420, the first port> the second port> the third port>
Assuming that the higher priority is set in the order of the fourth port, the first port is selected, and the value [1000] is set in the output register 430 and the holding register 440 is set at T2.
Holds the value [0010].

At this time, since the output of the hold register 440 includes "1", the value of the hold register 440 is selected by the selector 410. In this case, since the value of the holding register is [0010], at T3,
[0010] is held in the output register 430 by the holding register 4.
40 holds [0000].

At this time, the holding register 440 is set to [0
000], the input request is selected in T3. Therefore, at T4, the subsequent request [0100] is held in the output register 430.

Comparing the arbitration timing according to the embodiment of the present invention shown in FIG. 3 with the prior art shown in FIG.
In the prior art, the output at T4 is [0000], and there is a vacancy in issuing a request for one cycle, whereas in the present invention, the subsequent request [0100] is issued at T4. The cause of this is that in the prior art, the judgment is made based on the result held in the register 930. On the other hand, in the present invention, the holding register 440
Since the determination is made based on the remaining request, it is possible to arbitrate the remaining request and select the next request that can be issued.

Next, another feature of the priority determining circuit in the multiprocessor system of the present invention will be described.

In the priority determination circuits 401 to 404 of the multiprocessor system shown in FIG. 1, the fixed priority circuits 421 to 424 shown in FIG. 2 can set the priority independently for each priority determination circuit. For example, as an example, it is conceivable that, for all of the fixed priority circuits 421 to 424, as in the circuit of FIG. 6, a high priority is set in the order of first port> second port> third port> fourth port. . Also,
As another example, the fixed priority circuit 421 has a first port>
A high priority is set in the order of second port> third port> fourth port, and a high priority is set in the fixed priority circuit 422 in the order of second port> third port> fourth port> first port and fixed. The priority circuit 423 defines a high priority in the order of third port> fourth port> first port> second port, and the fixed priority circuit 424 includes fourth port> first port> second.
It is also possible to set a high priority in the order of port> third port. Particularly, according to the latter method (hereinafter, referred to as “fixed cyclic assignment”), it is possible to impart a fairer priority to each input port.

First, with reference to FIG. 4, an operation in the case where a high priority is set in the order of first port> second port> third port> fourth port for all the fixed priority circuits 421 to 424 will be described. . In FIG. 4, for example, "C [3
“→ 1]” represents “request C output from the third processor 103 to the first output destination 601”.
Further, in each input, the signal in the first stage represents a request from the processor. The signal in the second stage represents the request held at the head of the input buffer. The signal in the third row represents the request held second from the head of the input buffer.

At time T1, when the request A is input from the first processor, the request B is input from the second processor, the request C is input from the third processor, and the request D is input from the fourth processor, request A and request C are input. Have the same first output destination, contention occurs, and both requests are arbitrated in the priority determination circuit 401. Here, since the input from the first port has a higher priority, the request A is output to the first output destination 601 at T2. The request C is temporarily held in the input buffer 203 and output at T3 with a delay of one cycle.

At time T2, request E and request F compete for each other at the second port, and request E from the first port is prioritized and output at T3. The request F is once held in the input buffer 202 and is output at T4 with a delay of one cycle. Further, since the request C is held at the head of the input buffer 203 at the third port of the input ports, the request G is not an output target and is held at the head of the input buffer 203 at T3.

At time T3, the request I from the first port and the request G from the input buffer 203 of the third port
Compete with each other at the third port, and the request I from the first port has priority. Request G is input buffer 2
It is kept held at 03 and output at T5. Since this request G is held in the input buffer 203, the request K is not an output target, and is held second at the beginning of the input buffer 203 at T4.

At time T4, the request M from the first port and the request J from the input buffer 202 of the second port.
Compete with each other at the fourth port, and the request M from the first port is prioritized. Request J is input buffer 2
It is kept held at 02 and is output at T6.

In this way, each request is sequentially output, and all the requests A to P are output at time T7.

Next, with reference to FIG. 5, the operation when the priority is determined by the fixed cyclic allocation described above will be described.

At time T1, the request A is input from the first processor, the request B is input from the second processor, the request C is input from the third processor, and the request D is input from the fourth processor. The same first port as the output port,
Contention occurs, and both requests are arbitrated in the priority determination circuit 401. Here, since the input from the first port has a higher priority, the request A is output to the first output destination 601 at T2. The request C is temporarily held in the input buffer 203 and is delayed by one cycle to T3.
Is output with.

At time T2, request E and request F compete for each other at the second port. In the fixed cyclic allocation, in the second port of the output ports, the second port of the input ports has a higher priority than the first port, so the request F from the second port is prioritized and output at T3. It The request E is temporarily held in the input buffer 201 and output at T4 with a delay of one cycle. Also,
Since the request C is held at the head of the input buffer 203 at the third port of the input ports, the request G is not an output target and is held at the head of the input buffer 203 at T3.

At time T3, since the request E is held at the head of the input buffer 201 in the first port of the input ports, the request I is not output. Therefore, at this time T3, no competition occurs between the requests.

Similarly, at time T4, the request I is not output because the request I is held at the head of the input buffer 201 in the first port of the input ports. Therefore, even at this time T4, no competition occurs between the requests.

In this way, each request is sequentially output, and at time T6, all the requests A to P are output.

Here, comparing FIG. 4 with FIG. 5, fixed priority circuits 421 to 424 of the priority determination circuits 401 to 404 are shown.
It can be understood that the performance of the entire system is improved in FIG. 5 in which the priorities are set by the fixed cyclic allocation, as compared with FIG. 4 in which all the priorities are set as the same. However, it should be noted that in this example, relatively even requests occur. When the number of requests from the first port of the input ports is extremely large, the fixed priority circuit 42
Higher performance may be exhibited if the priority levels 1 to 424 are all set to be the same.

As described above, according to the multiprocessor system according to the embodiment of the present invention, the request left unselected by the fixed priority circuit 420 is retained in the holding register 4.
By holding in 40, the pending request can be processed with priority. Further, by adopting the fixed cyclic allocation method in the fixed priority circuit 420, the priority can be imparted to each input port fairly.

[0051]

As is apparent from the above description, according to the present invention, it is possible to arbitrate so that requests can be output without a gap. Further, by arbitrating the requests from each processor evenly, there is an effect that the performance of the entire system is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiprocessor system of the present invention.

FIG. 2 is a diagram showing a configuration of a priority determination circuit according to an embodiment of the present invention.

FIG. 3 is a diagram showing timing of request arbitration according to an embodiment of a priority determination circuit in an embodiment of the present invention.

FIG. 4 is a time chart showing an example of processing by an embodiment of the priority determination circuit of the present invention.

FIG. 5 is a time chart showing another example of processing by an embodiment of the priority determination circuit of the present invention.

FIG. 6 is a diagram illustrating an example of an arbitration circuit with fixed priority.

FIG. 7 is a diagram showing a priority determination circuit according to a conventional technique.

FIG. 8 is a diagram showing a timing of request arbitration according to a conventional technique.

[Explanation of symbols]

 101-104 processor 201-204 input buffer 301-304 decoder 401-404 priority determination circuit 410 selector 420 fixed priority circuit 430 output register 440 hold register 450 logical product circuit 460 logical sum circuit 501-504 selector

Claims (5)

[Claims] 1. A multiprocessor system comprising: a plurality of processors; a plurality of ports to which requests from the processors are output; and a plurality of priority determining circuits that arbitrate requests from the processors for the plurality of ports. , Each of the plurality of priority determination circuits detects a fixed priority circuit that selects one of the requests from the processor according to a fixed priority order and a request that is not selected by the fixed priority circuit and is held. A multiprocessor system comprising: a holding circuit that holds the detection result; and a selector that does not receive a new request from the processor when there is a pending request in the holding circuit. 2. The first holding circuit detects a request that is held without being selected by the fixed priority circuit.
Detection circuit, a holding register that holds the result detected by the first detection circuit, and a second detection circuit that detects that there is a request remaining in the holding register. The multiprocessor system according to claim 1. 3. The selector selects the output of the holding register when the second detection circuit determines that a request remains in the holding register,
3. The multiprocessor system according to claim 2, wherein a new request from the processor is selected when the second detection circuit determines that there is no request left in the holding register. 4. The fixed priority circuit of each of the plurality of priority determination circuits selects one of requests from the processor in accordance with the same fixed priority order. Multiprocessor system. 5. The fixed priority circuit of each of the plurality of priority determination circuits selects one of requests from the processor in accordance with a fixed priority order different from each other. Multiprocessor system.