JPH07319736A - Controller - Google Patents

Abstract

PURPOSE:To suppress the production of a control signal even if the producing conditions of this signal are satisfied in a rewrite mode and to prevent the malfunctions of a controller by asserting a mask signal when the value is set to one of plural registers and counters containing a loading function. CONSTITUTION:A signal LE1 is asserted and then negated when '0000h' is set at a counter 1. At the same time, a mask signal generating circuit 3 asserts a signal MASK, and a signal LE2 is asserted and then negated when '0100h' is set at a counter 2. At the same time, the circuit 3 negates the signal MASK. Therefore, a control signal generating circuit 4 can assert a signal CTRL. Under such conditions, the value of a 32-bit counter consisting of both counters 1 and 2 is equal to '0000h' and '0100h', and the signal CTRL is not asserted. As a result, the control signal that is wrongly produced while the value is set at each of plural counters containing the loading functions, is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device, and more particularly, to a plurality of registers or one or more registers and one or more load function counters or a plurality of load function counters, and the plurality of registers. Alternatively, the present invention relates to a control device that generates a control signal when the values of one or more registers and one or more load function counters or a plurality of load function counters reach preset values.

[0002]

2. Description of the Related Art A conventional control device inputs a value output from a register or a counter to a control signal output circuit, and the control signal output circuit generates a control signal when the input value satisfies a preset condition. It was something to do. For example, the control device disclosed in Japanese Patent Laid-Open No. 3-3041 is
The control signal is generated when the count value of the counter is compared with the value of the counter or the value of the register for storing the initial setting value and both values match.

[0003]

However, in the one disclosed in the above publication, when the number of bits of the register is larger than the bus width of the register data bus, for example, the number of registers is 16
If the register value is a bit register and the register data bus is 8 bits, and the value of the register is rewritten while the counter is operating, the value stored in the register and the value to be rewritten are in the process of rewriting. Therefore, the register value and the counter value may temporarily become equal to each other. At this time, although the control device should not generate the control signal, the control device generates the control signal and causes a malfunction.

The present invention has been made to solve the above-mentioned problems and is a control for preventing malfunction by preventing the control signal from being generated even if a condition for generating the control signal is satisfied during rewriting. The purpose is to provide a device.

[0005]

In order to solve the above problems, the present invention provides a mask signal generating circuit for a plurality of registers or one or more registers and one or more counters with a load function or a plurality of loads. When the setting of the value to any one of the functional counters is started, the mask signal is asserted to prohibit the generation of the control signal, and a plurality of registers or one or more registers and one or more registers are provided. When the setting of all values of the load function counter or the plurality of load function counters is completed, the mask signal is negated so that the control signal can be generated when the condition is satisfied.

[0006]

According to the present invention, the mask signal is asserted until the setting of the values to all of the plurality of registers or one or more registers and the one or more load function counters or the plurality of load function counters is completed. Since the control signals are masked by the above, the values are temporarily mistaken while setting the values in the above-mentioned plurality of registers or one or more registers and one or more load function counters or plural load function counters. The generation of control signals is prevented.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of an embodiment of a control device of the present invention. In FIG. 1, a counter 1 and a counter 2 are n-bit (n is a natural number) counter with a load function, and the counter 1 loads data on the data bus LD when a signal LE1 and a signal LE2 are asserted. . Further, the counter 1 and the counter 2 constitute one 2n-bit counter. The counter 1 counts in synchronization with the clock signal CLK when the signal CE and the counter 2 when the carry signal CRY from the counter 1 is asserted. Take action. When the signal MASK is not asserted, the control signal generation circuit 4 uses the counter 1
When the control signal CTRL is activated while the value of the 2n-bit counter constituted by the counter 2 and the counter 2 is equal to a predetermined value and the signal MASK is asserted, the counter 1
Is a circuit that makes the signal CTRL inactive regardless of the value of the 2n-bit counter configured by the counter 2 and the counter 2. The mask signal generation circuit 3 asserts either the signal LE1 or the signal LE2 from the start of the write access to either the counter 1 or the counter 2 until the end of the write access to the other one. It is a circuit that asserts the signal MASK after the other one is negated. Further, the data bus LD is an input data bus for setting a value in the counter 1 or the counter 2 from outside the control device, and a signal LE1.
And signal LE2 are exclusively active, load enable signals for counter 1 and counter 2, signal C
E is a count enable signal of the 2n-bit counter composed of the counter 1 and the counter 2, and the signal CLK.
Is a clock signal, and the signal CTRL is a control signal to a device to be controlled by this control device.

In the following, as an example, the counter 1 and the counter 2 are 16-bit counters, and the control signal generation circuit 4 has a value of the counter 1 of 0000h and a counter 2 of 2.
Is FFFFh, that is, the value of the 32-bit counter configured by the counter 1 and the counter 2 is 000.
The control signal CTRL is activated when 0 and FFFFh are set. When both the values of the counter 1 and the counter 2 are FFFFh, the counter 1 is set to 0000.
h, counter 2 to 0100h counter 1, counter 2
The operation of the control device of the present invention when resetting is performed in the order of.

In the above case, first, the signal LE1 is asserted, the counter 1 is set to 0000h, and when the setting is completed, the signal LE1 is negated. At this time, the mask signal generation circuit 3 asserts the signal MASK because the signal LE1 is asserted. When the counter 1 is set to 0000h, the value of the 32-bit counter configured by the counter 1 and the counter 2 becomes 0000 and FFFFh until the counter 2 is reset.
Since K is asserted, the control signal generation circuit 4 does not assert the signal CTRL. Next, the signal LE2 is asserted, the counter 2 is set to 0100h, and when the setting is completed, the signal LE2 is negated. At this time, the mask signal generation circuit 3 negates the signal MASK because the signal LE2 is asserted and negated after the signal LE1 is asserted and negated. Since the signal MASK is negated, the control signal generation circuit 4 outputs the signal CTR.
Although the L can be asserted, the value of the 32-bit counter constituted by the counter 1 and the counter 2 at this time is 0000,0100h, so that the signal CTR is used.
L is not asserted. That is, as described above, it is possible to prevent a control signal from being erroneously generated temporarily while setting values in the plurality of load function counters.

In the above embodiment, two counters are operated as one counter. However, even when three or more counters are operated as one counter, the counters are set in the same manner as above. It is easily inferred that it is possible to prevent a control signal from being erroneously generated temporarily while setting the. Needless to say, the same is true even if some or all of the plurality of counters are replaced with registers.

[0011]

As described above, according to the present invention,
When resetting the values of the plurality of registers or the counter with the load function, the mask signal is asserted when the setting of the value in any one of the plurality of registers or the counter with the load function is started. , The mask signal is negated when the values of all the registers or the counters with the load function have been set. The control signal is not generated even when the value becomes a value that should be generated. Therefore, it is possible to prevent the malfunction of the device to be controlled by the present control device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

[Explanation of symbols]

1, 2 ... Counter, 3 ... Mask signal generation circuit, 4 ... Control signal generation circuit, LD ... Register data bus, LE1 ... Load enable signal of counter 1, LE2 ... Counter 2
Load enable signal, CRY ... Carry signal for operating counter 1 and counter 2 as one counter, CLK ... Clock signal, CE ... Count enable signal of counter constituted by counter 1 and counter 2, CD1 ... Counter 1 Output data bus, CD2 ... Counter 2 output data bus, MASK ...
Mask signal, CTRL ... Control signal.

Claims (1)

[Claims] 1. When the values of a plurality of registers or one or more registers and one or more load function counters or a plurality of load function counters are input and the input values are preset values. A control signal generating circuit for generating a control signal, and a mask signal generating circuit for generating a signal for masking the control signal to the control signal generating circuit, and the plurality of registers or one or more registers and one When the setting of a value to any one of the above load function counter or a plurality of load function counters is started, the control signal generating circuit asserts a mask signal to generate a control signal. Ban,
A control device which negates a mask signal when setting of all values of a plurality of registers or one or more registers and one or more load function counters or a plurality of load function counters is completed.