JPH07319671A - Preprocessing method for division or residue and preprocessor for division or residue - Google Patents

Abstract

PURPOSE:To accurately perform preprocessing for division and residue as to a negative number fast. CONSTITUTION:In the processing which normalizes data on a division object or residue object consisting of a sign bit and numeric bits following it when the data is a plus number, or normalizes complement data of 2 when a minus number, the number of bits of leading '1' of each data or the number of bits of leading '0' of its complement data of 1 is found when the data is minus and whether or not there are successive bits '10' in the bit sequence or whether or not there are successive bits '10' in the bit sequence of the its complement data of 1 is detected, and, a control signal for (negative number) normalization generated on the basis of the number of bits is made different by '1' between the case wherein there are the successive bits and a case wherein there are not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention normalizes each piece of data to be divided or modulo consisting of a sign bit and a numerical bit following the sign bit when the data is a positive number, and a negative number. In this case, the present invention relates to a division or remainder preprocessing method for normalizing the 2's complement data and a preprocessing apparatus therefor. In the following description, preprocessing for division will be described, but this is to omit the description “division or remainder” each time, and the description of the present invention will be given below. It goes without saying that the contents obtained by replacing the “division” part with the “remainder” are also covered by the present invention.

Generally, when a dividend and a divisor are divided from a sign bit and a numerical bit following the sign bit, when the dividend is a negative number, a preprocessing such as first converting to a two's complement and then normalizing is performed. However, there has been a demand for simplification and speedup of this pretreatment, and the present invention responds to such demand.

[0003]

2. Description of the Related Art FIGS. 5 to 8 are explanatory views of general pre-division processing, and FIG. 5 shows data (16 bits) indicating a dividend and a divisor to be divided and an expression when each is normalized. The format is shown in FIG. 6, the procedure for normalizing the dividend and the divisor, and FIGS. 7 and 8 are block diagrams of the pre-division processing.

As shown in FIG. 5, the division target data itself has a positive and negative sign in its most significant bit (MSB).
In addition, it has a fixed decimal point format in which the subsequent numerical bits indicate, for example, an integer value.

When normalizing a positive number, firstly, the number of bits of the leading "0" of the data to be divided is counted. Then, from "15 (bit width of numerical value bit portion)", this count is performed. Obtain the shift data (decimal point movement data) from which the value has been subtracted, and then use this shift data to perform a series of processing such as moving the decimal point of the division target data and setting the exponent value accordingly. .

For example, for the binary number "0000000010001110" of "142" in the case of (a), first, the number of bits "8" of the leading "0" is counted, and then the shift data “7 (= 15−8)” is calculated, and then, using this value “7”, the initial binary number “0000” is obtained.
"0000101110" to "1.000111 x 2
⁷ ".

Further, when normalizing a negative number, the same processing as in the case of a positive number is performed on the 2's complement of the data to be divided. For example, in the case of (c), the binary number of "-142" is "1".
111111101110010 ": First, the complement of 1 is" 00000000100 ".
"01101" is calculated, and then "1" is added to this binary number to obtain "000000."
0010001110 ", and then performs the same processing as in the case of a positive number on this complement data to obtain the initial binary number" 1111111101 ".
110010 "is converted into the form of" -1.000111 × 2 ⁷ ".

FIG. 6 is an explanatory view showing the procedure of the pre-division processing, and its contents are as follows. It is determined whether the most significant bit of the division target data (dividend and divisor) is "1". If "YES", the process proceeds to the next step, and if "NO", the process proceeds to step.
In the case of "YES", when the division target data is a negative number,
In the case of "NO", the division target data is a positive number. The one's complement of this division target data is obtained, and the process proceeds to the next step. The complemented data is incremented by "+1" to obtain the 2's complement of the division target data,
Go to the next step. The division target data itself (when it is a positive number) or the complement data obtained at the step (when it is a negative number) is held in the register, and the process proceeds to the next step. The number of bits of the leading "0" of the held data is counted, and the process proceeds to the next step. The normalization process is executed based on this count value.

FIG. 7 is a block diagram of the pre-division processing described above. Reference numeral 31 is a 2's complement circuit for the data to be divided.
Is a gate circuit for selecting one of division target data, 2's complement data and normalization data, and 33 is this gate circuit.
Register holding the output of 32, 34 is a reading "0"
A detection circuit, a normalization control signal (a signal indicating an exponent value, a decimal point moving digit number, etc.) 35, a register 36 for holding the calculated value, and a normalization circuit 37.

This circuit block is provided for each of the dividend and the divisor. For example, in the case of (a): First, either the division target data or the two's complement data is gated. 32. Then, this is held in the register 33. Then, the reading "0" of this holding data is detected by the detection circuit 34. Then, the bit of this reading "0" is detected. A normalization control signal such as an exponent value based on a number is obtained by the setting circuit 35. Then, this is held in the register 36. Then, a normalization process based on the held content, that is, the number of the dividend or divisor is small. The point position is moved and the exponent is set. Then, this normalized data is selected by the gate circuit 32 and held in the register 33. Next, this normalized data is taken out from the register 33. And send it to the division unit.

In the case of (b), either the division target data selected by the gate circuit 32 or the two's complement data is not held in the register 33 and its leading "0" is stored. Is detected, it is possible to reduce the processing time by the timing of this holding as compared with the case of (a).

FIG. 8 shows a specific example of the gate circuit 32. An AND gate 41 for selecting data to be divided and an AND gate 42 for selecting 2's complement data and normalization data. It consists of an AND gate 43 for selecting.

Where the inversion signal a of the code signal based on the MSB of the two's complement data is "L" and the inversion signal b of the control signal for specifying the extraction timing of the normalized data is "L". When "L", only the AND gate 41 is opened and the division target data is the register.
Held in 33, when the inversion signal a is "H" and the inversion signal b is "L", only the AND gate 42 is opened and the two's complement data is held in the register 33; When b is "H", only the AND gate 43 is opened and the normalization data is held in the register 33.

[0014]

As described above, conventionally, a normalization control signal such as an exponent value required for normalization in the pre-division processing of the division target data of a negative number is set to the 2's complement number of the division target data. That is, since it is generated based on the number of bits of the leading "0" of the complement obtained after executing the two-step processing of obtaining the one's complement and incrementing it by "1", the execution time of the pre-division processing There was a problem that it became longer.

Therefore, according to the present invention, the normalization control signal of the data to be divided by a negative number is incremented by "1" to the 1's complement data of the data to be divided to obtain the 2's complement. Of the division target data itself or its 1's complement data, and when the least significant bit of the leading "0" portion is inverted to "1" with the increment, this is It is an object of the present invention to enable correct and high-speed pre-division processing for negative numbers by reflecting it in the generation process.

[0016]

FIG. 1 is a diagram for explaining the principle of the present invention. In the figure, 1 and 2 are processes similar to the conventional process for positive numbers, 3 to 9 are processes for negative numbers, and 10 is a process for both positive numbers and negative numbers. .

That is, 1 is a process for detecting the number of bits of the leading "0" for the dividend x or the divisor y, and 2 is a normalization control signal (exponent value or decimal point moving digit) based on this bit number. (A signal indicating a number) (see FIG. 5), 3 is a process for obtaining the complement of “1” for the dividend x or the divisor y, and 4 is for incrementing this complement data by “1”. And 5 to detect the number of bits of the leading "1" for the dividend x or the divisor y, and 6 is "01" for the bit string of the dividend x or the divisor y. Is a process for checking whether there is a continuous bit of "," 7 is a process for detecting the number of bits of leading "0" of the complement data obtained in the process of 3, and 8
Is "10" in the bit string of the complement data obtained by the process of 3.
Is a process for checking whether or not there are consecutive bits, and 9 generates a normalization control signal (a signal indicating an exponent value, the number of decimal places to move, etc.) based on the number of bits obtained in the process of 5 or 7. (Refer to FIG. 5), and when the inversion is detected in the processing of 6 or 8, adjustment is performed by "1" in this generation, for example, processing in which a value obtained by subtracting "1" from the number of bits is used. Yes, 10 is a process of normalizing the dividend x and the divisor y based on the normalization control signal obtained in the process of 2 or 9.

Here, the presence or absence of the consecutive bits of "01" is checked in the case of a negative number, at the stage before the increment of the complement of the "1" is executed, the leading "1" or the "1" is read. This is because the bit number of the leading "0" of the complement of "1" is obtained, and this bit number may not match that of the leading "0" of the data after the increment.

That is, as shown in FIG. 2 (b), when only a "0" bit follows a negative reading "1", or when all the negative bits are "1", When the complement of "1" is incremented by "1", the least significant bit of the leading "0" of the complement changes to "1" because of a carry. For example, in the case of "-126 (decimal)", By the increment, the number of bits of the leading "0" is changed from "9" to "8", and the two do not match.

This discrepancy in the number of bits is corrected based on the result of the check processing of consecutive bits at 6 or 8, which means that there is "01" consecutive bits in the negative bit string or its "1". "" In the complement bit string of
If there are consecutive bits of, the effect of the carry due to the increment stops at this consecutive bit part, but when these consecutive bits do not exist, the least significant bit of the leading "0" of the complement of "1" is carried. The focus is on the disagreement state.

That is, when these consecutive bits are not present, the normalization control signal is set to the original value by adjusting "1" when the normalization control signal is generated in the process of 9. I am trying.

The adjustment method when the exponent value or the number of moving digits of the decimal point is used as the control signal for normalization is as follows:
The subtraction process similar to that of FIG. 5 is executed using the value obtained by subtracting the same value.-The subtraction process similar to that of FIG. 5 is executed using the bit number as it is, and "1" is added to the execution result. The normalization control signal when there is no continuous bit has a value larger by "1" than when there is this continuous bit.

In the case of using the left shift amount in the holding register as the normalization control signal instead of the exponent value or the number of decimal places to move when the negative number is normalized, the same subtraction process as in FIG. 5 is not necessary. The normalization control signal when there is no continuous bit has a value smaller by “1” than when there is this continuous bit.

Further, the present invention is as follows: For each data to be divided consisting of a sign bit and a numerical bit following the sign bit, if the data is a negative number, the 2's complement data is obtained. If each data corresponds to a negative number, the number of bits of the leading "1" or the number of bits of the leading "0" of the complement data of 1 is obtained, and "01" in the bit string is obtained. Data determining means (corresponding to each processing of 5, 6, 7, and 8) for detecting the presence or absence of the consecutive bits of 10 or the presence of consecutive bits of "10" in the bit string of the one's complement data, and these bits. A normalization control signal setting means for generating a normalization control signal having a value different by "1" depending on whether the continuous bit is "present" or "absent" based on the number and the presence or absence of the continuous bit. (Process 9 is (Corresponding) and the data pre-processing device for normalizing the 2's complement data on the basis of the normalization control signal (corresponding to the processing of 10).

[0025]

As described above, according to the present invention, the normalization control signal (exponent value, decimal point moving digit number, etc.) for a negative number to be divided is calculated by the number of bits of the leading "1" of the negative number itself or its "1". The complement of "" is executed based on the number of bits of "0".

Further, in parallel with the calculation of the number of bits, it is determined whether the number of bits of these leading parts matches that of the complement of “2” after incrementing the complement by “1” by the negative number itself or By checking from the continuous bit state of each bit string of the "1" complement, and when the result is "mismatch", by adjusting only "1" in calculating the normalization control signal and setting it to a correct value. , The accuracy of pre-division processing for negative numbers is ensured and the speed is increased.

Further, the combination of the bit number detection and the continuous bit state check is as follows: Detection of the bit number of the leading "1" of the negative number itself and check of the presence or absence of consecutive bits of "01" in the negative number itself "1 Of the leading "0" in the complement of ", and checking for the presence or absence of consecutive bits of" 01 "in the negative number itself-Detection of the number of leading" 1 "bits in the negative number itself,
Check for the presence or absence of "10" consecutive bits in the "1" complement ・ Leading "1" complement detection of the number of "0" bits and the presence or absence of "10" consecutive bits in the "1" complement There are four ways to check, and the first combination is the most efficient with the least time delay for speeding up.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. 3 and 4 are explanatory diagrams showing a block diagram of pre-division processing, and FIG. 5 is an explanatory diagram showing a procedure of pre-division processing. In the following embodiments, for convenience of explanation, the exponent value and the number of moving decimal points will be used as the normalization control signal.

In FIG. 3, 11 is a "01" detection circuit,
12 is the code signal (MSB of the data to be divided) and this "0
1 "and the output signal of the detection circuit 11 is input, 13 is a register that holds the output signal of the AND gate 12, and 14 is the sign signal and the output signal of the 1's complement circuit 19 described later. An AND gate to be input, 15 is an AND gate to which the code signal and the data to be divided are input, 16 is a leading "0" detection circuit to which the output signals of the AND gates 14 and 15 are input, and 17 is this reading A register that holds the output signal of the "0" detection circuit 16, and a setting circuit 19 that generates a normalization control signal (exponent value or decimal point moving digit number) based on the contents of the registers 13 and 17.
Is a 1's complement circuit for division target data, and 20 is an increment circuit for adding "1" to the output signal of the complement circuit 19. In addition, 2 of the data to be divided
The complementing circuit 31, the gate circuit 32, the register 33, and the normalizing circuit 37 of FIG. 7 have the same configurations as those shown in FIG.

Here, the AND gates 12 and 14 are used when the sign bit of the data to be divided is "H" (corresponding to a negative number).
Further, the AND gate 15 is opened when the sign bit of the division target data is "L" (a positive number is equivalent), and the AND gate 15 outputs "1" from the complementation circuit 19 (1 of the division target data). Will be sent to the leading "0" detection circuit 16, and the data to be divided itself will be sent from the AND gate 15 to the leading "0" detection circuit 16.

Further, the "01" detection circuit 11 outputs a signal which becomes "H" when detecting the consecutive bits of "01" as an adjustment flag, which is held in the register 13 at a predetermined timing thereafter. It is sent to the setting circuit 18. In addition,
The output of the AND gate 12 shows "L" for a positive number or a negative number having consecutive bits of "01", and "H" for a negative number having no consecutive bits of "01". .

In the setting circuit 18, for example, an operation similar to that shown in FIG. 5 is executed based on the contents of the register 17 (the number of bits of the leading "0") and the contents of the register 13 (whether there are consecutive bits of "01"). By doing so (subtracting the number of bits from the bit width of the numerical bit portion of the division target data), the normalization control signal necessary for normalizing the division target data is generated.

At the time of this generation, when the "H" adjustment flag is held in the register 13, that is, when the data to be divided is a negative number and there are no consecutive bits of "01" in the bit string, the adjustment method is used. An adjustment process is performed in which the normalization control signal is increased by “1” compared to when the adjustment flag is not held.

The output signal of the setting circuit 18 is sent to the normalization circuit 37, and the normalized data is divided by the operation in the gate circuit 32 and the register 33 in the same manner as in the prior art (see FIGS. 7 and 8). Sent to.

In FIG. 4, instead of detecting the leading "0" in the output signal of the complementing circuit 19 in FIG. 3, the leading "1" in the division target data itself is detected.

As a component corresponding to this, a leading "1" detection circuit 23, an AND gate 24 and an AND gate 26 are provided, and a normalization control signal setting circuit 27 is provided.
A register 28 for holding the output signal of is provided.

Then, including the setting circuit 27, "1" complement circuit 19, increment circuit 20, "01" detection circuit 21, AND gate 22, "2" complement circuit 31, gate circuit 32, register. Each of 33 and the normalization circuit 37 performs the same operation as that shown in FIG.

For example, when the sign bit of the division target data is "H" (a negative number is equivalent), the AND gate 22 and
When only 24 is opened and the sign bit is "L" (a positive number is equivalent), only the AND gate 26 is opened and the normalization processing similar to that shown in FIG. 3 is executed.

In FIGS. 3 and 4, the 2's complementing circuit 31 serves as the complement creating means, and the "01" detecting circuits 11, 21 and AND gates 12, 14, 15,
22, 24, 26 and leading "0" detection circuit 16,25 and leading "1" detection circuit 23 are used as the data judgment means, and normalization control signal setting circuits 18, 27 are used for the normalization control signal setting. The normalizing circuit 37 corresponds to the data normalizing means.

Of course, the register 13 for holding the output signal of the AND gate 12 in FIG. 3 may be omitted, or a register for holding the output signal of the AND gate 22 in FIG. 4 may be provided.

Further, as described at the beginning of the detailed description of the invention, it goes without saying that the contents described so far by taking the case of division as an example can be directly applied to the preprocessing of the remainder.

[0042]

As described above, according to the present invention, a control signal (exponent value, etc.) for normalizing target data of a negative number for division or remainder.
Is generated from the data before the one's complement data of this target data is incremented by "1" to be the two's complement, that is, the target data itself or its one's complement data, Further, when the least significant bit of the leading "0" portion up to that time is inverted to "1" with the increment, this is reflected in the generation process, so the normalization processing for the target data is performed with a negative number. It can also be done accurately and fast.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a negative reading "1" and its 1 according to the present invention.
FIG. 6 is an explanatory diagram showing the relationship between the number of bits of the leading “0” of the complement of and the number of bits of the leading “0” of the two's complement.

FIG. 3 is an explanatory diagram (No. 1) showing a block diagram of pre-division processing of the present invention.

FIG. 4 is an explanatory diagram (part 2) showing a block diagram of pre-division processing of the present invention.

FIG. 5 is an explanatory diagram showing a general expression of a dividend and a divisor (2-byte data) and their normalized expressions.

FIG. 6 is an explanatory diagram showing a conventional procedure of pre-division processing.

FIG. 7 is an explanatory diagram showing a block diagram of conventional division preprocessing.

8 is an explanatory diagram showing a specific example of the gate circuit in FIG. 7. FIG.

[Explanation of symbols]

In FIG. 1, 1 ... Process for detecting the number of leading "0" bits of division target data 2 ... Process for generating normalization control signal 3 ... Process for obtaining 1's complement of division target data 4 ... Process of incrementing by "1" and converting to 2's complement data 5 ... Process of detecting bit number of leading "1" of division target data 6 ... "01" in division target data Process for checking presence / absence of consecutive bits of 7 ... Process for detecting bit number of leading "0" of 1's complement data 8 ... Process for examining presence / absence of consecutive bits of "10" in 1's complement data 9 ... Process for generating normalization control signal 10 ... Process for normalizing division target data based on the normalization control signal

Claims (6)

[Claims] 1. Data for division or remainder consisting of a sign bit and a numerical bit following the sign bit,
In the division or remainder preprocessing method for normalizing the data itself when it is a positive number and for normalizing the two's complement data when it is a negative number, if each data is negative, the The number of bits of leading "1" or the number of bits of leading "0" of its one's complement data is calculated, and whether or not there are consecutive bits of "01" in the bit string or the bit string of its one's complement data Presence / absence of consecutive bits of "10" is detected, and based on the number of bits and the presence / absence of consecutive bits, "1" is determined depending on whether the consecutive bits are "present" or "absent".
A normalization control signal having different values is generated, and the 2's complement data is normalized by the normalization control signal. 2. When generating the normalization control signal, when the detection result is “present”, the number of bits is subtracted from the bit width of the numerical bit, and when the detection result is “absent”. From the bit width, "the number of bits-
2. The preprocessing method for division or remainder according to claim 1, wherein "1" is subtracted. 3. The method according to claim 1, wherein when the data is a negative number, the number of bits of the leading “1” is obtained and the presence or absence of consecutive bits of “01” in the bit string is detected. Preconditioning method for division or remainder. 4. Complement generating means for obtaining two's complement data of each data of division object or remainder object consisting of a sign bit and a numerical bit following the sign bit, and each data is a negative number. , The number of bits of the leading "1" or the number of bits of the leading "0" of the one's complement data is determined, and the presence or absence of consecutive bits of "01" in the bit string or its one's complement data Data determining means for detecting the presence / absence of "10" consecutive bits in the bit string of the data, and the case of "present" and "absent" based on the number of bits and the presence / absence of consecutive bits. And "1"
A normalization control signal setting means for generating a normalization control signal having a different value, and a data normalization means for normalizing the two's complement data based on the normalization control signal. A preprocessing device for division or remainder characterized by the following. 5. The normalization control signal setting means subtracts the bit number from the bit width of the numerical value bit when the detection result is “present”, and when the detection result is “absent”. The subtraction or remainder preprocessing device according to claim 4, wherein "the number of bits-1" is subtracted from the bit width. 6. The data determination means obtains the number of bits of leading “1” for the negative data and detects the presence or absence of consecutive bits of “01” in the bit string. Item 4. A division or remainder preprocessing device according to item 4 or 5.