JPH07312611A - Communication apparatus involving swapping - Google Patents

Abstract

PURPOSE: To provide a device for swapping an input value to an output value in an extremely short time less than 2 microseconds by using an inexpensive memory. CONSTITUTION: A swap function for swapping an input value to an output value is executed by a pseudo associative storage device for providing an output value corresponding to an (n) bit input value equivalent to an integer E (E=2<p> -1). The pseudo associative storage device is composed of plural cascade type random access memories 20 having at least 2<d> (d>p) address capacities. A control logic circuit for setting a (p) bit pointer to each random access memory 20 is provided. Each pointer is made different from another pointer, and assigned to the input value at random.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device that allows an input value to be swapped with an output value, in particular the input value is the header of a data stream received by the communication system and the output value is An apparatus used in such a communication system, which is the header of the corresponding data stream transmitted by that communication system.
The device is also used to implement any table lookup function.

[0002]

BACKGROUND OF THE INVENTION Most communication systems include switches and links that allow data received on an input link to
It has the function of transporting the stream to the addressed output link.

Today, there is a tendency to use the so-called asynchronous transfer mode (ATM) in preparation for high speed transmission and switching in future communication networks. In this mode all data is transported as cells, each cell having a length of 53 bytes. The first 5 bytes are a header including a 12-bit VP (virtual path) field and a 16-bit VC (virtual channel) field, and include an address indicating the destination of the cell.

At the input of the switching node, the VP / VC field is replaced (swapped) by the new field and a routing header is added so that the cell is routed through the switch. The routing header is then stripped and the cell is sent to the appropriate output link.

Fast swapping of VP / VC fields is a difficult task. Because 2 ²⁸ = 268.10 ⁶
This is because the above VP / VC combination is possible, and cells must be processed in 2.5 microseconds or less at a transmission rate of 155 gigabits / second.

Therefore, it is not practical to handle all these combinations. In practice, a transport node consists of a communication adapter, one connected to a physical link and the other to a switch. Each adapter must be able to recognize approximately 2000 VP / VC fields (entries) per physical link. Therefore, if it is connected to 4 physical links, it should be able to recognize about 8000 entries.

To accomplish this function, the communication adapter includes a table that is updated by the network manager as a function of the connections established by the adapter.

As a result, 80 is searched and updated within the cell interval to perform the VP / VC swapping function.
A table with 00 entries needs to be implemented in each communication adapter.

One conventional method of implementing such a table is to use a content addressable memory.
I will provide a. Another method implements a binary search algorithm or hashing method.

The first drawback of these techniques is that the search operation takes up most of the cell processing time.
The second drawback is due to the fact that a new entry in the table has to be created in the correct location and therefore the table is not easy to update.

An example of the search algorithm is the IEEE bulletin Vo.
l. 135 No. 1 (January 1988).

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to enable a swapping function that swaps an input value to an output value within a very short time of 2 microseconds or less by using a low-cost memory. It is to provide a device to do.

Another object of the present invention is to provide such a device in which the memory can be easily updated to change the input values that are swapped.

[0014]

According to the invention, the swap function is performed by cascading look-up tables, the width of which depends on the number of entries allowed in an equivalent associative memory. Combined by path. The pointer must be set and updated in the table so that the search path is clearly marked for all possible entries.

The swap function is thus performed by a pseudo-associative memory device which provides a corresponding output value of the integer E (E = 2 ^p -1) corresponding to an n-bit input value.

The pseudo-associative memory device comprises a plurality of cascaded random address memories having an address capacity of at least 2 ^d . Here, d is larger than p.

Control logic is provided for setting the p-bit pointer in each random access memory. Each pointer is different from the other pointers and is randomly assigned to the input value. In order to find the output value corresponding to the input value, the control logic circuit
The access memory is sequentially addressed and read. The first memory is addressed by the portion containing the n1 bits of the input value and each subsequent memory is addressed by the pointer read from the preceding memory concatenated with the ni bit portion of the input value. Here, ni is np or less. The output value is found as a result of the last memory addressing.

[0018]

1 is a schematic representation of the receiving side of a communication node,
A circuit is used that swaps the input value with the output value. Obviously, such a circuit could be used in any other environment. A receiving circuit 2 for processing a bit stream received from an input link, as shown in FIG.
, Input links 1-1 through 1-4 are provided.
In the preferred application of the invention, the bit stream is arranged in cells according to the so-called asynchronous transfer mode (ATM).

One of the functions of the receiving circuit 2 is to detect the header of the cell provided to the swap circuit 4. The swap circuit 4 changes the VP / VC field included in the header into a new VP / VC field, which is inserted into the cell and transmitted by the node.

The cells are processed and routed through circuit 6, provided with a new header, and transmitted by circuit 8 onto node output links 10-1 through 10-3. The new header is provided by the circuit 4 via the bus 5. The node includes a node manager 12, one function of which is to control the swap circuit 4.

The swap circuit 4 has a VP function within the cell processing time.
/ X which provides the VP / VC output value corresponding to the / VC input value
It is composed of a pseudo-associative storage device that functions as an entry table.

In the preferred embodiment of the invention, the input value provided by the receiver circuit 2 via the bus 14 comprises a 28-bit VP / VC field of the ATM cell and an additional 5 bits, the latter of which is the input link. It includes additional information such as physical address and control information indicating how to handle the cell.

The swap circuit 4 is shown in FIG. It consists of a memory structure 20 and control logic 22 which functions as a pseudo-associative memory device.

As mentioned above, assuming that the input value contains 33 bits and 2 ¹³ input tables are required, the memory organization is 3 random access memories 2.
4-A, 24-B and 24-C.

The largest readily available random access memory (RAM) today is 16 megabit dynamic RAM (DRAM). Various configurations are possible. Most vendors of such DRAM devices provide 1 Mbit × 16 configured devices suitable for the present invention. All modern DRAMs implement a CAS (column address select) before RAS (row address select) mechanism, allowing direct device refresh. Since the DRAM refresh operation requires only a timer and there is only one memory inquiry per received cell, there is sufficient time between two cells to perform the memory refresh operation without interfering with normal operation. Exists. At 155 megabits / second,
Cells are received every 2.7 microseconds.

As will be described later, four RAM accesses (each 150 nanoseconds) are required to execute the swap function, and 10% or less of the cell processing time is required to inquire the memory.

The dynamic random access memories 24-A, 24-B and 24-C are coupled through paths, the width of which corresponds to the depth or number of entries allowed in an equivalent associative memory. Therefore, assuming that a 33-bit search is required, E = 2 ¹³ −1 = 8
There are 191 possible input values and the control logic 22 has memory control lines or read / write (R / W) 28, R
Addressing memories 24-A, 24-B and 24-C sequentially by activating AS / CAS 30, 32 and 34. The R / W line 28 is common to the three memories, and there are three RAS / CAS lines corresponding to each memory represented as lines 30, 32 and 34.

First, memory 24-A is addressed via control logic 22 which provides a first portion on address bus 26 which contains the n1 bits of the input value. The 13-bit data read from memory 24-A is provided to control logic 22 via data bus 36. The control logic 22 then outputs 24-A to the second part (different from the first part), ie, the input value of ni = n2 bits.
From the memory 2 by the address added with 13 bits from
Address 4-B. The 13 bits of data read from memory 24-B are provided to control logic 22 via data bus 36, which in turn controls the third portion (different from the first and second portions). , Ie ni = n
The memory 24-C is addressed by the address obtained by adding 13 bits from 24-B to the 3-bit input value.

The 13-bit data read from memory 24-C is used to address the control block portion reserved in one of the memories, for example memory 24-A, which is memory 24-A, 24-. Contains VP / VC output values corresponding to VP / VC input values used to sequentially address B and 24-C.

Obviously, different numbers of DRAMs are required depending on the addressing function of the DRAMs, ie the number of entries and the number of bits of the input value. Those skilled in the art will understand to cascade as many DRAMs as needed for each particular application.

In the preferred embodiment of the present invention, assume that the swap function is accomplished with three DRAMs and that: That is, the input value is n bits wide. E = 2 ^p −
An associative memory with one entry is needed. Each memory has an address capacity of 2 ^d . Where d is p
Is greater than. n1 + n2 + n3 = n, ie with respect to the number of bits of the input value for which the search has to be performed,
n1 is d or less, and n2 + p and n3 + p are d or less.

Assuming d = 20 and p = 13, in the preferred embodiment of the invention, memory 24-A is addressed by an input value of n1 = 19 bits and memory 24-B is n.
Addressed by an input value of 2 = 7 bits and 13 bits read from memory 24-A, memory 24-C has n3 = 7 bits and 13 read from memory 24-B.
Addressed by bits and.

Since each memory has an address capacity of 2 ²⁰ only half of the memory 24-A is used in the search operation, the other half being the control blocks and memory needed to update the memory contents, as described below. Used to store the pointer stack.

The search path of the pointer is a pseudo-associative memory configuration 2
3 memories 2 as clearly marked at 0
Must be set and updated in 4-A, 24-B and 24-C.

To this end, three stacks SA, SB and SC of 2 ¹³ -1 different pointers are stored in the memory 24-A.
Assigned to each of the memories 24-A, 24-B and 24-C.

Adding a new entry while the pseudo-associative memory is not full is accomplished by picking a new specific pointer from the pointer stack.
If the new paths marked have a format that is totally different from all others, new pointers are pulled from each stack, emptying each of them by one.

If the new entry has something in common with the previous entry, the corresponding table must not be updated so as not to destroy the previously established path. Therefore, each time a new entry is executed in the pseudo-associative memory, a search must be performed to determine if the path has already been marked. DRAM
If either A, B, or C returns anything other than "all 0s" (indicating an empty location), then the contents must not be changed and the pointer is not removed from the corresponding stack.

The final DRAM 24-C is constantly updated unless the new path is an exact duplicate of the previous entry. In the case of an exact copy, the swap table is either replaced by a new possible value or flagged as an error to the user, depending on the particular application.

When an entry has to be erased from the pseudo-associative memory, a check must be done to make sure that the corresponding entry actually exists there. During the checking process, the pointers returned as a result of reading the memories A, B and C must be collected.

The pointer read from C is always removed and repositioned at the top of stack C, ready for immediate reuse.

The pointer read from B must not be removed if it is used by multiple passes.
Checks for this must be performed.

Finally, the pointer read from A must also be checked for multiple uses in memory B.

FIG. 4 shows these operations.
It will be described with reference to FIGS.

The control logic 22 is shown in FIG. 3, which includes a logic circuit 40, which receives circuit 2 from bus 2 to bus 1.
4 receives the modified input value, and
Control data is received from the manager 12 via the bus 16.

The logic circuit 40 is the RAS / CAS line 3
It generates memory control signals on the 0, 32, 34 and R / W lines 28, which are necessary to perform reset, update, search and erase operations of the pseudo-associative memory device 20. Logic circuit 40 also provides address bits to address forming register 43 via bus 42. In register 43, the address bits are organized as described below. In the preferred embodiment of the invention, the DR
AMs A, B and C are provided with row and column addressing schemes in which the address bits obtained from address bit forming register 43 are separated into a 12-bit row address and an 8-bit column address, respectively in row address register 44.
And a column address register 46 and further to a multiplexer 48 to provide line 50 by circuit 40.
It is output on the address bus 26 under the control of the row / column select signal generated above.

A data bus is provided to the receiver circuit 52,
The bit received from this bus is the data input register 5
4 is input. The received bit stored in the register 54 is provided to the logic circuit 40 via the bus 56. The data to be written to the selected DRAM A, B or C is provided to the data output register 60 by the circuit 40 and further written to the addressed location via the driver 62. Driver 62 is activated by a write enable signal generated by circuit 40 on line 64.

Referring to FIG. 4, a pseudo associative memory device is initiated by the node manager 12
It is shown how it is initialized during the on-reset operation.

As shown in step 70, the power
If an on-reset command is detected on bus 16, circuit 40 causes data output register 60
Are all set to 0. 3 DRAMs A, B and C
Are cleared in parallel by scanning 2 ²⁰ addresses and writing "all 0s" to each addressed location.

This is the R, as shown in step 74.
By activating the AS / CAS and R / W lines, this is accomplished by performing 2 ⁸ consecutive write operations in parallel in page mode for DRAMs A, B and C.

For each write operation, step 76 tests whether the page boundaries cross (cross page boundaries) and, if not, step 77.
The column address is incremented by 1 to continue the burst write operation. On each page cross, it is tested at step 78 if this is the last page cross, and if not, the row address is incremented at step 79, and then the RAS / CAS line is activated, D
New 2 ⁸ burst writes to RAM A, B and C are performed. If yes, the initialization operation is completed at step 80.

Next, pointer stacks SA, SB and SC must be prepared in the upper portion of DRAM 24-A.

The same processing as shown in FIG. 5 is executed for each stack SA, SB and SC. For each stack, the node manager issues a create stack command via bus 16. This is decoded by the circuit 40, as shown in step 90. This operation is part of the initialization operation. In circuit 40, in order to perform this function, three 13
A bit up / down counter is provided. One of these counters, CTN-92, is shown in FIG. 5 and is assigned to each stack. Circuit 40 produces control signals on control bus 94 to increment or decrement CTN-92,
These signals are used to perform the operations described with reference to Figures 5-11.

First, as shown in step 96, the counter 92 indicates that the first pointer value, eg, "000000000000".
Reset to 1 "and the first stack address is loaded into register 43.

Next, at step 98, DRAM-A is addressed. At step 100, the value set in up / down counter 92 is written to the addressed location of the stack and the stack address in register 43 is incremented by one.

In step 102, the up / down counter value is tested and the last pointer value, ie "111".
It is determined whether the 1111111111 "has been reached. This is indicated by the most significant 1 on the full line 103. If not, the up / down counter is incremented by 1 at step 104.
Incremented and processing resumes with step 98.

If yes, the process ends at step 106.

Referring to FIGS. 6-8, in order to mark the paths corresponding to all possible entries, the DRAM
It is shown that 24-A, 24-B and 24-C are updated.

This is accomplished through node manager 12, which issues an "update entry" xxx "" command on bus 16 as shown at step 120. Here, xxx is a 33-bit input value.

In step 122, the value of up / down counter 92 associated with stack C is tested and D
It is determined whether RAM-C is full. If yes,
This means that no new value has been added and an error or warning will be reported. If not, the 19 most significant bits (MSBs) of entry "xxx" are sent to positions 0-18 of 20-bit address formation register 43, where 0 is the position of the register, as shown in step 124. Set to 19 to address the lower portion of DRAM 24-A and read the value stored at this address.
This address value is stored.

Next, at step 126, the read value is "
All 0's are tested. If not, this means that there is already an entry containing the same 19 MSB bits and the current pointer read in step 124 is stored in the address formation register 43 in step 128. Loaded.

In the affirmative, a new pointer is fetched from stack A by addressing the location at the beginning of stack SA and reading pointer "PA", as shown in step 130. Next step 1
As shown at 32, the up / down counter 92 (named 92-A) associated with the stack SA is decremented, and at step 134 the fetched pointer P
A is written to the saved address of DRAM 24-A in step 124 and PA is loaded into locations 19 through 7 of address formation register 43.

The process continues as shown in FIG. 7, first in step 136 the next 7 bits of entry "xxx" are loaded into registers 43 at positions 6-0. Register 4
The address thus set in 3 is stored and DR
AM24-B is read.

Next, at step 138, the read value is "
All 0 "are tested. If not, this means that there is already an entry containing the same 7 bits and the current pointer read in step 136 is stored in the address formation register 43 in step 140. Loaded.

If yes, a new pointer is fetched from stack B by addressing the location at the beginning of stack SB and reading pointer "PB", as shown in step 142. Next step 1
As shown at 44, the up / down counter 92 (named 92-B) associated with stack SB is decremented and at step 144 the fetched pointer P
B is written in the address of the DRAM 24-B saved in step 136, and PB is written in the address forming register 43.
Loaded in positions 19 to 7.

The process continues as shown in FIG. 8 by first loading the remaining 7 bits of entry "xxx" into register 43, positions 6 through 0, at step 148. The address thus set in the register 43 is stored, and D
RAM 24-C is read.

Next, at step 150, the read value is "
All 0's are tested. If not, this means that an entry containing the same 7 bits already exists, and the current pointer read in step 148 is saved in step 152. Update A warning signal is sent to the node manager indicating that the path inside is already marked.

In the affirmative, a new pointer is fetched from stack C by addressing the top location of stack SC and reading pointer "PC", as shown in step 154. Next step 1
As shown at 56, the up / down counter 92 (named 92-C) associated with the stack SC is decremented, and at step 158 the fetched pointer P
C is written to the address of DRAM 24-C saved in step 148 and the PC is saved.

Next, as shown in step 160, P
The upper control block of the DRAM-24, which has an address based on C, is addressed and the output value corresponding to entry "xxx" is written to this control block.

The update process ends at step 162.

Referring now to FIG. 9, the operations performed by control logic 40 to locate the output value corresponding to the received 33-bit input value are shown.

These operations are step 17
It is initiated when a header containing a 33-bit input value is provided on bus 14, as indicated by 0.

As shown in step 172, the 19 MSB bits of the input value are loaded into locations 0-18 of address formation register 43, location 19 of the register being 0.
Is set to. The DRAM 24-A is addressed and read, and the pointer PA is returned to the logic circuit 40 via the register 54.

The PA pointer value is tested in step 174, and if it is all equal to 0, the mismatch signal is returned to processing / routing circuit 6 via line 65.

If all are not 0, step 176.
Then, the pointer PA moves to position 1 of the address formation register 43.
9 to 7 loaded, the next 7 bits of the input value are in position 6
Loaded to 0.

Next, in step 178, the DRAM 24-B is read, and in step 180, it is tested whether the pointer PB returned to the circuit 40 via the register 54 is all 0s. If all zeros, the mismatch signal is returned via line 65.

If all are not 0, in step 182,
The 3-bit pointer PB is loaded into positions 19 to 7 of register 43 and the remaining 7 bits of the input value are in register 4
3 positions 6 to 0 are loaded.

Next, at step 184, the DRAM 24-C
Is read and the pointer PC is returned to the logic circuit 40.

The value of pointer PC is tested in step 186 and if all zeros, the mismatch signal is returned via line 65.

If not all 0's, this indicates a match, the pointer value is used to address the control block in the upper portion of DRAM-A, the control block containing the output value is read out, and via output bus 64. , Processing / routing circuit 6.

Next, how the entry "yyy" is deleted will be described with reference to FIGS.

Operation begins with the receipt of an "erase entry" yyy "" command received from the node manager 12 via bus 16, as shown in step 190.

First, as shown in step 192,
By performing steps 172-184 of FIG. 9, a search operation is initiated with a 33-bit "yyy" entry. Pointers PA, PB and PC and their DRAMs 24-A, 24-B and 24-C
The address within is stored.

Next, at step 194, a test is made to see if a match is found, and if not, the erase operation ends. This is because this means that the entry "yyy" does not exist in the pseudo-associative memory.

In the affirmative, the pointer PC is written to the address pointed to by the contents of the up / down counter 92-C at the top of the stack SC, which is then incremented by one. All zeros are written to the PC address stored in step 192.

Then, as shown in step 198, the reading of DRAM 24-C begins with the concatenation of PB and 0000000 based on the pointer PB and all possible combinations of 7 bits. The pointer PC returned in each read operation is tested in step 200,
If this turns out not to be all zeros, the erase operation is complete. Because this means that pointers are still used to mark different paths. If the pointer is found all 0, is 2 ⁷ times whether it read operation was performed a test in step 202, if not, the address is incremented by 1 in step 204 and loops back to step 198.

In the affirmative, all 0's are written to the PB address saved in step 192 and PB is pushed to the stack SB.
Is written to the address indicated by the counter 92-B at the beginning of, and the counter is incremented by 1.

Then, as shown in step 208, the read of DRAM 24-B begins with the concatenation of PA and 0000000 based on the pointer PA and all possible combinations of 7 bits. The pointer PB returned in each read operation is tested in step 210,
If this turns out not to be all zeros, the erase operation is complete. Because this means that pointers are still used to mark different paths.

If the pointer is found to be all zeros, then step 212 tests to see if 2 ⁷ read operations have been performed, and if not, the address is incremented by 1 at step 208 and loops back to step 208.

In the affirmative, all zeros are written to the PA address saved in step 192 and PA is pushed to stack S.
It is written to the address indicated by the counter 92-A at the head of A, and the counter is incremented by 1.

The erase operation is now step 21.
It ends at 8.

In the preferred embodiment of the present invention, when a search operation has to be performed on a part of an input value such as a VP, the search process is performed when a match with the VP pattern of the input value is found. Ends. Depending on which part of the input value has to be searched, the search ends in step 174, 180 or 186 of FIG.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) A data communication device for providing an output value corresponding to an n-bit input value of a number corresponding to an integer E of 2 ^p -1 or less, which is 2 ^d (d is an integer such that d> p) A plurality of cascaded memories (24-
A, 24-B and 24-C) and means for setting a plurality of p-bit pointers, each of which is different from the other, in each of the above memories, and at least one of the memories. Means for sequentially addressing and reading one of the input values, the first memory being addressed by a portion of the input value that includes n1 (n1 is an integer n1 ≦ d) bits, and each subsequent memory is The input value ni
Addressing means, addressed by the pointer read from the preceding memory connected to the (ni≤n-n1) bit portion, and means for outputting the output value resulting from the addressing of the last memory in order. And a data communication device including. (2) The means for setting the p-bit pointer includes a stack of the pointers assigned to each of the memories, and a means for setting 2 ^p -1 different pointers in each stack. (1) The device according to the above. (3) The means for setting the p-bit pointer is means for sequentially addressing and writing the memory in response to the input value, and the first memory is n1 of the input value.
A bit and the pointer assigned to the first memory
Said pointer fetched from the stack and written to said address location, and said respective succeeding memory being written to said preceding memory concatenated with the ni bit portion of said input value; An apparatus according to claim (2), including write means written to an addressed location of the memory, addressed by the pointer fetched from the assigned pointer stack and written to the address location. (4) The device according to any one of (1) to (3) above, including means for erasing the pointer stored in the memory in response to an n-bit input value. (5) The erasing means is a means for sequentially addressing the memory in response to an n-bit value to be erased.
Means for addressing said memory by n1 bits of said input value, and each said subsequent memory is addressed by said pointer read from said preceding memory concatenated with the ni bit portion of said input value. And means for storing the pointers sequentially read from the memory, and writing the pointer read from the last memory to the top of the stack allocated to the memory, and the addressing location of the last memory. Means for canceling the pointer, and the pointer read from the memory other than the last memory are written at the head of the stack allocated to the memory, and the pointer corresponds to the input value that is not erased. Addressing the memory if not used to address location And means for canceling the pointer to the application, the above (4) device according. (6) The means for outputting the output value are organized in one of the memories each of which is addressed by the pointer read from the last memory and which stores the output value corresponding to the input value. The apparatus according to any one of (1) to (5) above, which includes a control block. (7) The device according to any one of (1) to (6) above, wherein the memory is a dynamic random access memory. (8) The device according to (6) or (7) above, wherein n = 33 and p = 13. (9) The device according to (8) above, wherein n1 = 20 and ni = 7. (10) The stack and the control block are the first
The device according to (6) above, which is stored in the memory.

[0094]

As described above, according to the present invention,
By using low cost memory, it is possible to provide a device that performs a swapping function that swaps an input value with an output value within a very short time of 2 microseconds or less.

[Brief description of drawings]

FIG. 1 is a diagram representing a communication node in which the present invention is implemented.

FIG. 2 is a diagram showing a swap circuit including a cascaded dynamic random access memory.

[Figure 3] Memory required to implement the swap function
It is a figure showing the control logic which controls operation.

FIG. 4 is a diagram representing operations performed by control logic to initialize memory contents.

FIG. 5 is a diagram representing operations performed by control logic to create a pointer stack.

FIG. 6 is a diagram representing operations performed by control logic to update memory contents for a new entry.

FIG. 7 is a diagram representing the operations performed by the control logic to update the memory contents for a new entry.

FIG. 8 is a diagram representing the operations performed by the control logic to update the memory contents for a new entry.

FIG. 9 is a diagram representing operations performed by control logic to obtain an output value corresponding to an input value.

FIG. 10 is a diagram representing the operations performed by the control logic to erase an entry.

FIG. 11 is a diagram representing the operations performed by the control logic to erase an entry.

[Explanation of symbols]

 2 reception circuit 4 swap circuit 5, 14 bus 6 cell circuit 8 circuit 12 node manager 20 memory configuration 22 control logic 26 address bus 28 read / write (RW) 30, 32, 34 RAS / CAS 50, 64 lines 52 receiver circuit 54 data input register 60 data output register 62 driver 92 up / down counter

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Francois Carmalec France 06600, Antibes, Impas de la Brague, Magda Cottage Cii (no street number) (72) Inventor Eric Larmando France 06610, La・ Gaude, Shemin de Vallestretch 57, Mas Kabli (no address) (72) Inventor Tan Ham France 06600, Antibes, Shemin Des Conves 120 (72) Inventor Hans Rudolf Schindler Switzerland, See-h-8135 Runau am Albis, Wildenbuillers Truss 40

Claims (10)

[Claims] 1. A data communication device for providing an output value corresponding to an n-bit input value of a number corresponding to an integer E of 2 ^p -1 or less, wherein an address of 2 ^d (d is an integer d> p). A plurality of cascading memories having a capacity, a means for setting a plurality of p-bit pointers, each of which is different from the other, to one of the input values, and at least one of the memories. Means for sequentially addressing and reading, wherein the first memory is n1 of the input values.
(N1 is an integer n1 ≦ d) bits, and each subsequent memory is read from a preceding memory concatenated with a ni (ni ≦ n−n1) bit part of the input value. A data communication device comprising: addressing means addressed by a pointer; and means for outputting an output value resulting from the addressing of the last memory in order. 2. A means for setting the p-bit pointer comprises a stack of the pointers assigned to each of the memories, and a means for setting 2 ^p -1 different pointers in each of the stacks. The device according to claim 1. 3. The means for setting the p-bit pointer is means for sequentially addressing and writing the memory in response to the input value, the first memory being n of the input value.
1 bit and written to the address location by the pointer fetched from the pointer stack assigned to the first memory, and each succeeding memory is ni bits of the input value. Write to the address location addressed by the pointer written to the preceding memory that is concatenated with the part and the pointer fetched from the pointer stack that is written to the addressed location of the memory. 3. The device of claim 2 including writing means provided. 4. An apparatus according to claim 1, including means for erasing the pointer stored in the memory in response to an n-bit input value. 5. The erase means is means for sequentially addressing the memory in response to an n-bit value being erased, the first memory being addressed by n1 bits of the input value. Each subsequent memory is addressed by the pointer read from the preceding memory concatenated with the ni-bit portion of the input value, and means for storing the pointer sequentially read from the memory. Means for writing the pointer read from the last memory to the top of the stack allocated to the memory, canceling the pointer indicating the last addressing location of the memory, and excluding the last memory Write the pointer read from the memory to the top of the stack allocated to the memory, 5. The apparatus of claim 4, further comprising: means for canceling the pointer to the addressed location of the memory if is not used to address a location corresponding to the input value that is not erased. 6. The means for outputting the output value is organized in one of the memories, each of which is addressed by the pointer read from the last memory and stores the output value corresponding to the input value. 6. The apparatus according to any of claims 1-5, including a control block that is implemented. 7. The apparatus according to claim 1, wherein the memory is a dynamic random access memory. 8. The device according to claim 6, wherein n = 33 and p = 13. 9. The apparatus according to claim 8, wherein n1 = 20 and ni = 7. 10. The apparatus of claim 6, wherein the stack and the control block are stored in the first memory.