JPH07312410A - Parallel connection structure of flat type semiconductor switch - Google Patents

Abstract

PURPOSE:To reduce the operation time difference of semiconductor switches, by reducing the wiring inductance of each control electrode, when a plurality of semiconductor switches are connected in parallel. CONSTITUTION:A first electrode 21 of each semiconductor switch is bought into contact with first plate-like conductor 11. Belt-like conductor 41 for a second electrode 22 is brought into contact with the second electrode 22 formed on the surface opposite to the first electrode 21. A third electrode 23 is brought into contact with a thin film conductor 31 for the third electrode 22. The second electrode conductor 41 and the third electrode conductor 31 are stacked, interposing wide thin film-like insulator 51, i.e., a multilayer structure is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel connection structure of flat semiconductor switches in which a plurality of flat structure semiconductor switches are connected in parallel and each semiconductor switch can be turned on and off at high speed without causing a time difference.

[0002]

2. Description of the Related Art If a semiconductor switch is used, it is possible to easily and smoothly convert power from direct current to alternating current and convert alternating current to direct current. However, since the capacity of the semiconductor switch is limited and the power to be converted is also restricted, the capacity of the converted power is increased by increasing the capacity of the semiconductor switch alone or connecting a large number of semiconductor switches in parallel. .

FIG. 5 is a circuit diagram showing a general example of a circuit in which a plurality of semiconductor switches are connected in parallel.
The circuit of FIG. 6 has three semiconductor switches (2a, 2a) shown in FIG.
b, 2c) The case of parallel connection is illustrated. That is, the drain electrodes 2D of the respective semiconductor switches are commonly connected by the drain line 6, and the source electrodes 2S are commonly connected by the source line 7. When performing power conversion, it is necessary to turn on / off each semiconductor switch at the same time. Therefore, the gate electrodes 2G of each semiconductor switch 2 are commonly connected by the gate line 8, and the gate line 8 and the source line described above are connected. 7 and 7 are connected to the gate drive circuit 5. When the gate drive circuit 5 applies an on-voltage between the gate and the source of each semiconductor switch and causes an on-current to flow from the gate electrode to the source electrode, all of these semiconductor switches are turned on all at once and the application of the on-voltage is stopped. Alternatively, when a reverse voltage is applied and an off current is passed from the source electrode to the gate electrode, all the semiconductor switches are turned off all at once.

[0004]

If the gate drive circuit 5 and the semiconductor switches 2a, 2b, 2c are in the positional relationship shown in FIG. 5 described above, the gate drive circuit 5 is connected to the gate electrodes of the semiconductor switch 2b. The length of the gate line 8 from the gate drive circuit 5 to the semiconductor switch 2a
Of the gate line 8 from the gate drive circuit 5 to the semiconductor switch 2c.

For example, if the length of the gate line 8 connecting the gate electrodes of each semiconductor switch is several tens cm, the wiring inductance L of the gate line and the source line is several hundreds nH. On the other hand, the capacitance C of the gate of a semiconductor switch having a large capacity such as several hundreds of volts and several hundreds of amperes is about several hundreds nF. The transmission delay time of the signal (ON current) from the gate drive circuit 5 to each gate pole is determined by the line inductance L described above.
Is approximately equal to the square root of the product of the gate capacitance C. Therefore, when a plurality of semiconductor switches are connected in parallel, the signal transmission delay time becomes several hundred nanoseconds when the inductance L and the gate capacitance C of the gate wiring are the above-mentioned values.

That is, in the semiconductor switch parallel connection circuit shown in FIG. 5, the semiconductor switch 2a and the semiconductor switch 2c have a difference in signal transmission time due to the influence of the inductance. There is a time difference of several hundreds of nanoseconds or more in the on / off operation with respect to 2a and 2c. Since the current is concentrated in the semiconductor switch that is turned off after the transition from the on state to the off state, the turn-off loss is concentrated in the semiconductor switch. Also, when the off-state shifts to the on-state, turn-on loss concentrates on the semiconductor switch that turns on quickly.

If there is a time difference between the ON / OFF operations as described above, the loss is concentrated on a specific semiconductor switch, so that it becomes meaningless to connect a large number of semiconductor switches in parallel, and the semiconductor switches are connected in parallel. Even so, the converted power does not increase so much. Therefore, if an attempt is made to increase the size of the gate wiring to reduce its inductance, a large wiring space is required, and a large space is required to connect a thick wiring. Also, it is not easy to connect thick wiring. Furthermore, since the inductance of the main circuit conductor (that is, the anode-side conductor and the cathode-side conductor) of the high-power semiconductor switch must also be reduced, it is not allowed to provide a space for passing useless magnetic flux around the semiconductor switch. Therefore, it is difficult to secure a space for screw tightening work or soldering work for connecting the conductors.

An object of the present invention is to reduce the wiring inductance between the control electrodes when a plurality of semiconductor switches are connected in parallel to reduce the operating time difference between the semiconductor switches.

[0009]

In order to achieve the above object, according to the present invention, when a plurality of flat structure semiconductor switches are connected in parallel, the first electrode of each semiconductor switch is a plate-shaped first conductor. And a strip-shaped second electrode conductor is brought into contact with each second electrode provided on the surface opposite to the first electrode, and each third electrode and a film-shaped third electrode conductor are provided. Although they are brought into contact with each other, a wide and thin strip-shaped insulator is interposed between the second electrode conductor and the third electrode conductor to form a layered structure, that is, a so-called laminated structure.

Alternatively, the second electrode conductors and the third electrode conductors are bent through the film-shaped insulator and alternately stacked, and a second electrode conductor is provided with a second surface on the side opposite to the strip-shaped portion. The structure is such that the conductor for three electrodes is exposed.

[0011]

By constructing the second and third electrode conductors as described above, the inductance of the third electrode conductor becomes smaller by two digits or more than that of the conventional one.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing the configuration of the present invention similarly to FIG. 5, in which a plurality of semiconductor switches 20 shown in FIG. 3 are connected in parallel. The difference from FIG. 5 is that the drain conductor 1 has a plane for connection of the drain, source, and gate poles.
1, the source conductor 41, and the gate conductor 31. The source conductor 41 and the gate conductor 31 have a so-called laminated structure with a film-shaped insulator 51 interposed therebetween.

FIG. 2 is a diagram showing a first embodiment of the present invention, and shows a state in which a plurality of semiconductor switches 20 having the structure shown in FIG. 3 are connected in parallel. As is apparent from FIG. 3, the drain electrode 21 of the semiconductor switch is pressed in the direction of the arrow by a pressurizing device (not shown), contacts the plate-shaped drain conductor 11 as the first conductor, and the source electrode 22 also has the arrow. The strip-shaped source conductor 41 is in contact with the directional force. Further, the gate electrode 23 is distorted by the pressing force in the direction of the arrow, and is in contact with the band-shaped gate conductor 31 by the spring force that tries to restore this strain.
Is insulated from the source conductor 41 by a thin insulator 51. Here, the source conductor 41, the gate conductor 31, and the insulator 51 form the second conductor 12.

When one semiconductor switch element uses an element having a plurality of gate poles 23 as in the first embodiment, if the gate poles 23 are driven by the same signal, the gate conductor 31 is placed at its end. By connecting the gate conductor 31 in common by the same member as the gate conductor 31, that is, by forming the gate conductor 31 in a shape commonly connected at the end, the inductance of the gate conductor is reduced to 1/2.

If the plurality of gate poles 23 behave differently by different signals, it is needless to say that other actions can be made by different signals unless connection is made at the ends of the gate conductors. In the first embodiment, the end portions of the gate conductor 31 are commonly connected, and the source conductor 41 and the gate conductor 3 are connected.
A gate drive circuit is connected between 1 and 1 to give a signal to the gate pole 23.

Since the film-shaped insulator 51 is interposed between the source conductor 41 and the gate conductor 31, the inductance of the gate conductor has a smaller value than the connection by wiring. FIG. 4 is a diagram showing a second embodiment of the present invention, and shows a state in which a plurality of semiconductor switches having the structure shown in FIG. 3 are connected in parallel. In the second embodiment of FIG. 4, the source conductor 42 is composed of a slightly thick strip 42a and a film portion 42b thinner than the strip 42a, and the film portion 42b and the film gate conductor 32 are bent to form a film. The gate conductors 3 are alternately overlapped with each other via the strip-shaped insulators 52, and the gate conductor 3 is provided on the side opposite to the pressing surface of the strip portion 42a, that is, on the side where the film portion 42b is provided.
The third conductor 13 is configured such that one surface of the second conductor 2 is exposed. In addition, this overlapping portion is the semiconductor switch 20.
The same number as the number of the gate poles 23 of is provided.

Similar to the first embodiment, by applying pressure in the direction of the arrow by a pressurizing device (not shown), the strip portion 42a of the source conductor is the source pole 22, the drain conductor 11 is the drain pole 21, and the gate conductor 32. The exposed surface is the gate pole 2
Contact with 3 respectively. Further, the gate drive circuit 5 is connected between the source conductor 42 and the gate conductor 32.

In the second embodiment, the source conductor 42 has a slightly thick strip 42a and a film 42b thinner than the strip 42a.
And the film-shaped portion 42b and the film-shaped gate conductor 32 are bent and overlapped with each other via the film-shaped insulator 52, the magnetic path of the film-shaped portion 42b and the gate conductor 32 becomes long. Therefore, the magnetomotive force generated in the film-shaped portion 42b and the magnetomotive force generated in the gate conductor 32 are canceled by the gate current, and the inductance is compared with the connection by wiring or compared with the first embodiment. Is remarkable.

[0019]

According to the present invention, the on / off signal output from the gate drive circuit flows to the gate pole of the semiconductor switch through the gate conductor and the source conductor, but these gate conductor and source conductor are extremely thin. Since it is a conductor with a wide width that is closely attached via an insulator, it cancels the magnetomotive force generated by the gate current, so that even if 5 to 10 flat-structured semiconductor switches are connected in parallel, the wiring inductance Can be as small as a few nH.

Therefore, since the delay time of signal transmission due to the inductance of the gate wiring can be shortened to several tens of nanoseconds or less, the delay time can be greatly shortened as compared with the conventional wiring structure, and turn-on loss of each semiconductor switch and Turn-off loss can be reduced. As a result, the converted power can be increased almost in proportion to the number of parallel semiconductor switches.
The effect that a larger-sized power converter can be realized is obtained.

By increasing the area where the source conductor and the gate conductor are opposed to each other through the film-shaped insulator, the inductance of the gate wiring can be further reduced, so that the loss of the semiconductor switch can be further reduced. . Furthermore, when connecting a large number of semiconductor switches in parallel, they are assembled by pressure welding without screwing or soldering work, so no extra work space is required, so not only can the device be made compact, but the wiring can also be reduced. Inductance is reduced. In addition, the effect that the labor of wiring connection can be omitted is also obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of the present invention.

FIG. 2 is a diagram showing a first embodiment of the present invention.

FIG. 3 is a diagram showing a structure of a semiconductor switch used in an embodiment of the present invention.

FIG. 4 is a diagram showing a second embodiment of the present invention.

FIG. 5 is a diagram showing a conventional configuration.

FIG. 6 is a diagram showing a structure of a semiconductor switch used in a conventional example.

[Explanation of symbols]

2, 20 ... Semiconductor switch, 5 ... Gate drive circuit,
6 ... drain line, 7 ... source line, 8 ... gate line,
2D, 21 ... Drain pole, 2S, 22 ... Source pole,
2G, 23 ... Gate pole, 11 ... Drain conductor, 4
1, 42 ... Source conductor, 31, 32 ... Gate conductor,
51, 52 ... Insulator

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 23, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 1

[Correction method] Change

[Correction content]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction content]

FIG. 2 is a diagram showing a first embodiment of the present invention, and shows a state in which a plurality of semiconductor switches 20 having the structure shown in FIG. 3 are connected in parallel. As is apparent from FIG. 2, the drain electrode 21 of the semiconductor switch is pressed in the direction of the arrow by a pressurizing device (not shown), contacts the plate-shaped drain conductor 11 as the first conductor, and the source electrode 22 also has the arrow. The strip-shaped source conductor 41 is in contact with the directional force. Further, the gate electrode 23 is distorted by the pressing force in the direction of the arrow, and is in contact with the band-shaped gate conductor 31 by the spring force that tries to restore this strain.
Is insulated from the source conductor 41 by a thin insulator 51. Here, the source conductor 41, the gate conductor 31, and the insulator 51 form the second conductor 12.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0015

[Correction method] Change

[Correction content]

If the plurality of gate poles 23 behave differently by different signals, it is needless to say that other actions can be made by different signals unless connection is made at the ends of the gate conductors. In the first embodiment, the end portions of the gate conductor 31 are commonly connected, and the source conductor 41 and the gate conductor 3 are connected.
The gate drive circuit 5 is connected between the
Is giving a signal to.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

[Procedure Amendment 5]

[Document name to be corrected] Drawing

[Name of item to be corrected] Fig. 4

[Correction method] Change

[Correction content]

[Figure 4]

Claims (8)

[Claims] 1. A flat electrode having a first electrode of a semiconductor switch formed on one of its flat surfaces, and a second electrode protruding on the other flat surface, and the second electrode being insulated and electrically conductive. In a structure in which a plurality of flat semiconductor switches each including a plurality of third electrodes formed of an elastic material are connected in parallel, a plate-shaped first conductor, a belt-shaped second electrode conductor, and a plurality of film-shaped conductors A second conductor composed of a third electrode conductor corresponding to the third electrode and a film-like insulator which is separately inserted between the second electrode conductor and the third electrode conductor to insulate the two. A plurality of the flat semiconductor switches are inserted between the first conductor and the second conductor, the first electrode of each flat semiconductor switch and the first conductor are brought into contact with each other, and the second electrode of each flat semiconductor switch is provided. Contact the electrode and the conductor for the second electrode, and A plurality of third electrodes and a plurality of third electrode conductors are brought into contact with each other, and a pressure is applied between the first conductor and the third conductor to press-contact each electrode and each conductor. Parallel semiconductor switch parallel connection structure. 2. The parallel connection structure of flat type semiconductor switches according to claim 1, wherein the third electrode conductor is connected in common at the end by the same member as the third electrode conductor. Parallel connection structure of semiconductor switches. 3. A flat electrode having a first electrode of a semiconductor switch formed on one of its flat surfaces, and a second electrode formed on the other flat surface so as to project, and the second electrode is insulated and electrically conductive. In a structure in which a plurality of flat semiconductor switches having a plurality of third electrodes formed of an elastic material are connected in parallel, a plate-shaped first conductor, a band-shaped portion, and a film-shaped second conductor are provided. An electrode conductor, a film-shaped third electrode conductor corresponding to the plurality of third electrodes, and a film-shaped insulator for insulating the second electrode conductor and the third electrode conductor from each other, The film-shaped portion of the conductor for the second electrode and the conductor for the third electrode are bent and overlapped with each other through the film-shaped insulator, and are alternately overlapped with each other. A third conductor is configured such that the third electrode conductor is exposed, and a double conductor is provided between the first conductor and the third conductor. Inserting the flat semiconductor switch, contacting the first electrode and the first conductor of each flat semiconductor switch, contacting the second electrode of each flat semiconductor switch and the conductor for the second electrode, and each flat semiconductor switch The plurality of third electrodes and the plurality of third electrode conductors are separately contacted with each other, and a pressure is applied between the first conductor and the third conductor to press-contact each electrode and each conductor. Parallel connection structure of flat semiconductor switches. 4. The flat-type semiconductor switch parallel connection structure according to claim 3, wherein the third electrode conductor is connected in common at the end thereof with the same member as the third electrode conductor. Parallel connection structure of semiconductor switches. 5. The parallel connection structure of flat semiconductor switches according to claim 1, wherein the semiconductor switch is a MOSFET, the first electrode is a drain electrode, and the second electrode is a source electrode. A parallel connection structure of flat semiconductor switches, wherein the third electrode is a gate electrode. 6. The parallel connection structure for flat semiconductor switches according to claim 1, wherein the semiconductor switch is an IGBT, the first electrode is a drain electrode, and the second electrode is a source electrode. A parallel connection structure of flat semiconductor switches, wherein the third electrode is a gate electrode. 7. The parallel connection structure of flat semiconductor switches according to claim 1, wherein the semiconductor switch is a thyristor, the first electrode is an anode pole, and the second electrode is a cathode pole. A parallel connection structure of flat semiconductor switches, wherein the third electrode is a gate electrode. 8. The parallel connection structure of flat semiconductor switches according to claim 1, wherein the semiconductor switch is a bipolar transistor.
The parallel connection structure of flat semiconductor switches, wherein the first electrode is a collector electrode, the second electrode is an emitter electrode, and the third electrode is a base electrode.